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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 5078 | serge | 1 | /* |
| 2 | * Copyright 2013 Advanced Micro Devices, Inc. |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice shall be included in |
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| 12 | * all copies or substantial portions of the Software. |
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| 13 | * |
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| 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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| 18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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| 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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| 20 | * OTHER DEALINGS IN THE SOFTWARE. |
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| 21 | * |
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| 22 | * Authors: Christian König |
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| 23 | */ |
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| 24 | |||
| 25 | #include |
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| 26 | #include |
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| 27 | #include "radeon.h" |
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| 28 | #include "radeon_asic.h" |
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| 29 | #include "cikd.h" |
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| 30 | |||
| 31 | /** |
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| 32 | * uvd_v4_2_resume - memory controller programming |
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| 33 | * |
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| 34 | * @rdev: radeon_device pointer |
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| 35 | * |
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| 36 | * Let the UVD memory controller know it's offsets |
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| 37 | */ |
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| 38 | int uvd_v4_2_resume(struct radeon_device *rdev) |
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| 39 | { |
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| 40 | uint64_t addr; |
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| 41 | uint32_t size; |
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| 42 | |||
| 43 | /* programm the VCPU memory controller bits 0-27 */ |
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| 44 | addr = rdev->uvd.gpu_addr >> 3; |
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| 45 | size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 4) >> 3; |
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| 46 | WREG32(UVD_VCPU_CACHE_OFFSET0, addr); |
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| 47 | WREG32(UVD_VCPU_CACHE_SIZE0, size); |
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| 48 | |||
| 49 | addr += size; |
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| 50 | size = RADEON_UVD_STACK_SIZE >> 3; |
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| 51 | WREG32(UVD_VCPU_CACHE_OFFSET1, addr); |
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| 52 | WREG32(UVD_VCPU_CACHE_SIZE1, size); |
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| 53 | |||
| 54 | addr += size; |
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| 55 | size = RADEON_UVD_HEAP_SIZE >> 3; |
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| 56 | WREG32(UVD_VCPU_CACHE_OFFSET2, addr); |
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| 57 | WREG32(UVD_VCPU_CACHE_SIZE2, size); |
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| 58 | |||
| 59 | /* bits 28-31 */ |
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| 60 | addr = (rdev->uvd.gpu_addr >> 28) & 0xF; |
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| 61 | WREG32(UVD_LMI_ADDR_EXT, (addr << 12) | (addr << 0)); |
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| 62 | |||
| 63 | /* bits 32-39 */ |
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| 64 | addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; |
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| 65 | WREG32(UVD_LMI_EXT40_ADDR, addr | (0x9 << 16) | (0x1 << 31)); |
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| 66 | |||
| 67 | return 0; |
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| 68 | } |