Rev 1313 | Rev 1404 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
1246 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
||
3 | * Copyright 2008 Red Hat Inc. |
||
4 | * Copyright 2009 Jerome Glisse. |
||
5 | * |
||
6 | * Permission is hereby granted, free of charge, to any person obtaining a |
||
7 | * copy of this software and associated documentation files (the "Software"), |
||
8 | * to deal in the Software without restriction, including without limitation |
||
9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
||
10 | * and/or sell copies of the Software, and to permit persons to whom the |
||
11 | * Software is furnished to do so, subject to the following conditions: |
||
12 | * |
||
13 | * The above copyright notice and this permission notice shall be included in |
||
14 | * all copies or substantial portions of the Software. |
||
15 | * |
||
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
||
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
||
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
||
19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
||
20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
||
21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
||
22 | * OTHER DEALINGS IN THE SOFTWARE. |
||
23 | * |
||
24 | * Authors: Dave Airlie |
||
25 | * Alex Deucher |
||
26 | * Jerome Glisse |
||
27 | */ |
||
1403 | serge | 28 | //#include |
1246 | serge | 29 | //#include |
30 | #include "drmP.h" |
||
31 | #include "radeon.h" |
||
32 | #include "radeon_drm.h" |
||
33 | #include "rv770d.h" |
||
34 | #include "atom.h" |
||
35 | #include "avivod.h" |
||
36 | |||
37 | #define R700_PFP_UCODE_SIZE 848 |
||
38 | #define R700_PM4_UCODE_SIZE 1360 |
||
39 | |||
40 | static void rv770_gpu_init(struct radeon_device *rdev); |
||
41 | void rv770_fini(struct radeon_device *rdev); |
||
42 | |||
43 | |||
44 | /* |
||
45 | * GART |
||
46 | */ |
||
47 | int rv770_pcie_gart_enable(struct radeon_device *rdev) |
||
48 | { |
||
49 | u32 tmp; |
||
50 | int r, i; |
||
51 | |||
52 | if (rdev->gart.table.vram.robj == NULL) { |
||
53 | dev_err(rdev->dev, "No VRAM object for PCIE GART.\n"); |
||
54 | return -EINVAL; |
||
55 | } |
||
56 | r = radeon_gart_table_vram_pin(rdev); |
||
57 | if (r) |
||
58 | return r; |
||
59 | /* Setup L2 cache */ |
||
60 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
||
61 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
||
62 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
||
63 | WREG32(VM_L2_CNTL2, 0); |
||
64 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
||
65 | /* Setup TLB control */ |
||
66 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | |
||
67 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
||
68 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | |
||
69 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
||
70 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
||
71 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
||
72 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
||
73 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
||
74 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
||
75 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
||
76 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
||
77 | WREG32(VM_CONTEXT0_PAGE_TABLE_START_ADDR, rdev->mc.gtt_start >> 12); |
||
78 | WREG32(VM_CONTEXT0_PAGE_TABLE_END_ADDR, rdev->mc.gtt_end >> 12); |
||
79 | WREG32(VM_CONTEXT0_PAGE_TABLE_BASE_ADDR, rdev->gart.table_addr >> 12); |
||
80 | WREG32(VM_CONTEXT0_CNTL, ENABLE_CONTEXT | PAGE_TABLE_DEPTH(0) | |
||
81 | RANGE_PROTECTION_FAULT_ENABLE_DEFAULT); |
||
82 | WREG32(VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR, |
||
83 | (u32)(rdev->dummy_page.addr >> 12)); |
||
84 | for (i = 1; i < 7; i++) |
||
85 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
||
86 | |||
87 | r600_pcie_gart_tlb_flush(rdev); |
||
88 | rdev->gart.ready = true; |
||
89 | return 0; |
||
90 | } |
||
91 | |||
92 | void rv770_pcie_gart_disable(struct radeon_device *rdev) |
||
93 | { |
||
94 | u32 tmp; |
||
1403 | serge | 95 | int i, r; |
1246 | serge | 96 | |
97 | /* Disable all tables */ |
||
98 | for (i = 0; i < 7; i++) |
||
99 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
||
100 | |||
101 | /* Setup L2 cache */ |
||
102 | WREG32(VM_L2_CNTL, ENABLE_L2_FRAGMENT_PROCESSING | |
||
103 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
||
104 | WREG32(VM_L2_CNTL2, 0); |
||
105 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
||
106 | /* Setup TLB control */ |
||
107 | tmp = EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
||
108 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
||
109 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
||
110 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
||
111 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
||
112 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
||
113 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
||
114 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
||
115 | if (rdev->gart.table.vram.robj) { |
||
116 | // radeon_object_kunmap(rdev->gart.table.vram.robj); |
||
117 | // radeon_object_unpin(rdev->gart.table.vram.robj); |
||
118 | } |
||
119 | } |
||
120 | |||
121 | void rv770_pcie_gart_fini(struct radeon_device *rdev) |
||
122 | { |
||
123 | rv770_pcie_gart_disable(rdev); |
||
124 | // radeon_gart_table_vram_free(rdev); |
||
125 | radeon_gart_fini(rdev); |
||
126 | } |
||
127 | |||
128 | |||
129 | void rv770_agp_enable(struct radeon_device *rdev) |
||
130 | { |
||
131 | u32 tmp; |
||
132 | int i; |
||
133 | |||
134 | /* Setup L2 cache */ |
||
135 | WREG32(VM_L2_CNTL, ENABLE_L2_CACHE | ENABLE_L2_FRAGMENT_PROCESSING | |
||
136 | ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE | |
||
137 | EFFECTIVE_L2_QUEUE_SIZE(7)); |
||
138 | WREG32(VM_L2_CNTL2, 0); |
||
139 | WREG32(VM_L2_CNTL3, BANK_SELECT(0) | CACHE_UPDATE_MODE(2)); |
||
140 | /* Setup TLB control */ |
||
141 | tmp = ENABLE_L1_TLB | ENABLE_L1_FRAGMENT_PROCESSING | |
||
142 | SYSTEM_ACCESS_MODE_NOT_IN_SYS | |
||
143 | SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU | |
||
144 | EFFECTIVE_L1_TLB_SIZE(5) | EFFECTIVE_L1_QUEUE_SIZE(5); |
||
145 | WREG32(MC_VM_MD_L1_TLB0_CNTL, tmp); |
||
146 | WREG32(MC_VM_MD_L1_TLB1_CNTL, tmp); |
||
147 | WREG32(MC_VM_MD_L1_TLB2_CNTL, tmp); |
||
148 | WREG32(MC_VM_MB_L1_TLB0_CNTL, tmp); |
||
149 | WREG32(MC_VM_MB_L1_TLB1_CNTL, tmp); |
||
150 | WREG32(MC_VM_MB_L1_TLB2_CNTL, tmp); |
||
151 | WREG32(MC_VM_MB_L1_TLB3_CNTL, tmp); |
||
152 | for (i = 0; i < 7; i++) |
||
153 | WREG32(VM_CONTEXT0_CNTL + (i * 4), 0); |
||
154 | } |
||
155 | |||
156 | static void rv770_mc_program(struct radeon_device *rdev) |
||
157 | { |
||
158 | struct rv515_mc_save save; |
||
159 | u32 tmp; |
||
160 | int i, j; |
||
161 | |||
162 | /* Initialize HDP */ |
||
163 | for (i = 0, j = 0; i < 32; i++, j += 0x18) { |
||
164 | WREG32((0x2c14 + j), 0x00000000); |
||
165 | WREG32((0x2c18 + j), 0x00000000); |
||
166 | WREG32((0x2c1c + j), 0x00000000); |
||
167 | WREG32((0x2c20 + j), 0x00000000); |
||
168 | WREG32((0x2c24 + j), 0x00000000); |
||
169 | } |
||
170 | WREG32(HDP_REG_COHERENCY_FLUSH_CNTL, 0); |
||
171 | |||
172 | rv515_mc_stop(rdev, &save); |
||
173 | if (r600_mc_wait_for_idle(rdev)) { |
||
174 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
||
175 | } |
||
176 | /* Lockout access through VGA aperture*/ |
||
177 | WREG32(VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); |
||
178 | /* Update configuration */ |
||
179 | if (rdev->flags & RADEON_IS_AGP) { |
||
180 | if (rdev->mc.vram_start < rdev->mc.gtt_start) { |
||
181 | /* VRAM before AGP */ |
||
182 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
||
183 | rdev->mc.vram_start >> 12); |
||
184 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
||
185 | rdev->mc.gtt_end >> 12); |
||
186 | } else { |
||
187 | /* VRAM after AGP */ |
||
188 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
||
189 | rdev->mc.gtt_start >> 12); |
||
190 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
||
191 | rdev->mc.vram_end >> 12); |
||
192 | } |
||
193 | } else { |
||
194 | WREG32(MC_VM_SYSTEM_APERTURE_LOW_ADDR, |
||
195 | rdev->mc.vram_start >> 12); |
||
196 | WREG32(MC_VM_SYSTEM_APERTURE_HIGH_ADDR, |
||
197 | rdev->mc.vram_end >> 12); |
||
198 | } |
||
199 | WREG32(MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR, 0); |
||
200 | tmp = ((rdev->mc.vram_end >> 24) & 0xFFFF) << 16; |
||
201 | tmp |= ((rdev->mc.vram_start >> 24) & 0xFFFF); |
||
202 | WREG32(MC_VM_FB_LOCATION, tmp); |
||
203 | WREG32(HDP_NONSURFACE_BASE, (rdev->mc.vram_start >> 8)); |
||
204 | WREG32(HDP_NONSURFACE_INFO, (2 << 7)); |
||
205 | WREG32(HDP_NONSURFACE_SIZE, (rdev->mc.mc_vram_size - 1) | 0x3FF); |
||
206 | if (rdev->flags & RADEON_IS_AGP) { |
||
207 | WREG32(MC_VM_AGP_TOP, rdev->mc.gtt_end >> 16); |
||
208 | WREG32(MC_VM_AGP_BOT, rdev->mc.gtt_start >> 16); |
||
209 | WREG32(MC_VM_AGP_BASE, rdev->mc.agp_base >> 22); |
||
210 | } else { |
||
211 | WREG32(MC_VM_AGP_BASE, 0); |
||
212 | WREG32(MC_VM_AGP_TOP, 0x0FFFFFFF); |
||
213 | WREG32(MC_VM_AGP_BOT, 0x0FFFFFFF); |
||
214 | } |
||
215 | if (r600_mc_wait_for_idle(rdev)) { |
||
216 | dev_warn(rdev->dev, "Wait for MC idle timedout !\n"); |
||
217 | } |
||
218 | rv515_mc_resume(rdev, &save); |
||
219 | /* we need to own VRAM, so turn off the VGA renderer here |
||
220 | * to stop it overwriting our objects */ |
||
221 | rv515_vga_render_disable(rdev); |
||
222 | } |
||
223 | |||
224 | |||
225 | /* |
||
226 | * CP. |
||
227 | */ |
||
228 | void r700_cp_stop(struct radeon_device *rdev) |
||
229 | { |
||
230 | WREG32(CP_ME_CNTL, (CP_ME_HALT | CP_PFP_HALT)); |
||
231 | } |
||
232 | |||
1403 | serge | 233 | #if 0 |
1246 | serge | 234 | static int rv770_cp_load_microcode(struct radeon_device *rdev) |
235 | { |
||
236 | const __be32 *fw_data; |
||
237 | int i; |
||
238 | |||
239 | if (!rdev->me_fw || !rdev->pfp_fw) |
||
240 | return -EINVAL; |
||
241 | |||
242 | r700_cp_stop(rdev); |
||
243 | WREG32(CP_RB_CNTL, RB_NO_UPDATE | (15 << 8) | (3 << 0)); |
||
244 | |||
245 | /* Reset cp */ |
||
246 | WREG32(GRBM_SOFT_RESET, SOFT_RESET_CP); |
||
247 | RREG32(GRBM_SOFT_RESET); |
||
248 | mdelay(15); |
||
249 | WREG32(GRBM_SOFT_RESET, 0); |
||
250 | |||
251 | fw_data = (const __be32 *)rdev->pfp_fw->data; |
||
252 | WREG32(CP_PFP_UCODE_ADDR, 0); |
||
253 | for (i = 0; i < R700_PFP_UCODE_SIZE; i++) |
||
254 | WREG32(CP_PFP_UCODE_DATA, be32_to_cpup(fw_data++)); |
||
255 | WREG32(CP_PFP_UCODE_ADDR, 0); |
||
256 | |||
257 | fw_data = (const __be32 *)rdev->me_fw->data; |
||
258 | WREG32(CP_ME_RAM_WADDR, 0); |
||
259 | for (i = 0; i < R700_PM4_UCODE_SIZE; i++) |
||
260 | WREG32(CP_ME_RAM_DATA, be32_to_cpup(fw_data++)); |
||
261 | |||
262 | WREG32(CP_PFP_UCODE_ADDR, 0); |
||
263 | WREG32(CP_ME_RAM_WADDR, 0); |
||
264 | WREG32(CP_ME_RAM_RADDR, 0); |
||
265 | return 0; |
||
266 | } |
||
267 | |||
1403 | serge | 268 | #endif |
1246 | serge | 269 | |
270 | /* |
||
271 | * Core functions |
||
272 | */ |
||
273 | static u32 r700_get_tile_pipe_to_backend_map(u32 num_tile_pipes, |
||
274 | u32 num_backends, |
||
275 | u32 backend_disable_mask) |
||
276 | { |
||
277 | u32 backend_map = 0; |
||
278 | u32 enabled_backends_mask; |
||
279 | u32 enabled_backends_count; |
||
280 | u32 cur_pipe; |
||
281 | u32 swizzle_pipe[R7XX_MAX_PIPES]; |
||
282 | u32 cur_backend; |
||
283 | u32 i; |
||
284 | |||
285 | if (num_tile_pipes > R7XX_MAX_PIPES) |
||
286 | num_tile_pipes = R7XX_MAX_PIPES; |
||
287 | if (num_tile_pipes < 1) |
||
288 | num_tile_pipes = 1; |
||
289 | if (num_backends > R7XX_MAX_BACKENDS) |
||
290 | num_backends = R7XX_MAX_BACKENDS; |
||
291 | if (num_backends < 1) |
||
292 | num_backends = 1; |
||
293 | |||
294 | enabled_backends_mask = 0; |
||
295 | enabled_backends_count = 0; |
||
296 | for (i = 0; i < R7XX_MAX_BACKENDS; ++i) { |
||
297 | if (((backend_disable_mask >> i) & 1) == 0) { |
||
298 | enabled_backends_mask |= (1 << i); |
||
299 | ++enabled_backends_count; |
||
300 | } |
||
301 | if (enabled_backends_count == num_backends) |
||
302 | break; |
||
303 | } |
||
304 | |||
305 | if (enabled_backends_count == 0) { |
||
306 | enabled_backends_mask = 1; |
||
307 | enabled_backends_count = 1; |
||
308 | } |
||
309 | |||
310 | if (enabled_backends_count != num_backends) |
||
311 | num_backends = enabled_backends_count; |
||
312 | |||
313 | memset((uint8_t *)&swizzle_pipe[0], 0, sizeof(u32) * R7XX_MAX_PIPES); |
||
314 | switch (num_tile_pipes) { |
||
315 | case 1: |
||
316 | swizzle_pipe[0] = 0; |
||
317 | break; |
||
318 | case 2: |
||
319 | swizzle_pipe[0] = 0; |
||
320 | swizzle_pipe[1] = 1; |
||
321 | break; |
||
322 | case 3: |
||
323 | swizzle_pipe[0] = 0; |
||
324 | swizzle_pipe[1] = 2; |
||
325 | swizzle_pipe[2] = 1; |
||
326 | break; |
||
327 | case 4: |
||
328 | swizzle_pipe[0] = 0; |
||
329 | swizzle_pipe[1] = 2; |
||
330 | swizzle_pipe[2] = 3; |
||
331 | swizzle_pipe[3] = 1; |
||
332 | break; |
||
333 | case 5: |
||
334 | swizzle_pipe[0] = 0; |
||
335 | swizzle_pipe[1] = 2; |
||
336 | swizzle_pipe[2] = 4; |
||
337 | swizzle_pipe[3] = 1; |
||
338 | swizzle_pipe[4] = 3; |
||
339 | break; |
||
340 | case 6: |
||
341 | swizzle_pipe[0] = 0; |
||
342 | swizzle_pipe[1] = 2; |
||
343 | swizzle_pipe[2] = 4; |
||
344 | swizzle_pipe[3] = 5; |
||
345 | swizzle_pipe[4] = 3; |
||
346 | swizzle_pipe[5] = 1; |
||
347 | break; |
||
348 | case 7: |
||
349 | swizzle_pipe[0] = 0; |
||
350 | swizzle_pipe[1] = 2; |
||
351 | swizzle_pipe[2] = 4; |
||
352 | swizzle_pipe[3] = 6; |
||
353 | swizzle_pipe[4] = 3; |
||
354 | swizzle_pipe[5] = 1; |
||
355 | swizzle_pipe[6] = 5; |
||
356 | break; |
||
357 | case 8: |
||
358 | swizzle_pipe[0] = 0; |
||
359 | swizzle_pipe[1] = 2; |
||
360 | swizzle_pipe[2] = 4; |
||
361 | swizzle_pipe[3] = 6; |
||
362 | swizzle_pipe[4] = 3; |
||
363 | swizzle_pipe[5] = 1; |
||
364 | swizzle_pipe[6] = 7; |
||
365 | swizzle_pipe[7] = 5; |
||
366 | break; |
||
367 | } |
||
368 | |||
369 | cur_backend = 0; |
||
370 | for (cur_pipe = 0; cur_pipe < num_tile_pipes; ++cur_pipe) { |
||
371 | while (((1 << cur_backend) & enabled_backends_mask) == 0) |
||
372 | cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; |
||
373 | |||
374 | backend_map |= (u32)(((cur_backend & 3) << (swizzle_pipe[cur_pipe] * 2))); |
||
375 | |||
376 | cur_backend = (cur_backend + 1) % R7XX_MAX_BACKENDS; |
||
377 | } |
||
378 | |||
379 | return backend_map; |
||
380 | } |
||
381 | |||
382 | static void rv770_gpu_init(struct radeon_device *rdev) |
||
383 | { |
||
384 | int i, j, num_qd_pipes; |
||
385 | u32 sx_debug_1; |
||
386 | u32 smx_dc_ctl0; |
||
387 | u32 num_gs_verts_per_thread; |
||
388 | u32 vgt_gs_per_es; |
||
389 | u32 gs_prim_buffer_depth = 0; |
||
390 | u32 sq_ms_fifo_sizes; |
||
391 | u32 sq_config; |
||
392 | u32 sq_thread_resource_mgmt; |
||
393 | u32 hdp_host_path_cntl; |
||
394 | u32 sq_dyn_gpr_size_simd_ab_0; |
||
395 | u32 backend_map; |
||
396 | u32 gb_tiling_config = 0; |
||
397 | u32 cc_rb_backend_disable = 0; |
||
398 | u32 cc_gc_shader_pipe_config = 0; |
||
399 | u32 mc_arb_ramcfg; |
||
400 | u32 db_debug4; |
||
401 | |||
402 | /* setup chip specs */ |
||
403 | switch (rdev->family) { |
||
404 | case CHIP_RV770: |
||
405 | rdev->config.rv770.max_pipes = 4; |
||
406 | rdev->config.rv770.max_tile_pipes = 8; |
||
407 | rdev->config.rv770.max_simds = 10; |
||
408 | rdev->config.rv770.max_backends = 4; |
||
409 | rdev->config.rv770.max_gprs = 256; |
||
410 | rdev->config.rv770.max_threads = 248; |
||
411 | rdev->config.rv770.max_stack_entries = 512; |
||
412 | rdev->config.rv770.max_hw_contexts = 8; |
||
413 | rdev->config.rv770.max_gs_threads = 16 * 2; |
||
414 | rdev->config.rv770.sx_max_export_size = 128; |
||
415 | rdev->config.rv770.sx_max_export_pos_size = 16; |
||
416 | rdev->config.rv770.sx_max_export_smx_size = 112; |
||
417 | rdev->config.rv770.sq_num_cf_insts = 2; |
||
418 | |||
419 | rdev->config.rv770.sx_num_of_sets = 7; |
||
420 | rdev->config.rv770.sc_prim_fifo_size = 0xF9; |
||
421 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
||
422 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
||
423 | break; |
||
424 | case CHIP_RV730: |
||
425 | rdev->config.rv770.max_pipes = 2; |
||
426 | rdev->config.rv770.max_tile_pipes = 4; |
||
427 | rdev->config.rv770.max_simds = 8; |
||
428 | rdev->config.rv770.max_backends = 2; |
||
429 | rdev->config.rv770.max_gprs = 128; |
||
430 | rdev->config.rv770.max_threads = 248; |
||
431 | rdev->config.rv770.max_stack_entries = 256; |
||
432 | rdev->config.rv770.max_hw_contexts = 8; |
||
433 | rdev->config.rv770.max_gs_threads = 16 * 2; |
||
434 | rdev->config.rv770.sx_max_export_size = 256; |
||
435 | rdev->config.rv770.sx_max_export_pos_size = 32; |
||
436 | rdev->config.rv770.sx_max_export_smx_size = 224; |
||
437 | rdev->config.rv770.sq_num_cf_insts = 2; |
||
438 | |||
439 | rdev->config.rv770.sx_num_of_sets = 7; |
||
440 | rdev->config.rv770.sc_prim_fifo_size = 0xf9; |
||
441 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
||
442 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
||
443 | if (rdev->config.rv770.sx_max_export_pos_size > 16) { |
||
444 | rdev->config.rv770.sx_max_export_pos_size -= 16; |
||
445 | rdev->config.rv770.sx_max_export_smx_size += 16; |
||
446 | } |
||
447 | break; |
||
448 | case CHIP_RV710: |
||
449 | rdev->config.rv770.max_pipes = 2; |
||
450 | rdev->config.rv770.max_tile_pipes = 2; |
||
451 | rdev->config.rv770.max_simds = 2; |
||
452 | rdev->config.rv770.max_backends = 1; |
||
453 | rdev->config.rv770.max_gprs = 256; |
||
454 | rdev->config.rv770.max_threads = 192; |
||
455 | rdev->config.rv770.max_stack_entries = 256; |
||
456 | rdev->config.rv770.max_hw_contexts = 4; |
||
457 | rdev->config.rv770.max_gs_threads = 8 * 2; |
||
458 | rdev->config.rv770.sx_max_export_size = 128; |
||
459 | rdev->config.rv770.sx_max_export_pos_size = 16; |
||
460 | rdev->config.rv770.sx_max_export_smx_size = 112; |
||
461 | rdev->config.rv770.sq_num_cf_insts = 1; |
||
462 | |||
463 | rdev->config.rv770.sx_num_of_sets = 7; |
||
464 | rdev->config.rv770.sc_prim_fifo_size = 0x40; |
||
465 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
||
466 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
||
467 | break; |
||
468 | case CHIP_RV740: |
||
469 | rdev->config.rv770.max_pipes = 4; |
||
470 | rdev->config.rv770.max_tile_pipes = 4; |
||
471 | rdev->config.rv770.max_simds = 8; |
||
472 | rdev->config.rv770.max_backends = 4; |
||
473 | rdev->config.rv770.max_gprs = 256; |
||
474 | rdev->config.rv770.max_threads = 248; |
||
475 | rdev->config.rv770.max_stack_entries = 512; |
||
476 | rdev->config.rv770.max_hw_contexts = 8; |
||
477 | rdev->config.rv770.max_gs_threads = 16 * 2; |
||
478 | rdev->config.rv770.sx_max_export_size = 256; |
||
479 | rdev->config.rv770.sx_max_export_pos_size = 32; |
||
480 | rdev->config.rv770.sx_max_export_smx_size = 224; |
||
481 | rdev->config.rv770.sq_num_cf_insts = 2; |
||
482 | |||
483 | rdev->config.rv770.sx_num_of_sets = 7; |
||
484 | rdev->config.rv770.sc_prim_fifo_size = 0x100; |
||
485 | rdev->config.rv770.sc_hiz_tile_fifo_size = 0x30; |
||
486 | rdev->config.rv770.sc_earlyz_tile_fifo_fize = 0x130; |
||
487 | |||
488 | if (rdev->config.rv770.sx_max_export_pos_size > 16) { |
||
489 | rdev->config.rv770.sx_max_export_pos_size -= 16; |
||
490 | rdev->config.rv770.sx_max_export_smx_size += 16; |
||
491 | } |
||
492 | break; |
||
493 | default: |
||
494 | break; |
||
495 | } |
||
496 | |||
497 | /* Initialize HDP */ |
||
498 | j = 0; |
||
499 | for (i = 0; i < 32; i++) { |
||
500 | WREG32((0x2c14 + j), 0x00000000); |
||
501 | WREG32((0x2c18 + j), 0x00000000); |
||
502 | WREG32((0x2c1c + j), 0x00000000); |
||
503 | WREG32((0x2c20 + j), 0x00000000); |
||
504 | WREG32((0x2c24 + j), 0x00000000); |
||
505 | j += 0x18; |
||
506 | } |
||
507 | |||
508 | WREG32(GRBM_CNTL, GRBM_READ_TIMEOUT(0xff)); |
||
509 | |||
510 | /* setup tiling, simd, pipe config */ |
||
511 | mc_arb_ramcfg = RREG32(MC_ARB_RAMCFG); |
||
512 | |||
513 | switch (rdev->config.rv770.max_tile_pipes) { |
||
514 | case 1: |
||
515 | gb_tiling_config |= PIPE_TILING(0); |
||
516 | break; |
||
517 | case 2: |
||
518 | gb_tiling_config |= PIPE_TILING(1); |
||
519 | break; |
||
520 | case 4: |
||
521 | gb_tiling_config |= PIPE_TILING(2); |
||
522 | break; |
||
523 | case 8: |
||
524 | gb_tiling_config |= PIPE_TILING(3); |
||
525 | break; |
||
526 | default: |
||
527 | break; |
||
528 | } |
||
529 | |||
530 | if (rdev->family == CHIP_RV770) |
||
531 | gb_tiling_config |= BANK_TILING(1); |
||
532 | else |
||
1268 | serge | 533 | gb_tiling_config |= BANK_TILING((mc_arb_ramcfg & NOOFBANK_MASK) >> NOOFBANK_SHIFT); |
1246 | serge | 534 | |
535 | gb_tiling_config |= GROUP_SIZE(0); |
||
536 | |||
1268 | serge | 537 | if (((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT) > 3) { |
1246 | serge | 538 | gb_tiling_config |= ROW_TILING(3); |
539 | gb_tiling_config |= SAMPLE_SPLIT(3); |
||
540 | } else { |
||
541 | gb_tiling_config |= |
||
542 | ROW_TILING(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); |
||
543 | gb_tiling_config |= |
||
544 | SAMPLE_SPLIT(((mc_arb_ramcfg & NOOFROWS_MASK) >> NOOFROWS_SHIFT)); |
||
545 | } |
||
546 | |||
547 | gb_tiling_config |= BANK_SWAPS(1); |
||
548 | |||
549 | backend_map = r700_get_tile_pipe_to_backend_map(rdev->config.rv770.max_tile_pipes, |
||
550 | rdev->config.rv770.max_backends, |
||
551 | (0xff << rdev->config.rv770.max_backends) & 0xff); |
||
552 | gb_tiling_config |= BACKEND_MAP(backend_map); |
||
553 | |||
554 | cc_gc_shader_pipe_config = |
||
555 | INACTIVE_QD_PIPES((R7XX_MAX_PIPES_MASK << rdev->config.rv770.max_pipes) & R7XX_MAX_PIPES_MASK); |
||
556 | cc_gc_shader_pipe_config |= |
||
557 | INACTIVE_SIMDS((R7XX_MAX_SIMDS_MASK << rdev->config.rv770.max_simds) & R7XX_MAX_SIMDS_MASK); |
||
558 | |||
559 | cc_rb_backend_disable = |
||
560 | BACKEND_DISABLE((R7XX_MAX_BACKENDS_MASK << rdev->config.rv770.max_backends) & R7XX_MAX_BACKENDS_MASK); |
||
561 | |||
562 | WREG32(GB_TILING_CONFIG, gb_tiling_config); |
||
563 | WREG32(DCP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
||
564 | WREG32(HDP_TILING_CONFIG, (gb_tiling_config & 0xffff)); |
||
565 | |||
566 | WREG32(CC_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
||
567 | WREG32(CC_GC_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
||
568 | WREG32(GC_USER_SHADER_PIPE_CONFIG, cc_gc_shader_pipe_config); |
||
569 | |||
570 | WREG32(CC_SYS_RB_BACKEND_DISABLE, cc_rb_backend_disable); |
||
571 | WREG32(CGTS_SYS_TCC_DISABLE, 0); |
||
572 | WREG32(CGTS_TCC_DISABLE, 0); |
||
573 | WREG32(CGTS_USER_SYS_TCC_DISABLE, 0); |
||
574 | WREG32(CGTS_USER_TCC_DISABLE, 0); |
||
575 | |||
576 | num_qd_pipes = |
||
577 | R7XX_MAX_BACKENDS - r600_count_pipe_bits(cc_gc_shader_pipe_config & INACTIVE_QD_PIPES_MASK); |
||
578 | WREG32(VGT_OUT_DEALLOC_CNTL, (num_qd_pipes * 4) & DEALLOC_DIST_MASK); |
||
579 | WREG32(VGT_VERTEX_REUSE_BLOCK_CNTL, ((num_qd_pipes * 4) - 2) & VTX_REUSE_DEPTH_MASK); |
||
580 | |||
581 | /* set HW defaults for 3D engine */ |
||
582 | WREG32(CP_QUEUE_THRESHOLDS, (ROQ_IB1_START(0x16) | |
||
583 | ROQ_IB2_START(0x2b))); |
||
584 | |||
585 | WREG32(CP_MEQ_THRESHOLDS, STQ_SPLIT(0x30)); |
||
586 | |||
587 | WREG32(TA_CNTL_AUX, (DISABLE_CUBE_ANISO | |
||
588 | SYNC_GRADIENT | |
||
589 | SYNC_WALKER | |
||
590 | SYNC_ALIGNER)); |
||
591 | |||
592 | sx_debug_1 = RREG32(SX_DEBUG_1); |
||
593 | sx_debug_1 |= ENABLE_NEW_SMX_ADDRESS; |
||
594 | WREG32(SX_DEBUG_1, sx_debug_1); |
||
595 | |||
596 | smx_dc_ctl0 = RREG32(SMX_DC_CTL0); |
||
597 | smx_dc_ctl0 &= ~CACHE_DEPTH(0x1ff); |
||
598 | smx_dc_ctl0 |= CACHE_DEPTH((rdev->config.rv770.sx_num_of_sets * 64) - 1); |
||
599 | WREG32(SMX_DC_CTL0, smx_dc_ctl0); |
||
600 | |||
601 | WREG32(SMX_EVENT_CTL, (ES_FLUSH_CTL(4) | |
||
602 | GS_FLUSH_CTL(4) | |
||
603 | ACK_FLUSH_CTL(3) | |
||
604 | SYNC_FLUSH_CTL)); |
||
605 | |||
606 | if (rdev->family == CHIP_RV770) |
||
607 | WREG32(DB_DEBUG3, DB_CLK_OFF_DELAY(0x1f)); |
||
608 | else { |
||
609 | db_debug4 = RREG32(DB_DEBUG4); |
||
610 | db_debug4 |= DISABLE_TILE_COVERED_FOR_PS_ITER; |
||
611 | WREG32(DB_DEBUG4, db_debug4); |
||
612 | } |
||
613 | |||
614 | WREG32(SX_EXPORT_BUFFER_SIZES, (COLOR_BUFFER_SIZE((rdev->config.rv770.sx_max_export_size / 4) - 1) | |
||
615 | POSITION_BUFFER_SIZE((rdev->config.rv770.sx_max_export_pos_size / 4) - 1) | |
||
616 | SMX_BUFFER_SIZE((rdev->config.rv770.sx_max_export_smx_size / 4) - 1))); |
||
617 | |||
618 | WREG32(PA_SC_FIFO_SIZE, (SC_PRIM_FIFO_SIZE(rdev->config.rv770.sc_prim_fifo_size) | |
||
619 | SC_HIZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_hiz_tile_fifo_size) | |
||
620 | SC_EARLYZ_TILE_FIFO_SIZE(rdev->config.rv770.sc_earlyz_tile_fifo_fize))); |
||
621 | |||
622 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); |
||
623 | |||
624 | WREG32(VGT_NUM_INSTANCES, 1); |
||
625 | |||
626 | WREG32(SPI_CONFIG_CNTL, GPR_WRITE_PRIORITY(0)); |
||
627 | |||
628 | WREG32(SPI_CONFIG_CNTL_1, VTX_DONE_DELAY(4)); |
||
629 | |||
630 | WREG32(CP_PERFMON_CNTL, 0); |
||
631 | |||
632 | sq_ms_fifo_sizes = (CACHE_FIFO_SIZE(16 * rdev->config.rv770.sq_num_cf_insts) | |
||
633 | DONE_FIFO_HIWATER(0xe0) | |
||
634 | ALU_UPDATE_FIFO_HIWATER(0x8)); |
||
635 | switch (rdev->family) { |
||
636 | case CHIP_RV770: |
||
637 | sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x1); |
||
638 | break; |
||
639 | case CHIP_RV730: |
||
640 | case CHIP_RV710: |
||
641 | case CHIP_RV740: |
||
642 | default: |
||
643 | sq_ms_fifo_sizes |= FETCH_FIFO_HIWATER(0x4); |
||
644 | break; |
||
645 | } |
||
646 | WREG32(SQ_MS_FIFO_SIZES, sq_ms_fifo_sizes); |
||
647 | |||
648 | /* SQ_CONFIG, SQ_GPR_RESOURCE_MGMT, SQ_THREAD_RESOURCE_MGMT, SQ_STACK_RESOURCE_MGMT |
||
649 | * should be adjusted as needed by the 2D/3D drivers. This just sets default values |
||
650 | */ |
||
651 | sq_config = RREG32(SQ_CONFIG); |
||
652 | sq_config &= ~(PS_PRIO(3) | |
||
653 | VS_PRIO(3) | |
||
654 | GS_PRIO(3) | |
||
655 | ES_PRIO(3)); |
||
656 | sq_config |= (DX9_CONSTS | |
||
657 | VC_ENABLE | |
||
658 | EXPORT_SRC_C | |
||
659 | PS_PRIO(0) | |
||
660 | VS_PRIO(1) | |
||
661 | GS_PRIO(2) | |
||
662 | ES_PRIO(3)); |
||
663 | if (rdev->family == CHIP_RV710) |
||
664 | /* no vertex cache */ |
||
665 | sq_config &= ~VC_ENABLE; |
||
666 | |||
667 | WREG32(SQ_CONFIG, sq_config); |
||
668 | |||
669 | WREG32(SQ_GPR_RESOURCE_MGMT_1, (NUM_PS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | |
||
670 | NUM_VS_GPRS((rdev->config.rv770.max_gprs * 24)/64) | |
||
671 | NUM_CLAUSE_TEMP_GPRS(((rdev->config.rv770.max_gprs * 24)/64)/2))); |
||
672 | |||
673 | WREG32(SQ_GPR_RESOURCE_MGMT_2, (NUM_GS_GPRS((rdev->config.rv770.max_gprs * 7)/64) | |
||
674 | NUM_ES_GPRS((rdev->config.rv770.max_gprs * 7)/64))); |
||
675 | |||
676 | sq_thread_resource_mgmt = (NUM_PS_THREADS((rdev->config.rv770.max_threads * 4)/8) | |
||
677 | NUM_VS_THREADS((rdev->config.rv770.max_threads * 2)/8) | |
||
678 | NUM_ES_THREADS((rdev->config.rv770.max_threads * 1)/8)); |
||
679 | if (((rdev->config.rv770.max_threads * 1) / 8) > rdev->config.rv770.max_gs_threads) |
||
680 | sq_thread_resource_mgmt |= NUM_GS_THREADS(rdev->config.rv770.max_gs_threads); |
||
681 | else |
||
682 | sq_thread_resource_mgmt |= NUM_GS_THREADS((rdev->config.rv770.max_gs_threads * 1)/8); |
||
683 | WREG32(SQ_THREAD_RESOURCE_MGMT, sq_thread_resource_mgmt); |
||
684 | |||
685 | WREG32(SQ_STACK_RESOURCE_MGMT_1, (NUM_PS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | |
||
686 | NUM_VS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); |
||
687 | |||
688 | WREG32(SQ_STACK_RESOURCE_MGMT_2, (NUM_GS_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4) | |
||
689 | NUM_ES_STACK_ENTRIES((rdev->config.rv770.max_stack_entries * 1)/4))); |
||
690 | |||
691 | sq_dyn_gpr_size_simd_ab_0 = (SIMDA_RING0((rdev->config.rv770.max_gprs * 38)/64) | |
||
692 | SIMDA_RING1((rdev->config.rv770.max_gprs * 38)/64) | |
||
693 | SIMDB_RING0((rdev->config.rv770.max_gprs * 38)/64) | |
||
694 | SIMDB_RING1((rdev->config.rv770.max_gprs * 38)/64)); |
||
695 | |||
696 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_0, sq_dyn_gpr_size_simd_ab_0); |
||
697 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_1, sq_dyn_gpr_size_simd_ab_0); |
||
698 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_2, sq_dyn_gpr_size_simd_ab_0); |
||
699 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_3, sq_dyn_gpr_size_simd_ab_0); |
||
700 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_4, sq_dyn_gpr_size_simd_ab_0); |
||
701 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_5, sq_dyn_gpr_size_simd_ab_0); |
||
702 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_6, sq_dyn_gpr_size_simd_ab_0); |
||
703 | WREG32(SQ_DYN_GPR_SIZE_SIMD_AB_7, sq_dyn_gpr_size_simd_ab_0); |
||
704 | |||
705 | WREG32(PA_SC_FORCE_EOV_MAX_CNTS, (FORCE_EOV_MAX_CLK_CNT(4095) | |
||
706 | FORCE_EOV_MAX_REZ_CNT(255))); |
||
707 | |||
708 | if (rdev->family == CHIP_RV710) |
||
709 | WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(TC_ONLY) | |
||
710 | AUTO_INVLD_EN(ES_AND_GS_AUTO))); |
||
711 | else |
||
712 | WREG32(VGT_CACHE_INVALIDATION, (CACHE_INVALIDATION(VC_AND_TC) | |
||
713 | AUTO_INVLD_EN(ES_AND_GS_AUTO))); |
||
714 | |||
715 | switch (rdev->family) { |
||
716 | case CHIP_RV770: |
||
717 | case CHIP_RV730: |
||
718 | case CHIP_RV740: |
||
719 | gs_prim_buffer_depth = 384; |
||
720 | break; |
||
721 | case CHIP_RV710: |
||
722 | gs_prim_buffer_depth = 128; |
||
723 | break; |
||
724 | default: |
||
725 | break; |
||
726 | } |
||
727 | |||
728 | num_gs_verts_per_thread = rdev->config.rv770.max_pipes * 16; |
||
729 | vgt_gs_per_es = gs_prim_buffer_depth + num_gs_verts_per_thread; |
||
730 | /* Max value for this is 256 */ |
||
731 | if (vgt_gs_per_es > 256) |
||
732 | vgt_gs_per_es = 256; |
||
733 | |||
734 | WREG32(VGT_ES_PER_GS, 128); |
||
735 | WREG32(VGT_GS_PER_ES, vgt_gs_per_es); |
||
736 | WREG32(VGT_GS_PER_VS, 2); |
||
737 | |||
738 | /* more default values. 2D/3D driver should adjust as needed */ |
||
739 | WREG32(VGT_GS_VERTEX_REUSE, 16); |
||
740 | WREG32(PA_SC_LINE_STIPPLE_STATE, 0); |
||
741 | WREG32(VGT_STRMOUT_EN, 0); |
||
742 | WREG32(SX_MISC, 0); |
||
743 | WREG32(PA_SC_MODE_CNTL, 0); |
||
744 | WREG32(PA_SC_EDGERULE, 0xaaaaaaaa); |
||
745 | WREG32(PA_SC_AA_CONFIG, 0); |
||
746 | WREG32(PA_SC_CLIPRECT_RULE, 0xffff); |
||
747 | WREG32(PA_SC_LINE_STIPPLE, 0); |
||
748 | WREG32(SPI_INPUT_Z, 0); |
||
749 | WREG32(SPI_PS_IN_CONTROL_0, NUM_INTERP(2)); |
||
750 | WREG32(CB_COLOR7_FRAG, 0); |
||
751 | |||
752 | /* clear render buffer base addresses */ |
||
753 | WREG32(CB_COLOR0_BASE, 0); |
||
754 | WREG32(CB_COLOR1_BASE, 0); |
||
755 | WREG32(CB_COLOR2_BASE, 0); |
||
756 | WREG32(CB_COLOR3_BASE, 0); |
||
757 | WREG32(CB_COLOR4_BASE, 0); |
||
758 | WREG32(CB_COLOR5_BASE, 0); |
||
759 | WREG32(CB_COLOR6_BASE, 0); |
||
760 | WREG32(CB_COLOR7_BASE, 0); |
||
761 | |||
762 | WREG32(TCP_CNTL, 0); |
||
763 | |||
764 | hdp_host_path_cntl = RREG32(HDP_HOST_PATH_CNTL); |
||
765 | WREG32(HDP_HOST_PATH_CNTL, hdp_host_path_cntl); |
||
766 | |||
767 | WREG32(PA_SC_MULTI_CHIP_CNTL, 0); |
||
768 | |||
769 | WREG32(PA_CL_ENHANCE, (CLIP_VTX_REORDER_ENA | |
||
770 | NUM_CLIP_SEQ(3))); |
||
771 | |||
772 | } |
||
773 | |||
774 | int rv770_mc_init(struct radeon_device *rdev) |
||
775 | { |
||
776 | fixed20_12 a; |
||
777 | u32 tmp; |
||
1268 | serge | 778 | int chansize, numchan; |
1246 | serge | 779 | |
780 | /* Get VRAM informations */ |
||
781 | rdev->mc.vram_is_ddr = true; |
||
1268 | serge | 782 | tmp = RREG32(MC_ARB_RAMCFG); |
783 | if (tmp & CHANSIZE_OVERRIDE) { |
||
784 | chansize = 16; |
||
785 | } else if (tmp & CHANSIZE_MASK) { |
||
786 | chansize = 64; |
||
787 | } else { |
||
788 | chansize = 32; |
||
789 | } |
||
790 | tmp = RREG32(MC_SHARED_CHMAP); |
||
791 | switch ((tmp & NOOFCHAN_MASK) >> NOOFCHAN_SHIFT) { |
||
792 | case 0: |
||
793 | default: |
||
794 | numchan = 1; |
||
795 | break; |
||
796 | case 1: |
||
797 | numchan = 2; |
||
798 | break; |
||
799 | case 2: |
||
800 | numchan = 4; |
||
801 | break; |
||
802 | case 3: |
||
803 | numchan = 8; |
||
804 | break; |
||
805 | } |
||
806 | rdev->mc.vram_width = numchan * chansize; |
||
1246 | serge | 807 | /* Could aper size report 0 ? */ |
808 | rdev->mc.aper_base = drm_get_resource_start(rdev->ddev, 0); |
||
809 | rdev->mc.aper_size = drm_get_resource_len(rdev->ddev, 0); |
||
810 | /* Setup GPU memory space */ |
||
811 | rdev->mc.mc_vram_size = RREG32(CONFIG_MEMSIZE); |
||
812 | rdev->mc.real_vram_size = RREG32(CONFIG_MEMSIZE); |
||
813 | |||
814 | if (rdev->mc.mc_vram_size > rdev->mc.aper_size) |
||
815 | rdev->mc.mc_vram_size = rdev->mc.aper_size; |
||
816 | |||
817 | if (rdev->mc.real_vram_size > rdev->mc.aper_size) |
||
818 | rdev->mc.real_vram_size = rdev->mc.aper_size; |
||
819 | |||
820 | if (rdev->flags & RADEON_IS_AGP) { |
||
821 | /* gtt_size is setup by radeon_agp_init */ |
||
822 | rdev->mc.gtt_location = rdev->mc.agp_base; |
||
823 | tmp = 0xFFFFFFFFUL - rdev->mc.agp_base - rdev->mc.gtt_size; |
||
824 | /* Try to put vram before or after AGP because we |
||
825 | * we want SYSTEM_APERTURE to cover both VRAM and |
||
826 | * AGP so that GPU can catch out of VRAM/AGP access |
||
827 | */ |
||
828 | if (rdev->mc.gtt_location > rdev->mc.mc_vram_size) { |
||
1313 | serge | 829 | /* Enough place before */ |
1246 | serge | 830 | rdev->mc.vram_location = rdev->mc.gtt_location - |
831 | rdev->mc.mc_vram_size; |
||
832 | } else if (tmp > rdev->mc.mc_vram_size) { |
||
1313 | serge | 833 | /* Enough place after */ |
1246 | serge | 834 | rdev->mc.vram_location = rdev->mc.gtt_location + |
835 | rdev->mc.gtt_size; |
||
836 | } else { |
||
837 | /* Try to setup VRAM then AGP might not |
||
838 | * not work on some card |
||
839 | */ |
||
840 | rdev->mc.vram_location = 0x00000000UL; |
||
841 | rdev->mc.gtt_location = rdev->mc.mc_vram_size; |
||
842 | } |
||
843 | } else { |
||
844 | rdev->mc.vram_location = 0x00000000UL; |
||
845 | rdev->mc.gtt_location = rdev->mc.mc_vram_size; |
||
846 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
||
847 | } |
||
848 | rdev->mc.vram_start = rdev->mc.vram_location; |
||
849 | rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
||
850 | rdev->mc.gtt_start = rdev->mc.gtt_location; |
||
851 | rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
||
852 | /* FIXME: we should enforce default clock in case GPU is not in |
||
853 | * default setup |
||
854 | */ |
||
855 | a.full = rfixed_const(100); |
||
856 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); |
||
857 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
||
858 | return 0; |
||
859 | } |
||
860 | int rv770_gpu_reset(struct radeon_device *rdev) |
||
861 | { |
||
862 | /* FIXME: implement any rv770 specific bits */ |
||
863 | return r600_gpu_reset(rdev); |
||
864 | } |
||
865 | |||
866 | static int rv770_startup(struct radeon_device *rdev) |
||
867 | { |
||
868 | int r; |
||
869 | |||
870 | rv770_mc_program(rdev); |
||
871 | if (rdev->flags & RADEON_IS_AGP) { |
||
872 | rv770_agp_enable(rdev); |
||
873 | } else { |
||
874 | r = rv770_pcie_gart_enable(rdev); |
||
875 | if (r) |
||
876 | return r; |
||
877 | } |
||
878 | rv770_gpu_init(rdev); |
||
879 | |||
880 | // r = radeon_object_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, |
||
881 | // &rdev->r600_blit.shader_gpu_addr); |
||
882 | // if (r) { |
||
883 | // DRM_ERROR("failed to pin blit object %d\n", r); |
||
884 | // return r; |
||
885 | // } |
||
886 | |||
887 | // r = radeon_ring_init(rdev, rdev->cp.ring_size); |
||
888 | // if (r) |
||
889 | // return r; |
||
890 | // r = rv770_cp_load_microcode(rdev); |
||
891 | // if (r) |
||
892 | // return r; |
||
893 | // r = r600_cp_resume(rdev); |
||
894 | // if (r) |
||
895 | // return r; |
||
896 | /* write back buffer are not vital so don't worry about failure */ |
||
897 | // r600_wb_enable(rdev); |
||
898 | return 0; |
||
899 | } |
||
900 | |||
901 | |||
902 | /* Plan is to move initialization in that function and use |
||
903 | * helper function so that radeon_device_init pretty much |
||
904 | * do nothing more than calling asic specific function. This |
||
905 | * should also allow to remove a bunch of callback function |
||
906 | * like vram_info. |
||
907 | */ |
||
908 | int rv770_init(struct radeon_device *rdev) |
||
909 | { |
||
910 | int r; |
||
911 | |||
912 | r = radeon_dummy_page_init(rdev); |
||
913 | if (r) |
||
914 | return r; |
||
915 | /* This don't do much */ |
||
916 | r = radeon_gem_init(rdev); |
||
917 | if (r) |
||
918 | return r; |
||
919 | /* Read BIOS */ |
||
920 | if (!radeon_get_bios(rdev)) { |
||
921 | if (ASIC_IS_AVIVO(rdev)) |
||
922 | return -EINVAL; |
||
923 | } |
||
924 | /* Must be an ATOMBIOS */ |
||
925 | if (!rdev->is_atom_bios) { |
||
926 | dev_err(rdev->dev, "Expecting atombios for R600 GPU\n"); |
||
927 | return -EINVAL; |
||
928 | } |
||
929 | r = radeon_atombios_init(rdev); |
||
930 | if (r) |
||
931 | return r; |
||
932 | /* Post card if necessary */ |
||
1403 | serge | 933 | if (!r600_card_posted(rdev)) { |
934 | if (!rdev->bios) { |
||
935 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
||
936 | return -EINVAL; |
||
937 | } |
||
1246 | serge | 938 | DRM_INFO("GPU not posted. posting now...\n"); |
939 | atom_asic_init(rdev->mode_info.atom_context); |
||
940 | } |
||
941 | /* Initialize scratch registers */ |
||
942 | r600_scratch_init(rdev); |
||
943 | /* Initialize surface registers */ |
||
944 | radeon_surface_init(rdev); |
||
1268 | serge | 945 | /* Initialize clocks */ |
1246 | serge | 946 | radeon_get_clock_info(rdev->ddev); |
947 | r = radeon_clocks_init(rdev); |
||
948 | if (r) |
||
949 | return r; |
||
1268 | serge | 950 | /* Initialize power management */ |
951 | radeon_pm_init(rdev); |
||
1246 | serge | 952 | /* Fence driver */ |
953 | // r = radeon_fence_driver_init(rdev); |
||
954 | // if (r) |
||
955 | // return r; |
||
1403 | serge | 956 | if (rdev->flags & RADEON_IS_AGP) { |
957 | r = radeon_agp_init(rdev); |
||
958 | if (r) |
||
959 | radeon_agp_disable(rdev); |
||
960 | } |
||
1246 | serge | 961 | r = rv770_mc_init(rdev); |
962 | if (r) |
||
963 | return r; |
||
964 | /* Memory manager */ |
||
1403 | serge | 965 | r = radeon_bo_init(rdev); |
1246 | serge | 966 | if (r) |
967 | return r; |
||
968 | |||
969 | // if (!rdev->me_fw || !rdev->pfp_fw) { |
||
970 | // r = r600_cp_init_microcode(rdev); |
||
971 | // if (r) { |
||
972 | // DRM_ERROR("Failed to load firmware!\n"); |
||
973 | // return r; |
||
974 | // } |
||
975 | // } |
||
976 | |||
977 | r = r600_pcie_gart_init(rdev); |
||
978 | if (r) |
||
979 | return r; |
||
980 | |||
981 | rdev->accel_working = true; |
||
982 | // r = r600_blit_init(rdev); |
||
983 | // if (r) { |
||
984 | // DRM_ERROR("radeon: failled blitter (%d).\n", r); |
||
985 | // rdev->accel_working = false; |
||
986 | // } |
||
987 | |||
988 | r = rv770_startup(rdev); |
||
989 | if (r) { |
||
990 | // rv770_suspend(rdev); |
||
991 | // r600_wb_fini(rdev); |
||
992 | // radeon_ring_fini(rdev); |
||
993 | rv770_pcie_gart_fini(rdev); |
||
994 | rdev->accel_working = false; |
||
995 | } |
||
996 | if (rdev->accel_working) { |
||
997 | // r = radeon_ib_pool_init(rdev); |
||
998 | // if (r) { |
||
999 | // DRM_ERROR("radeon: failled initializing IB pool (%d).\n", r); |
||
1000 | // rdev->accel_working = false; |
||
1001 | // } |
||
1002 | // r = r600_ib_test(rdev); |
||
1003 | // if (r) { |
||
1004 | // DRM_ERROR("radeon: failled testing IB (%d).\n", r); |
||
1005 | // rdev->accel_working = false; |
||
1006 | // } |
||
1007 | } |
||
1008 | return 0; |
||
1009 | }><>><>><>><>>><>><>>><>>>>>>><>><>><>><>>>>>> |
||
1010 |