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Rev | Author | Line No. | Line |
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1128 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1179 | serge | 28 | #include |
1986 | serge | 29 | #include |
1179 | serge | 30 | #include |
1128 | serge | 31 | #include "radeon.h" |
1963 | serge | 32 | #include "radeon_asic.h" |
1221 | serge | 33 | #include "rs400d.h" |
1128 | serge | 34 | |
1221 | serge | 35 | /* This files gather functions specifics to : rs400,rs480 */ |
36 | static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev); |
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1128 | serge | 37 | |
38 | void rs400_gart_adjust_size(struct radeon_device *rdev) |
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39 | { |
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40 | /* Check gart size */ |
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41 | switch (rdev->mc.gtt_size/(1024*1024)) { |
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42 | case 32: |
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43 | case 64: |
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44 | case 128: |
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45 | case 256: |
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46 | case 512: |
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47 | case 1024: |
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48 | case 2048: |
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49 | break; |
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50 | default: |
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51 | DRM_ERROR("Unable to use IGP GART size %uM\n", |
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1179 | serge | 52 | (unsigned)(rdev->mc.gtt_size >> 20)); |
1128 | serge | 53 | DRM_ERROR("Valid GART size for IGP are 32M,64M,128M,256M,512M,1G,2G\n"); |
54 | DRM_ERROR("Forcing to 32M GART size\n"); |
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55 | rdev->mc.gtt_size = 32 * 1024 * 1024; |
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56 | return; |
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57 | } |
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58 | } |
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59 | |||
60 | void rs400_gart_tlb_flush(struct radeon_device *rdev) |
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61 | { |
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62 | uint32_t tmp; |
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63 | unsigned int timeout = rdev->usec_timeout; |
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64 | |||
65 | WREG32_MC(RS480_GART_CACHE_CNTRL, RS480_GART_CACHE_INVALIDATE); |
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66 | do { |
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67 | tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); |
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68 | if ((tmp & RS480_GART_CACHE_INVALIDATE) == 0) |
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69 | break; |
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70 | DRM_UDELAY(1); |
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71 | timeout--; |
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72 | } while (timeout > 0); |
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73 | WREG32_MC(RS480_GART_CACHE_CNTRL, 0); |
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74 | } |
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75 | |||
1179 | serge | 76 | int rs400_gart_init(struct radeon_device *rdev) |
1128 | serge | 77 | { |
78 | int r; |
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79 | |||
2997 | Serge | 80 | if (rdev->gart.ptr) { |
1963 | serge | 81 | WARN(1, "RS400 GART already initialized\n"); |
1179 | serge | 82 | return 0; |
83 | } |
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84 | /* Check gart size */ |
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85 | switch(rdev->mc.gtt_size / (1024 * 1024)) { |
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86 | case 32: |
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87 | case 64: |
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88 | case 128: |
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89 | case 256: |
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90 | case 512: |
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91 | case 1024: |
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92 | case 2048: |
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93 | break; |
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94 | default: |
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95 | return -EINVAL; |
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96 | } |
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1128 | serge | 97 | /* Initialize common gart structure */ |
98 | r = radeon_gart_init(rdev); |
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1179 | serge | 99 | if (r) |
1128 | serge | 100 | return r; |
1179 | serge | 101 | if (rs400_debugfs_pcie_gart_info_init(rdev)) |
1128 | serge | 102 | DRM_ERROR("Failed to register debugfs file for RS400 GART !\n"); |
1179 | serge | 103 | rdev->gart.table_size = rdev->gart.num_gpu_pages * 4; |
104 | return radeon_gart_table_ram_alloc(rdev); |
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105 | } |
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1128 | serge | 106 | |
1179 | serge | 107 | int rs400_gart_enable(struct radeon_device *rdev) |
108 | { |
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109 | uint32_t size_reg; |
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110 | uint32_t tmp; |
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111 | |||
1430 | serge | 112 | radeon_gart_restore(rdev); |
1128 | serge | 113 | tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); |
114 | tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; |
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115 | WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); |
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116 | /* Check gart size */ |
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117 | switch(rdev->mc.gtt_size / (1024 * 1024)) { |
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118 | case 32: |
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119 | size_reg = RS480_VA_SIZE_32MB; |
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120 | break; |
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121 | case 64: |
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122 | size_reg = RS480_VA_SIZE_64MB; |
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123 | break; |
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124 | case 128: |
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125 | size_reg = RS480_VA_SIZE_128MB; |
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126 | break; |
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127 | case 256: |
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128 | size_reg = RS480_VA_SIZE_256MB; |
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129 | break; |
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130 | case 512: |
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131 | size_reg = RS480_VA_SIZE_512MB; |
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132 | break; |
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133 | case 1024: |
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134 | size_reg = RS480_VA_SIZE_1GB; |
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135 | break; |
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136 | case 2048: |
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137 | size_reg = RS480_VA_SIZE_2GB; |
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138 | break; |
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139 | default: |
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140 | return -EINVAL; |
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141 | } |
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142 | /* It should be fine to program it to max value */ |
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143 | if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { |
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144 | WREG32_MC(RS690_MCCFG_AGP_BASE, 0xFFFFFFFF); |
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145 | WREG32_MC(RS690_MCCFG_AGP_BASE_2, 0); |
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146 | } else { |
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147 | WREG32(RADEON_AGP_BASE, 0xFFFFFFFF); |
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148 | WREG32(RS480_AGP_BASE_2, 0); |
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149 | } |
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1430 | serge | 150 | tmp = REG_SET(RS690_MC_AGP_TOP, rdev->mc.gtt_end >> 16); |
151 | tmp |= REG_SET(RS690_MC_AGP_START, rdev->mc.gtt_start >> 16); |
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1128 | serge | 152 | if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { |
153 | WREG32_MC(RS690_MCCFG_AGP_LOCATION, tmp); |
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154 | tmp = RREG32(RADEON_BUS_CNTL) & ~RS600_BUS_MASTER_DIS; |
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155 | WREG32(RADEON_BUS_CNTL, tmp); |
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156 | } else { |
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157 | WREG32(RADEON_MC_AGP_LOCATION, tmp); |
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158 | tmp = RREG32(RADEON_BUS_CNTL) & ~RADEON_BUS_MASTER_DIS; |
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159 | WREG32(RADEON_BUS_CNTL, tmp); |
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160 | } |
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161 | /* Table should be in 32bits address space so ignore bits above. */ |
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1179 | serge | 162 | tmp = (u32)rdev->gart.table_addr & 0xfffff000; |
163 | tmp |= (upper_32_bits(rdev->gart.table_addr) & 0xff) << 4; |
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164 | |||
1128 | serge | 165 | WREG32_MC(RS480_GART_BASE, tmp); |
166 | /* TODO: more tweaking here */ |
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167 | WREG32_MC(RS480_GART_FEATURE_ID, |
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168 | (RS480_TLB_ENABLE | |
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169 | RS480_GTW_LAC_EN | RS480_1LEVEL_GART)); |
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170 | /* Disable snooping */ |
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171 | WREG32_MC(RS480_AGP_MODE_CNTL, |
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172 | (1 << RS480_REQ_TYPE_SNOOP_SHIFT) | RS480_REQ_TYPE_SNOOP_DIS); |
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173 | /* Disable AGP mode */ |
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174 | /* FIXME: according to doc we should set HIDE_MMCFG_BAR=0, |
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175 | * AGPMODE30=0 & AGP30ENHANCED=0 in NB_CNTL */ |
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176 | if ((rdev->family == CHIP_RS690) || (rdev->family == CHIP_RS740)) { |
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177 | WREG32_MC(RS480_MC_MISC_CNTL, |
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178 | (RS480_GART_INDEX_REG_EN | RS690_BLOCK_GFX_D3_EN)); |
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179 | } else { |
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180 | WREG32_MC(RS480_MC_MISC_CNTL, RS480_GART_INDEX_REG_EN); |
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181 | } |
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182 | /* Enable gart */ |
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183 | WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, (RS480_GART_EN | size_reg)); |
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184 | rs400_gart_tlb_flush(rdev); |
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2997 | Serge | 185 | DRM_INFO("PCIE GART of %uM enabled (table at 0x%016llX).\n", |
186 | (unsigned)(rdev->mc.gtt_size >> 20), |
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187 | (unsigned long long)rdev->gart.table_addr); |
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1128 | serge | 188 | rdev->gart.ready = true; |
189 | return 0; |
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190 | } |
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191 | |||
192 | void rs400_gart_disable(struct radeon_device *rdev) |
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193 | { |
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194 | uint32_t tmp; |
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195 | |||
196 | tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); |
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197 | tmp |= RS690_DIS_OUT_OF_PCI_GART_ACCESS; |
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198 | WREG32_MC(RS690_AIC_CTRL_SCRATCH, tmp); |
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199 | WREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE, 0); |
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200 | } |
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201 | |||
1179 | serge | 202 | void rs400_gart_fini(struct radeon_device *rdev) |
203 | { |
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1963 | serge | 204 | radeon_gart_fini(rdev); |
1179 | serge | 205 | rs400_gart_disable(rdev); |
206 | radeon_gart_table_ram_free(rdev); |
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207 | } |
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208 | |||
1963 | serge | 209 | #define RS400_PTE_WRITEABLE (1 << 2) |
210 | #define RS400_PTE_READABLE (1 << 3) |
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211 | |||
1128 | serge | 212 | int rs400_gart_set_page(struct radeon_device *rdev, int i, uint64_t addr) |
213 | { |
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1179 | serge | 214 | uint32_t entry; |
2997 | Serge | 215 | u32 *gtt = rdev->gart.ptr; |
1179 | serge | 216 | |
1128 | serge | 217 | if (i < 0 || i > rdev->gart.num_gpu_pages) { |
218 | return -EINVAL; |
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219 | } |
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1179 | serge | 220 | |
221 | entry = (lower_32_bits(addr) & PAGE_MASK) | |
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222 | ((upper_32_bits(addr) & 0xff) << 4) | |
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1963 | serge | 223 | RS400_PTE_WRITEABLE | RS400_PTE_READABLE; |
1179 | serge | 224 | entry = cpu_to_le32(entry); |
2997 | Serge | 225 | gtt[i] = entry; |
1128 | serge | 226 | return 0; |
227 | } |
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228 | |||
1404 | serge | 229 | int rs400_mc_wait_for_idle(struct radeon_device *rdev) |
230 | { |
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231 | unsigned i; |
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232 | uint32_t tmp; |
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233 | |||
234 | for (i = 0; i < rdev->usec_timeout; i++) { |
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235 | /* read MC_STATUS */ |
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1963 | serge | 236 | tmp = RREG32(RADEON_MC_STATUS); |
237 | if (tmp & RADEON_MC_IDLE) { |
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1404 | serge | 238 | return 0; |
239 | } |
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240 | DRM_UDELAY(1); |
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241 | } |
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242 | return -1; |
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243 | } |
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244 | |||
2997 | Serge | 245 | static void rs400_gpu_init(struct radeon_device *rdev) |
1128 | serge | 246 | { |
247 | /* FIXME: is this correct ? */ |
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248 | r420_pipes_init(rdev); |
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1404 | serge | 249 | if (rs400_mc_wait_for_idle(rdev)) { |
250 | printk(KERN_WARNING "rs400: Failed to wait MC idle while " |
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1963 | serge | 251 | "programming pipes. Bad things might happen. %08x\n", RREG32(RADEON_MC_STATUS)); |
1128 | serge | 252 | } |
253 | } |
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254 | |||
2997 | Serge | 255 | static void rs400_mc_init(struct radeon_device *rdev) |
1128 | serge | 256 | { |
1430 | serge | 257 | u64 base; |
258 | |||
1128 | serge | 259 | rs400_gart_adjust_size(rdev); |
1430 | serge | 260 | rdev->mc.igp_sideport_enabled = radeon_combios_sideport_present(rdev); |
1128 | serge | 261 | /* DDR for all card after R300 & IGP */ |
262 | rdev->mc.vram_is_ddr = true; |
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263 | rdev->mc.vram_width = 128; |
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1179 | serge | 264 | r100_vram_init_sizes(rdev); |
1430 | serge | 265 | base = (RREG32(RADEON_NB_TOM) & 0xffff) << 16; |
266 | radeon_vram_location(rdev, &rdev->mc, base); |
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1963 | serge | 267 | rdev->mc.gtt_base_align = rdev->mc.gtt_size - 1; |
1430 | serge | 268 | radeon_gtt_location(rdev, &rdev->mc); |
1963 | serge | 269 | radeon_update_bandwidth_info(rdev); |
1128 | serge | 270 | } |
271 | |||
272 | uint32_t rs400_mc_rreg(struct radeon_device *rdev, uint32_t reg) |
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273 | { |
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274 | uint32_t r; |
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275 | |||
276 | WREG32(RS480_NB_MC_INDEX, reg & 0xff); |
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277 | r = RREG32(RS480_NB_MC_DATA); |
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278 | WREG32(RS480_NB_MC_INDEX, 0xff); |
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279 | return r; |
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280 | } |
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281 | |||
282 | void rs400_mc_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
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283 | { |
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284 | WREG32(RS480_NB_MC_INDEX, ((reg) & 0xff) | RS480_NB_MC_IND_WR_EN); |
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285 | WREG32(RS480_NB_MC_DATA, (v)); |
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286 | WREG32(RS480_NB_MC_INDEX, 0xff); |
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287 | } |
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288 | |||
289 | #if defined(CONFIG_DEBUG_FS) |
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290 | static int rs400_debugfs_gart_info(struct seq_file *m, void *data) |
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291 | { |
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292 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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293 | struct drm_device *dev = node->minor->dev; |
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294 | struct radeon_device *rdev = dev->dev_private; |
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295 | uint32_t tmp; |
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296 | |||
297 | tmp = RREG32(RADEON_HOST_PATH_CNTL); |
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298 | seq_printf(m, "HOST_PATH_CNTL 0x%08x\n", tmp); |
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299 | tmp = RREG32(RADEON_BUS_CNTL); |
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300 | seq_printf(m, "BUS_CNTL 0x%08x\n", tmp); |
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301 | tmp = RREG32_MC(RS690_AIC_CTRL_SCRATCH); |
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302 | seq_printf(m, "AIC_CTRL_SCRATCH 0x%08x\n", tmp); |
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303 | if (rdev->family == CHIP_RS690 || (rdev->family == CHIP_RS740)) { |
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304 | tmp = RREG32_MC(RS690_MCCFG_AGP_BASE); |
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305 | seq_printf(m, "MCCFG_AGP_BASE 0x%08x\n", tmp); |
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306 | tmp = RREG32_MC(RS690_MCCFG_AGP_BASE_2); |
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307 | seq_printf(m, "MCCFG_AGP_BASE_2 0x%08x\n", tmp); |
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308 | tmp = RREG32_MC(RS690_MCCFG_AGP_LOCATION); |
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309 | seq_printf(m, "MCCFG_AGP_LOCATION 0x%08x\n", tmp); |
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1963 | serge | 310 | tmp = RREG32_MC(RS690_MCCFG_FB_LOCATION); |
1128 | serge | 311 | seq_printf(m, "MCCFG_FB_LOCATION 0x%08x\n", tmp); |
1963 | serge | 312 | tmp = RREG32(RS690_HDP_FB_LOCATION); |
1128 | serge | 313 | seq_printf(m, "HDP_FB_LOCATION 0x%08x\n", tmp); |
314 | } else { |
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315 | tmp = RREG32(RADEON_AGP_BASE); |
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316 | seq_printf(m, "AGP_BASE 0x%08x\n", tmp); |
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317 | tmp = RREG32(RS480_AGP_BASE_2); |
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318 | seq_printf(m, "AGP_BASE_2 0x%08x\n", tmp); |
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319 | tmp = RREG32(RADEON_MC_AGP_LOCATION); |
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320 | seq_printf(m, "MC_AGP_LOCATION 0x%08x\n", tmp); |
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321 | } |
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322 | tmp = RREG32_MC(RS480_GART_BASE); |
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323 | seq_printf(m, "GART_BASE 0x%08x\n", tmp); |
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324 | tmp = RREG32_MC(RS480_GART_FEATURE_ID); |
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325 | seq_printf(m, "GART_FEATURE_ID 0x%08x\n", tmp); |
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326 | tmp = RREG32_MC(RS480_AGP_MODE_CNTL); |
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327 | seq_printf(m, "AGP_MODE_CONTROL 0x%08x\n", tmp); |
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328 | tmp = RREG32_MC(RS480_MC_MISC_CNTL); |
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329 | seq_printf(m, "MC_MISC_CNTL 0x%08x\n", tmp); |
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330 | tmp = RREG32_MC(0x5F); |
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331 | seq_printf(m, "MC_MISC_UMA_CNTL 0x%08x\n", tmp); |
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332 | tmp = RREG32_MC(RS480_AGP_ADDRESS_SPACE_SIZE); |
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333 | seq_printf(m, "AGP_ADDRESS_SPACE_SIZE 0x%08x\n", tmp); |
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334 | tmp = RREG32_MC(RS480_GART_CACHE_CNTRL); |
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335 | seq_printf(m, "GART_CACHE_CNTRL 0x%08x\n", tmp); |
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336 | tmp = RREG32_MC(0x3B); |
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337 | seq_printf(m, "MC_GART_ERROR_ADDRESS 0x%08x\n", tmp); |
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338 | tmp = RREG32_MC(0x3C); |
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339 | seq_printf(m, "MC_GART_ERROR_ADDRESS_HI 0x%08x\n", tmp); |
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340 | tmp = RREG32_MC(0x30); |
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341 | seq_printf(m, "GART_ERROR_0 0x%08x\n", tmp); |
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342 | tmp = RREG32_MC(0x31); |
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343 | seq_printf(m, "GART_ERROR_1 0x%08x\n", tmp); |
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344 | tmp = RREG32_MC(0x32); |
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345 | seq_printf(m, "GART_ERROR_2 0x%08x\n", tmp); |
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346 | tmp = RREG32_MC(0x33); |
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347 | seq_printf(m, "GART_ERROR_3 0x%08x\n", tmp); |
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348 | tmp = RREG32_MC(0x34); |
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349 | seq_printf(m, "GART_ERROR_4 0x%08x\n", tmp); |
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350 | tmp = RREG32_MC(0x35); |
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351 | seq_printf(m, "GART_ERROR_5 0x%08x\n", tmp); |
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352 | tmp = RREG32_MC(0x36); |
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353 | seq_printf(m, "GART_ERROR_6 0x%08x\n", tmp); |
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354 | tmp = RREG32_MC(0x37); |
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355 | seq_printf(m, "GART_ERROR_7 0x%08x\n", tmp); |
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356 | return 0; |
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357 | } |
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358 | |||
359 | static struct drm_info_list rs400_gart_info_list[] = { |
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360 | {"rs400_gart_info", rs400_debugfs_gart_info, 0, NULL}, |
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361 | }; |
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362 | #endif |
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363 | |||
1221 | serge | 364 | static int rs400_debugfs_pcie_gart_info_init(struct radeon_device *rdev) |
1128 | serge | 365 | { |
366 | #if defined(CONFIG_DEBUG_FS) |
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367 | return radeon_debugfs_add_files(rdev, rs400_gart_info_list, 1); |
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368 | #else |
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369 | return 0; |
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370 | #endif |
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371 | } |
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1221 | serge | 372 | |
2997 | Serge | 373 | static void rs400_mc_program(struct radeon_device *rdev) |
1221 | serge | 374 | { |
375 | struct r100_mc_save save; |
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376 | |||
377 | /* Stops all mc clients */ |
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378 | r100_mc_stop(rdev, &save); |
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379 | |||
380 | /* Wait for mc idle */ |
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1404 | serge | 381 | if (rs400_mc_wait_for_idle(rdev)) |
382 | dev_warn(rdev->dev, "rs400: Wait MC idle timeout before updating MC.\n"); |
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1221 | serge | 383 | WREG32(R_000148_MC_FB_LOCATION, |
384 | S_000148_MC_FB_START(rdev->mc.vram_start >> 16) | |
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385 | S_000148_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
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386 | |||
387 | r100_mc_resume(rdev, &save); |
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388 | } |
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389 | |||
390 | static int rs400_startup(struct radeon_device *rdev) |
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391 | { |
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392 | int r; |
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393 | |||
1963 | serge | 394 | r100_set_common_regs(rdev); |
395 | |||
1221 | serge | 396 | rs400_mc_program(rdev); |
397 | /* Resume clock */ |
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398 | r300_clock_startup(rdev); |
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399 | /* Initialize GPU configuration (# pipes, ...) */ |
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400 | rs400_gpu_init(rdev); |
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1321 | serge | 401 | r100_enable_bm(rdev); |
1221 | serge | 402 | /* Initialize GART (initialize after TTM so we can allocate |
403 | * memory through TTM but finalize after TTM) */ |
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404 | r = rs400_gart_enable(rdev); |
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405 | if (r) |
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406 | return r; |
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2005 | serge | 407 | |
408 | /* allocate wb buffer */ |
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409 | r = radeon_wb_init(rdev); |
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410 | if (r) |
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411 | return r; |
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412 | |||
1221 | serge | 413 | /* Enable IRQ */ |
2005 | serge | 414 | r100_irq_set(rdev); |
1403 | serge | 415 | rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL); |
1221 | serge | 416 | /* 1M ring buffer */ |
1413 | serge | 417 | r = r100_cp_init(rdev, 1024 * 1024); |
418 | if (r) { |
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1963 | serge | 419 | dev_err(rdev->dev, "failed initializing CP (%d).\n", r); |
1413 | serge | 420 | return r; |
421 | } |
||
2997 | Serge | 422 | |
423 | r = radeon_ib_pool_init(rdev); |
||
2005 | serge | 424 | if (r) { |
2997 | Serge | 425 | dev_err(rdev->dev, "IB initialization failed (%d).\n", r); |
2005 | serge | 426 | return r; |
427 | } |
||
2997 | Serge | 428 | |
1221 | serge | 429 | return 0; |
430 | } |
||
431 | |||
432 | |||
433 | |||
434 | |||
435 | int rs400_init(struct radeon_device *rdev) |
||
436 | { |
||
437 | int r; |
||
438 | |||
439 | /* Disable VGA */ |
||
440 | r100_vga_render_disable(rdev); |
||
441 | /* Initialize scratch registers */ |
||
442 | radeon_scratch_init(rdev); |
||
443 | /* Initialize surface registers */ |
||
444 | radeon_surface_init(rdev); |
||
445 | /* TODO: disable VGA need to use VGA request */ |
||
1963 | serge | 446 | /* restore some register to sane defaults */ |
447 | r100_restore_sanity(rdev); |
||
1221 | serge | 448 | /* BIOS*/ |
449 | if (!radeon_get_bios(rdev)) { |
||
450 | if (ASIC_IS_AVIVO(rdev)) |
||
451 | return -EINVAL; |
||
452 | } |
||
453 | if (rdev->is_atom_bios) { |
||
454 | dev_err(rdev->dev, "Expecting combios for RS400/RS480 GPU\n"); |
||
455 | return -EINVAL; |
||
456 | } else { |
||
457 | r = radeon_combios_init(rdev); |
||
458 | if (r) |
||
459 | return r; |
||
460 | } |
||
461 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
||
1963 | serge | 462 | if (radeon_asic_reset(rdev)) { |
1221 | serge | 463 | dev_warn(rdev->dev, |
464 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
||
465 | RREG32(R_000E40_RBBM_STATUS), |
||
466 | RREG32(R_0007C0_CP_STAT)); |
||
467 | } |
||
468 | /* check if cards are posted or not */ |
||
1321 | serge | 469 | if (radeon_boot_test_post_card(rdev) == false) |
470 | return -EINVAL; |
||
471 | |||
1221 | serge | 472 | /* Initialize clocks */ |
473 | radeon_get_clock_info(rdev->ddev); |
||
1430 | serge | 474 | /* initialize memory controller */ |
475 | rs400_mc_init(rdev); |
||
1221 | serge | 476 | /* Fence driver */ |
2005 | serge | 477 | r = radeon_fence_driver_init(rdev); |
478 | if (r) |
||
479 | return r; |
||
480 | r = radeon_irq_kms_init(rdev); |
||
481 | if (r) |
||
482 | return r; |
||
1221 | serge | 483 | /* Memory manager */ |
1321 | serge | 484 | r = radeon_bo_init(rdev); |
1221 | serge | 485 | if (r) |
486 | return r; |
||
487 | r = rs400_gart_init(rdev); |
||
488 | if (r) |
||
489 | return r; |
||
490 | r300_set_reg_safe(rdev); |
||
2997 | Serge | 491 | |
1221 | serge | 492 | rdev->accel_working = true; |
493 | r = rs400_startup(rdev); |
||
494 | if (r) { |
||
495 | /* Somethings want wront with the accel init stop accel */ |
||
496 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
||
497 | // r100_cp_fini(rdev); |
||
498 | // r100_wb_fini(rdev); |
||
499 | // r100_ib_fini(rdev); |
||
500 | rs400_gart_fini(rdev); |
||
501 | // radeon_irq_kms_fini(rdev); |
||
502 | rdev->accel_working = false; |
||
503 | } |
||
504 | return 0; |
||
505 | }><>>><>>><>><>><>><> |