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Rev | Author | Line No. | Line |
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1246 | serge | 1 | |
2 | #include |
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3 | #include |
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4 | #include "radeon_drm.h" |
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5 | #include "radeon.h" |
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6 | #include "radeon_object.h" |
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7 | #include "display.h" |
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8 | #include "drm_fb_helper.h" |
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1986 | serge | 9 | |
1246 | serge | 10 | |
1986 | serge | 11 | struct drm_fb_helper helper; |
12 | struct radeon_framebuffer rfb; |
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13 | struct list_head fbdev_list; |
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14 | struct radeon_device *rdev; |
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15 | }; |
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16 | |||
1246 | serge | 17 | |
1986 | serge | 18 | |
19 | |||
20 | |||
1246 | serge | 21 | static void __stdcall move_cursor_kms(cursor_t *cursor, int x, int y); |
22 | |||
23 | |||
24 | |||
25 | |||
1313 | serge | 26 | |
27 | |||
1246 | serge | 28 | { |
29 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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30 | struct radeon_device *rdev = crtc->dev->dev_private; |
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31 | |||
32 | |||
33 | WREG32(RADEON_MM_INDEX, AVIVO_D1CUR_CONTROL + radeon_crtc->crtc_offset); |
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34 | WREG32(RADEON_MM_DATA, AVIVO_D1CURSOR_EN | |
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35 | (AVIVO_D1CURSOR_MODE_24BPP << AVIVO_D1CURSOR_MODE_SHIFT)); |
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36 | } else { |
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37 | switch (radeon_crtc->crtc_id) { |
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38 | case 0: |
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39 | WREG32(RADEON_MM_INDEX, RADEON_CRTC_GEN_CNTL); |
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40 | break; |
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41 | case 1: |
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42 | WREG32(RADEON_MM_INDEX, RADEON_CRTC2_GEN_CNTL); |
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43 | break; |
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44 | default: |
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45 | return; |
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46 | } |
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47 | |||
48 | |||
49 | (RADEON_CRTC_CUR_MODE_24BPP << RADEON_CRTC_CUR_MODE_SHIFT)), |
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50 | ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_CUR_MODE_MASK)); |
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51 | } |
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52 | } |
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53 | |||
54 | |||
55 | { |
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56 | struct radeon_device *rdev = crtc->dev->dev_private; |
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57 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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58 | uint32_t cur_lock; |
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59 | |||
60 | |||
61 | cur_lock = RREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset); |
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62 | if (lock) |
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63 | cur_lock |= AVIVO_D1CURSOR_UPDATE_LOCK; |
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64 | else |
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65 | cur_lock &= ~AVIVO_D1CURSOR_UPDATE_LOCK; |
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66 | WREG32(AVIVO_D1CUR_UPDATE + radeon_crtc->crtc_offset, cur_lock); |
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67 | } else { |
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68 | cur_lock = RREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset); |
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69 | if (lock) |
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70 | cur_lock |= RADEON_CUR_LOCK; |
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71 | else |
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72 | cur_lock &= ~RADEON_CUR_LOCK; |
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73 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, cur_lock); |
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74 | } |
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75 | } |
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76 | |||
77 | |||
78 | { |
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79 | struct radeon_device *rdev; |
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80 | struct radeon_crtc *radeon_crtc; |
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81 | cursor_t *old; |
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82 | uint32_t gpu_addr; |
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83 | |||
84 | |||
85 | radeon_crtc = to_radeon_crtc(rdisplay->crtc); |
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86 | |||
87 | |||
88 | |||
89 | |||
90 | gpu_addr = radeon_bo_gpu_offset(cursor->robj); |
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1404 | serge | 91 | |
1246 | serge | 92 | |
93 | WREG32(AVIVO_D1CUR_SURFACE_ADDRESS + radeon_crtc->crtc_offset, gpu_addr); |
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94 | else { |
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95 | radeon_crtc->legacy_cursor_offset = gpu_addr - rdev->mc.vram_start; |
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1430 | serge | 96 | /* offset is from DISP(2)_BASE_ADDRESS */ |
1246 | serge | 97 | WREG32(RADEON_CUR_OFFSET + radeon_crtc->crtc_offset, radeon_crtc->legacy_cursor_offset); |
98 | } |
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99 | |||
100 | |||
101 | }; |
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102 | |||
103 | |||
104 | { |
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105 | struct radeon_device *rdev; |
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106 | rdev = (struct radeon_device *)rdisplay->ddev->dev_private; |
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107 | struct drm_crtc *crtc = rdisplay->crtc; |
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108 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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109 | |||
110 | |||
111 | int hot_y = cursor->hot_y; |
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112 | |||
113 | |||
114 | if (ASIC_IS_AVIVO(rdev)) |
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115 | { |
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116 | int w = 32; |
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117 | int i = 0; |
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118 | struct drm_crtc *crtc_p; |
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119 | |||
120 | |||
121 | // x += crtc->x; |
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122 | // y += crtc->y; |
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123 | |||
124 | |||
125 | #if 0 |
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126 | /* avivo cursor image can't end on 128 pixel boundry or |
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127 | * go past the end of the frame if both crtcs are enabled |
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128 | */ |
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129 | list_for_each_entry(crtc_p, &crtc->dev->mode_config.crtc_list, head) { |
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130 | if (crtc_p->enabled) |
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131 | i++; |
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132 | } |
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133 | if (i > 1) { |
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134 | int cursor_end, frame_end; |
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135 | |||
136 | |||
137 | frame_end = crtc->x + crtc->mode.crtc_hdisplay; |
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138 | if (cursor_end >= frame_end) { |
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139 | w = w - (cursor_end - frame_end); |
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140 | if (!(frame_end & 0x7f)) |
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141 | w--; |
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142 | } else { |
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143 | if (!(cursor_end & 0x7f)) |
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144 | w--; |
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145 | } |
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146 | if (w <= 0) |
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147 | w = 1; |
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148 | } |
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149 | #endif |
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150 | WREG32(AVIVO_D1CUR_POSITION + radeon_crtc->crtc_offset, |
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151 | (x << 16) | y); |
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152 | WREG32(AVIVO_D1CUR_HOT_SPOT + radeon_crtc->crtc_offset, |
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153 | (hot_x << 16) | hot_y); |
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154 | WREG32(AVIVO_D1CUR_SIZE + radeon_crtc->crtc_offset, |
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155 | ((w - 1) << 16) | 31); |
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156 | } else { |
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157 | if (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN) |
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158 | y *= 2; |
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159 | |||
160 | |||
1404 | serge | 161 | int xorg =0, yorg=0; |
162 | |||
163 | |||
164 | y = y - hot_y; |
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165 | |||
166 | |||
167 | { |
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168 | xorg = -x + 1; |
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169 | x = 0; |
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170 | } |
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171 | |||
172 | |||
173 | { |
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174 | yorg = -hot_y + 1; |
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175 | y = 0; |
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176 | }; |
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177 | |||
178 | |||
179 | (RADEON_CUR_LOCK | (xorg << 16) | yorg )); |
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180 | WREG32(RADEON_CUR_HORZ_VERT_POSN, |
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181 | (RADEON_CUR_LOCK | (x << 16) | y)); |
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1246 | serge | 182 | |
183 | |||
1404 | serge | 184 | |
185 | |||
1246 | serge | 186 | WREG32(RADEON_CUR_OFFSET, |
1404 | serge | 187 | (gpu_addr - rdev->mc.vram_start + (yorg * 256))); |
1430 | serge | 188 | } |
1246 | serge | 189 | radeon_lock_cursor_kms(crtc, false); |
190 | } |
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191 | |||
192 | |||
193 | { |
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194 | static char name[4]; |
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195 | |||
196 | |||
197 | name[1] = ((x[0] & 0x03) << 3) + ((x[1] & 0xE0) >> 5) + '@'; |
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198 | name[2] = (x[1] & 0x1F) + '@'; |
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199 | name[3] = 0; |
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200 | |||
201 | |||
202 | } |
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203 | |||
204 | |||
205 | videomode_t *reqmode, bool strict) |
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1403 | serge | 206 | { |
1246 | serge | 207 | struct drm_display_mode *mode = NULL, *tmpmode; |
208 | |||
209 | |||
1986 | serge | 210 | |
211 | |||
212 | |||
213 | |||
214 | |||
1246 | serge | 215 | |
216 | |||
217 | |||
218 | |||
219 | reqmode->width, reqmode->height, reqmode->freq); |
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220 | |||
221 | |||
222 | { |
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223 | if( (drm_mode_width(tmpmode) == reqmode->width) && |
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224 | (drm_mode_height(tmpmode) == reqmode->height) && |
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225 | (drm_mode_vrefresh(tmpmode) == reqmode->freq) ) |
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226 | { |
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227 | mode = tmpmode; |
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228 | goto do_set; |
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229 | } |
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230 | }; |
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231 | |||
232 | |||
233 | { |
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234 | list_for_each_entry(tmpmode, &connector->modes, head) |
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235 | { |
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236 | if( (drm_mode_width(tmpmode) == reqmode->width) && |
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237 | (drm_mode_height(tmpmode) == reqmode->height) ) |
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238 | { |
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239 | mode = tmpmode; |
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240 | goto do_set; |
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241 | } |
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242 | }; |
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243 | }; |
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244 | |||
245 | |||
246 | |||
247 | |||
248 | { |
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249 | struct drm_framebuffer *fb; |
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250 | struct drm_encoder *encoder; |
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251 | struct drm_crtc *crtc; |
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252 | |||
253 | |||
254 | char *con_name; |
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255 | char *enc_name; |
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256 | |||
257 | |||
258 | crtc = encoder->crtc; |
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259 | |||
260 | |||
1963 | serge | 261 | // struct drm_framebuffer, filp_head); |
262 | |||
1246 | serge | 263 | |
264 | |||
265 | |||
266 | // manufacturer_name(con_edid + 0x08), |
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267 | // (unsigned short)(con_edid[0x0A] + (con_edid[0x0B] << 8)), |
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268 | // (unsigned int)(con_edid[0x0C] + (con_edid[0x0D] << 8) |
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269 | // + (con_edid[0x0E] << 16) + (con_edid[0x0F] << 24))); |
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270 | |||
271 | |||
272 | enc_name = drm_get_encoder_name(encoder); |
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273 | |||
274 | |||
275 | reqmode->width, reqmode->height, con_name, enc_name); |
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276 | |||
277 | |||
1986 | serge | 278 | |
279 | |||
1246 | serge | 280 | fb->height = reqmode->height; |
281 | fb->pitch = radeon_align_pitch(dev->dev_private, reqmode->width, 32, false) * ((32 + 1) / 8); |
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282 | fb->bits_per_pixel = 32; |
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1986 | serge | 283 | |
1246 | serge | 284 | |
285 | crtc->enabled = true; |
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286 | rdisplay->crtc = crtc; |
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287 | |||
288 | |||
289 | |||
290 | |||
291 | radeon_show_cursor_kms(crtc); |
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292 | |||
293 | |||
294 | { |
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295 | rdisplay->width = fb->width; |
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296 | rdisplay->height = fb->height; |
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297 | rdisplay->pitch = fb->pitch; |
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298 | rdisplay->vrefresh = drm_mode_vrefresh(mode); |
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299 | |||
300 | |||
301 | |||
302 | |||
303 | fb->width, fb->height, fb->pitch); |
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304 | } |
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305 | else |
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306 | DRM_ERROR("failed to set mode %d_%d on crtc %p\n", |
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307 | fb->width, fb->height, crtc); |
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308 | } |
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309 | |||
310 | |||
311 | return ret; |
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312 | }; |
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313 | |||
314 | |||
315 | { |
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316 | struct drm_display_mode *mode; |
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317 | int count = 0; |
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318 | |||
319 | |||
320 | { |
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321 | count++; |
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322 | }; |
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323 | return count; |
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324 | }; |
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325 | |||
326 | |||
327 | { |
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328 | struct drm_connector *connector; |
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329 | struct drm_connector_helper_funcs *connector_funcs; |
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1963 | serge | 330 | |
331 | |||
1246 | serge | 332 | |
333 | |||
334 | { |
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335 | struct drm_encoder *encoder; |
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336 | struct drm_crtc *crtc; |
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337 | |||
338 | |||
339 | continue; |
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340 | |||
341 | |||
1963 | serge | 342 | encoder = connector_funcs->best_encoder(connector); |
343 | if( encoder == NULL) |
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1246 | serge | 344 | continue; |
345 | |||
346 | |||
1963 | serge | 347 | |
348 | |||
1246 | serge | 349 | |
1963 | serge | 350 | |
1986 | serge | 351 | connector, connector->base.id, |
352 | connector->status, connector->encoder, |
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353 | crtc); |
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354 | |||
1246 | serge | 355 | |
1986 | serge | 356 | // continue; |
357 | |||
358 | |||
1246 | serge | 359 | |
1986 | serge | 360 | |
1246 | serge | 361 | }; |
362 | |||
363 | |||
364 | }; |
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365 | |||
366 | |||
1986 | serge | 367 | |
368 | |||
1403 | serge | 369 | { |
1246 | serge | 370 | struct drm_device *dev; |
371 | |||
372 | |||
373 | bool retval = false; |
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374 | u32_t ifl; |
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375 | |||
376 | |||
1986 | serge | 377 | struct drm_fb_helper *fb_helper; |
378 | |||
379 | |||
380 | |||
381 | |||
1246 | serge | 382 | |
383 | |||
384 | |||
385 | |||
386 | |||
387 | |||
388 | { |
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389 | list_for_each_entry(cursor, &rdisplay->cursors, list) |
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390 | { |
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391 | init_cursor(cursor); |
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392 | }; |
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393 | }; |
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394 | safe_sti(ifl); |
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395 | |||
396 | |||
1986 | serge | 397 | |
398 | |||
399 | fb_helper = &rfbdev->helper; |
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400 | |||
401 | |||
402 | |||
403 | // { |
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404 | struct drm_mode_set *mode_set = &fb_helper->crtc_info[0].mode_set; |
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405 | struct drm_crtc *crtc; |
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406 | struct drm_display_mode *mode; |
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407 | |||
408 | |||
409 | |||
410 | |||
411 | // continue; |
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412 | |||
413 | |||
414 | |||
415 | |||
416 | crtc->base.id, |
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417 | drm_mode_width(mode), drm_mode_height(mode), |
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418 | drm_mode_vrefresh(mode)); |
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419 | // } |
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420 | |||
421 | |||
422 | |||
1246 | serge | 423 | if( rdisplay->connector == 0 ) |
424 | { |
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425 | dbgprintf("no active connectors\n"); |
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426 | return false; |
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427 | }; |
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428 | |||
429 | |||
1986 | serge | 430 | |
431 | |||
432 | |||
1246 | serge | 433 | |
434 | |||
1268 | serge | 435 | rdisplay->width, rdisplay->height, rdisplay->vrefresh); |
436 | dbgprintf("user mode mode %d x %d x %d\n", |
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437 | usermode->width, usermode->height, usermode->freq); |
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438 | |||
439 | |||
1246 | serge | 440 | (usermode->height != 0) && |
441 | ( (usermode->width != rdisplay->width) || |
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442 | (usermode->height != rdisplay->height) || |
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443 | (usermode->freq != rdisplay->vrefresh) ) ) |
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444 | { |
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445 | |||
446 | |||
447 | } |
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448 | |||
449 | |||
450 | { |
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451 | rdisplay->restore_cursor(0,0); |
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452 | rdisplay->init_cursor = init_cursor; |
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453 | rdisplay->select_cursor = select_cursor_kms; |
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454 | rdisplay->show_cursor = NULL; |
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455 | rdisplay->move_cursor = move_cursor_kms; |
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456 | rdisplay->restore_cursor = restore_cursor; |
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457 | rdisplay->disable_mouse = disable_mouse; |
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1313 | serge | 458 | |
1268 | serge | 459 | |
460 | radeon_show_cursor_kms(rdisplay->crtc); |
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1246 | serge | 461 | }; |
462 | safe_sti(ifl); |
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463 | |||
464 | |||
465 | |||
466 | |||
467 | }; |
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468 | |||
469 | |||
1403 | serge | 470 | { |
1246 | serge | 471 | int err = -1; |
472 | |||
473 | |||
474 | |||
475 | |||
476 | |||
477 | |||
478 | { |
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479 | *count = rdisplay->supported_modes; |
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480 | err = 0; |
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481 | } |
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482 | else if( mode != NULL ) |
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483 | { |
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484 | struct drm_display_mode *drmmode; |
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485 | int i = 0; |
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486 | |||
487 | |||
488 | *count = rdisplay->supported_modes; |
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489 | |||
490 | |||
491 | { |
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492 | if( i < *count) |
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493 | { |
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494 | mode->width = drm_mode_width(drmmode); |
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495 | mode->height = drm_mode_height(drmmode); |
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496 | mode->bpp = 32; |
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497 | mode->freq = drm_mode_vrefresh(drmmode); |
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498 | i++; |
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499 | mode++; |
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500 | } |
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501 | else break; |
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502 | }; |
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503 | *count = i; |
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504 | err = 0; |
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505 | }; |
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506 | LEAVE(); |
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507 | return err; |
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508 | } |
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509 | |||
510 | |||
1403 | serge | 511 | { |
1246 | serge | 512 | int err = -1; |
513 | |||
514 | |||
515 | |||
516 | |||
517 | mode->width, mode->height, mode->freq); |
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518 | |||
519 | |||
520 | (mode->height != 0) && |
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521 | (mode->freq != 0 ) && |
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522 | ( (mode->width != rdisplay->width) || |
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523 | (mode->height != rdisplay->height) || |
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524 | (mode->freq != rdisplay->vrefresh) ) ) |
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525 | { |
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526 | if( set_mode(rdisplay->ddev, rdisplay->connector, mode, true) ) |
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527 | err = 0; |
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528 | }; |
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529 | |||
530 | |||
531 | return err; |
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532 | }; |
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533 | |||
534 | |||
1986 | serge | 535 | |
536 | |||
537 | struct drm_mode_fb_cmd *mode_cmd, |
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538 | struct drm_gem_object **gobj_p) |
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539 | { |
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1404 | serge | 540 | struct radeon_device *rdev = rfbdev->rdev; |
1986 | serge | 541 | struct drm_gem_object *gobj = NULL; |
542 | struct radeon_bo *rbo = NULL; |
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543 | bool fb_tiled = false; /* useful for testing */ |
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544 | u32 tiling_flags = 0; |
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545 | int ret; |
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546 | int aligned_size, size; |
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547 | int height = mode_cmd->height; |
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548 | |||
1404 | serge | 549 | |
1986 | serge | 550 | static struct drm_mm_node vm_node; |
551 | |||
552 | |||
553 | mode_cmd->pitch = radeon_align_pitch(rdev, mode_cmd->width, mode_cmd->bpp, fb_tiled) * ((mode_cmd->bpp + 1) / 8); |
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554 | |||
555 | |||
556 | height = ALIGN(mode_cmd->height, 8); |
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557 | size = mode_cmd->pitch * height; |
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558 | aligned_size = ALIGN(size, PAGE_SIZE); |
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559 | |||
560 | |||
561 | if (unlikely(ret)) { |
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562 | return ret; |
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563 | } |
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1404 | serge | 564 | |
565 | |||
1986 | serge | 566 | kos_bo.gem_base.driver_private = NULL; |
567 | kos_bo.surface_reg = -1; |
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568 | kos_bo.domain = RADEON_GEM_DOMAIN_VRAM; |
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569 | |||
570 | |||
571 | |||
572 | |||
573 | rbo = gem_to_radeon_bo(gobj); |
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574 | |||
575 | |||
576 | tiling_flags = RADEON_TILING_MACRO; |
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577 | |||
578 | |||
579 | rbo->tiling_flags = tiling_flags | RADEON_TILING_SURFACE; |
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580 | rbo->pitch = mode_cmd->pitch; |
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581 | } |
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1404 | serge | 582 | |
583 | |||
1986 | serge | 584 | vm_node.start = 0; |
585 | vm_node.mm = NULL; |
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586 | |||
587 | |||
588 | rbo->tbo.offset = rbo->tbo.vm_node->start << PAGE_SHIFT; |
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589 | rbo->tbo.offset += (u64)rbo->rdev->mc.vram_start; |
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590 | rbo->kptr = (void*)0xFE000000; |
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591 | rbo->pin_count = 1; |
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592 | |||
593 | |||
594 | // radeon_bo_check_tiling(rbo, 0, 0); |
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595 | |||
596 | |||
597 | return 0; |
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598 | }><>>>><>><>><>><>><>><>><>>>><>><>><>=>><>><> |
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1404 | serge | 599 |