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5078 | serge | 1 | /* |
2 | * Copyright 2011 Advanced Micro Devices, Inc. |
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3 | * All Rights Reserved. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the |
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7 | * "Software"), to deal in the Software without restriction, including |
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8 | * without limitation the rights to use, copy, modify, merge, publish, |
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9 | * distribute, sub license, and/or sell copies of the Software, and to |
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10 | * permit persons to whom the Software is furnished to do so, subject to |
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11 | * the following conditions: |
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12 | * |
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13 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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14 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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15 | * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL |
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16 | * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, |
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17 | * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR |
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18 | * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE |
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19 | * USE OR OTHER DEALINGS IN THE SOFTWARE. |
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20 | * |
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21 | * The above copyright notice and this permission notice (including the |
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22 | * next paragraph) shall be included in all copies or substantial portions |
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23 | * of the Software. |
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24 | * |
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25 | */ |
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26 | /* |
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27 | * Authors: |
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28 | * Christian König |
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29 | */ |
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30 | |||
31 | #include |
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32 | #include |
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33 | #include |
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34 | #include |
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35 | |||
36 | #include "radeon.h" |
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37 | #include "r600d.h" |
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38 | |||
39 | /* 1 second timeout */ |
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40 | #define UVD_IDLE_TIMEOUT_MS 1000 |
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41 | |||
42 | /* Firmware Names */ |
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6104 | serge | 43 | #define FIRMWARE_R600 "radeon/R600_uvd.bin" |
44 | #define FIRMWARE_RS780 "radeon/RS780_uvd.bin" |
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45 | #define FIRMWARE_RV770 "radeon/RV770_uvd.bin" |
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5078 | serge | 46 | #define FIRMWARE_RV710 "radeon/RV710_uvd.bin" |
47 | #define FIRMWARE_CYPRESS "radeon/CYPRESS_uvd.bin" |
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48 | #define FIRMWARE_SUMO "radeon/SUMO_uvd.bin" |
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49 | #define FIRMWARE_TAHITI "radeon/TAHITI_uvd.bin" |
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50 | #define FIRMWARE_BONAIRE "radeon/BONAIRE_uvd.bin" |
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51 | |||
5271 | serge | 52 | MODULE_FIRMWARE(FIRMWARE_R600); |
53 | MODULE_FIRMWARE(FIRMWARE_RS780); |
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54 | MODULE_FIRMWARE(FIRMWARE_RV770); |
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5078 | serge | 55 | MODULE_FIRMWARE(FIRMWARE_RV710); |
56 | MODULE_FIRMWARE(FIRMWARE_CYPRESS); |
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57 | MODULE_FIRMWARE(FIRMWARE_SUMO); |
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58 | MODULE_FIRMWARE(FIRMWARE_TAHITI); |
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59 | MODULE_FIRMWARE(FIRMWARE_BONAIRE); |
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60 | |||
61 | static void radeon_uvd_idle_work_handler(struct work_struct *work); |
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62 | |||
63 | int radeon_uvd_init(struct radeon_device *rdev) |
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64 | { |
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65 | unsigned long bo_size; |
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66 | const char *fw_name; |
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67 | int i, r; |
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68 | |||
69 | // INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler); |
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70 | |||
71 | switch (rdev->family) { |
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6104 | serge | 72 | case CHIP_RV610: |
73 | case CHIP_RV630: |
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74 | case CHIP_RV670: |
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75 | case CHIP_RV620: |
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76 | case CHIP_RV635: |
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77 | fw_name = FIRMWARE_R600; |
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78 | break; |
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79 | |||
80 | case CHIP_RS780: |
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81 | case CHIP_RS880: |
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82 | fw_name = FIRMWARE_RS780; |
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83 | break; |
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84 | |||
85 | case CHIP_RV770: |
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86 | fw_name = FIRMWARE_RV770; |
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87 | break; |
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88 | |||
5078 | serge | 89 | case CHIP_RV710: |
90 | case CHIP_RV730: |
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91 | case CHIP_RV740: |
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92 | fw_name = FIRMWARE_RV710; |
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93 | break; |
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94 | |||
95 | case CHIP_CYPRESS: |
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96 | case CHIP_HEMLOCK: |
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97 | case CHIP_JUNIPER: |
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98 | case CHIP_REDWOOD: |
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99 | case CHIP_CEDAR: |
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100 | fw_name = FIRMWARE_CYPRESS; |
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101 | break; |
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102 | |||
103 | case CHIP_SUMO: |
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104 | case CHIP_SUMO2: |
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105 | case CHIP_PALM: |
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106 | case CHIP_CAYMAN: |
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107 | case CHIP_BARTS: |
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108 | case CHIP_TURKS: |
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109 | case CHIP_CAICOS: |
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110 | fw_name = FIRMWARE_SUMO; |
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111 | break; |
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112 | |||
113 | case CHIP_TAHITI: |
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114 | case CHIP_VERDE: |
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115 | case CHIP_PITCAIRN: |
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116 | case CHIP_ARUBA: |
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117 | case CHIP_OLAND: |
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118 | fw_name = FIRMWARE_TAHITI; |
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119 | break; |
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120 | |||
121 | case CHIP_BONAIRE: |
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122 | case CHIP_KABINI: |
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123 | case CHIP_KAVERI: |
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124 | case CHIP_HAWAII: |
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125 | case CHIP_MULLINS: |
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126 | fw_name = FIRMWARE_BONAIRE; |
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127 | break; |
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128 | |||
129 | default: |
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130 | return -EINVAL; |
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131 | } |
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132 | |||
133 | r = request_firmware(&rdev->uvd_fw, fw_name, rdev->dev); |
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134 | if (r) { |
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135 | dev_err(rdev->dev, "radeon_uvd: Can't load firmware \"%s\"\n", |
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136 | fw_name); |
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137 | return r; |
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138 | } |
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139 | |||
140 | bo_size = RADEON_GPU_PAGE_ALIGN(rdev->uvd_fw->size + 8) + |
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5271 | serge | 141 | RADEON_UVD_STACK_SIZE + RADEON_UVD_HEAP_SIZE + |
142 | RADEON_GPU_PAGE_SIZE; |
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5078 | serge | 143 | r = radeon_bo_create(rdev, bo_size, PAGE_SIZE, true, |
5271 | serge | 144 | RADEON_GEM_DOMAIN_VRAM, 0, NULL, |
145 | NULL, &rdev->uvd.vcpu_bo); |
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5078 | serge | 146 | if (r) { |
147 | dev_err(rdev->dev, "(%d) failed to allocate UVD bo\n", r); |
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148 | return r; |
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149 | } |
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150 | |||
151 | r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); |
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152 | if (r) { |
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153 | radeon_bo_unref(&rdev->uvd.vcpu_bo); |
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154 | dev_err(rdev->dev, "(%d) failed to reserve UVD bo\n", r); |
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155 | return r; |
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156 | } |
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157 | |||
158 | r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM, |
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159 | &rdev->uvd.gpu_addr); |
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160 | if (r) { |
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161 | radeon_bo_unreserve(rdev->uvd.vcpu_bo); |
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162 | radeon_bo_unref(&rdev->uvd.vcpu_bo); |
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163 | dev_err(rdev->dev, "(%d) UVD bo pin failed\n", r); |
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164 | return r; |
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165 | } |
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166 | |||
167 | r = radeon_bo_kmap(rdev->uvd.vcpu_bo, &rdev->uvd.cpu_addr); |
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168 | if (r) { |
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169 | dev_err(rdev->dev, "(%d) UVD map failed\n", r); |
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170 | return r; |
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171 | } |
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172 | |||
173 | radeon_bo_unreserve(rdev->uvd.vcpu_bo); |
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174 | |||
175 | for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { |
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176 | atomic_set(&rdev->uvd.handles[i], 0); |
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177 | rdev->uvd.filp[i] = NULL; |
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178 | rdev->uvd.img_size[i] = 0; |
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179 | } |
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180 | |||
181 | return 0; |
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182 | } |
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183 | |||
184 | void radeon_uvd_fini(struct radeon_device *rdev) |
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185 | { |
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186 | int r; |
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187 | |||
188 | if (rdev->uvd.vcpu_bo == NULL) |
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189 | return; |
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190 | |||
191 | r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); |
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192 | if (!r) { |
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193 | radeon_bo_kunmap(rdev->uvd.vcpu_bo); |
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194 | radeon_bo_unpin(rdev->uvd.vcpu_bo); |
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195 | radeon_bo_unreserve(rdev->uvd.vcpu_bo); |
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196 | } |
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197 | |||
198 | radeon_bo_unref(&rdev->uvd.vcpu_bo); |
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199 | |||
200 | radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_UVD_INDEX]); |
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201 | |||
202 | release_firmware(rdev->uvd_fw); |
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203 | } |
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204 | |||
205 | int radeon_uvd_suspend(struct radeon_device *rdev) |
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206 | { |
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6104 | serge | 207 | int i, r; |
5078 | serge | 208 | |
209 | if (rdev->uvd.vcpu_bo == NULL) |
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210 | return 0; |
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211 | |||
6104 | serge | 212 | for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { |
213 | uint32_t handle = atomic_read(&rdev->uvd.handles[i]); |
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214 | if (handle != 0) { |
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215 | struct radeon_fence *fence; |
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5078 | serge | 216 | |
6104 | serge | 217 | radeon_uvd_note_usage(rdev); |
5078 | serge | 218 | |
6104 | serge | 219 | r = radeon_uvd_get_destroy_msg(rdev, |
220 | R600_RING_TYPE_UVD_INDEX, handle, &fence); |
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221 | if (r) { |
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222 | DRM_ERROR("Error destroying UVD (%d)!\n", r); |
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223 | continue; |
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224 | } |
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5078 | serge | 225 | |
6104 | serge | 226 | radeon_fence_wait(fence, false); |
227 | radeon_fence_unref(&fence); |
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5078 | serge | 228 | |
6104 | serge | 229 | rdev->uvd.filp[i] = NULL; |
230 | atomic_set(&rdev->uvd.handles[i], 0); |
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231 | } |
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232 | } |
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5078 | serge | 233 | |
234 | return 0; |
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235 | } |
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236 | |||
237 | int radeon_uvd_resume(struct radeon_device *rdev) |
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238 | { |
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239 | unsigned size; |
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240 | void *ptr; |
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241 | |||
242 | if (rdev->uvd.vcpu_bo == NULL) |
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243 | return -EINVAL; |
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244 | |||
245 | memcpy(rdev->uvd.cpu_addr, rdev->uvd_fw->data, rdev->uvd_fw->size); |
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246 | |||
247 | size = radeon_bo_size(rdev->uvd.vcpu_bo); |
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248 | size -= rdev->uvd_fw->size; |
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249 | |||
250 | ptr = rdev->uvd.cpu_addr; |
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251 | ptr += rdev->uvd_fw->size; |
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252 | |||
6104 | serge | 253 | memset(ptr, 0, size); |
5078 | serge | 254 | |
255 | return 0; |
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256 | } |
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257 | |||
5271 | serge | 258 | void radeon_uvd_force_into_uvd_segment(struct radeon_bo *rbo, |
259 | uint32_t allowed_domains) |
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5078 | serge | 260 | { |
5271 | serge | 261 | int i; |
262 | |||
263 | for (i = 0; i < rbo->placement.num_placement; ++i) { |
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264 | rbo->placements[i].fpfn = 0 >> PAGE_SHIFT; |
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265 | rbo->placements[i].lpfn = (256 * 1024 * 1024) >> PAGE_SHIFT; |
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266 | } |
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267 | |||
268 | /* If it must be in VRAM it must be in the first segment as well */ |
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269 | if (allowed_domains == RADEON_GEM_DOMAIN_VRAM) |
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270 | return; |
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271 | |||
272 | /* abort if we already have more than one placement */ |
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273 | if (rbo->placement.num_placement > 1) |
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274 | return; |
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275 | |||
276 | /* add another 256MB segment */ |
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277 | rbo->placements[1] = rbo->placements[0]; |
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278 | rbo->placements[1].fpfn += (256 * 1024 * 1024) >> PAGE_SHIFT; |
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279 | rbo->placements[1].lpfn += (256 * 1024 * 1024) >> PAGE_SHIFT; |
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280 | rbo->placement.num_placement++; |
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281 | rbo->placement.num_busy_placement++; |
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5078 | serge | 282 | } |
283 | |||
284 | void radeon_uvd_free_handles(struct radeon_device *rdev, struct drm_file *filp) |
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285 | { |
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286 | int i, r; |
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287 | for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { |
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288 | uint32_t handle = atomic_read(&rdev->uvd.handles[i]); |
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289 | if (handle != 0 && rdev->uvd.filp[i] == filp) { |
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290 | struct radeon_fence *fence; |
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291 | |||
292 | radeon_uvd_note_usage(rdev); |
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293 | |||
294 | r = radeon_uvd_get_destroy_msg(rdev, |
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295 | R600_RING_TYPE_UVD_INDEX, handle, &fence); |
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296 | if (r) { |
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297 | DRM_ERROR("Error destroying UVD (%d)!\n", r); |
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298 | continue; |
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299 | } |
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300 | |||
301 | radeon_fence_wait(fence, false); |
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302 | radeon_fence_unref(&fence); |
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303 | |||
304 | rdev->uvd.filp[i] = NULL; |
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305 | atomic_set(&rdev->uvd.handles[i], 0); |
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306 | } |
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307 | } |
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308 | } |
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309 | |||
310 | static int radeon_uvd_cs_msg_decode(uint32_t *msg, unsigned buf_sizes[]) |
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311 | { |
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312 | unsigned stream_type = msg[4]; |
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313 | unsigned width = msg[6]; |
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314 | unsigned height = msg[7]; |
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315 | unsigned dpb_size = msg[9]; |
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316 | unsigned pitch = msg[28]; |
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317 | |||
318 | unsigned width_in_mb = width / 16; |
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319 | unsigned height_in_mb = ALIGN(height / 16, 2); |
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320 | |||
321 | unsigned image_size, tmp, min_dpb_size; |
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322 | |||
323 | image_size = width * height; |
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324 | image_size += image_size / 2; |
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325 | image_size = ALIGN(image_size, 1024); |
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326 | |||
327 | switch (stream_type) { |
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328 | case 0: /* H264 */ |
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329 | |||
330 | /* reference picture buffer */ |
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331 | min_dpb_size = image_size * 17; |
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332 | |||
333 | /* macroblock context buffer */ |
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334 | min_dpb_size += width_in_mb * height_in_mb * 17 * 192; |
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335 | |||
336 | /* IT surface buffer */ |
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337 | min_dpb_size += width_in_mb * height_in_mb * 32; |
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338 | break; |
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339 | |||
340 | case 1: /* VC1 */ |
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341 | |||
342 | /* reference picture buffer */ |
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343 | min_dpb_size = image_size * 3; |
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344 | |||
345 | /* CONTEXT_BUFFER */ |
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346 | min_dpb_size += width_in_mb * height_in_mb * 128; |
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347 | |||
348 | /* IT surface buffer */ |
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349 | min_dpb_size += width_in_mb * 64; |
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350 | |||
351 | /* DB surface buffer */ |
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352 | min_dpb_size += width_in_mb * 128; |
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353 | |||
354 | /* BP */ |
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355 | tmp = max(width_in_mb, height_in_mb); |
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356 | min_dpb_size += ALIGN(tmp * 7 * 16, 64); |
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357 | break; |
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358 | |||
359 | case 3: /* MPEG2 */ |
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360 | |||
361 | /* reference picture buffer */ |
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362 | min_dpb_size = image_size * 3; |
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363 | break; |
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364 | |||
365 | case 4: /* MPEG4 */ |
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366 | |||
367 | /* reference picture buffer */ |
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368 | min_dpb_size = image_size * 3; |
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369 | |||
370 | /* CM */ |
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371 | min_dpb_size += width_in_mb * height_in_mb * 64; |
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372 | |||
373 | /* IT surface buffer */ |
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374 | min_dpb_size += ALIGN(width_in_mb * height_in_mb * 32, 64); |
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375 | break; |
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376 | |||
377 | default: |
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378 | DRM_ERROR("UVD codec not handled %d!\n", stream_type); |
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379 | return -EINVAL; |
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380 | } |
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381 | |||
382 | if (width > pitch) { |
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383 | DRM_ERROR("Invalid UVD decoding target pitch!\n"); |
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384 | return -EINVAL; |
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385 | } |
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386 | |||
387 | if (dpb_size < min_dpb_size) { |
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388 | DRM_ERROR("Invalid dpb_size in UVD message (%d / %d)!\n", |
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389 | dpb_size, min_dpb_size); |
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390 | return -EINVAL; |
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391 | } |
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392 | |||
393 | buf_sizes[0x1] = dpb_size; |
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394 | buf_sizes[0x2] = image_size; |
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395 | return 0; |
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396 | } |
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397 | |||
6104 | serge | 398 | static int radeon_uvd_validate_codec(struct radeon_cs_parser *p, |
399 | unsigned stream_type) |
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400 | { |
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401 | switch (stream_type) { |
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402 | case 0: /* H264 */ |
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403 | case 1: /* VC1 */ |
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404 | /* always supported */ |
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405 | return 0; |
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406 | |||
407 | case 3: /* MPEG2 */ |
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408 | case 4: /* MPEG4 */ |
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409 | /* only since UVD 3 */ |
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410 | if (p->rdev->family >= CHIP_PALM) |
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411 | return 0; |
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412 | |||
413 | /* fall through */ |
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414 | default: |
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415 | DRM_ERROR("UVD codec not supported by hardware %d!\n", |
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416 | stream_type); |
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417 | return -EINVAL; |
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418 | } |
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419 | } |
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420 | |||
5078 | serge | 421 | static int radeon_uvd_cs_msg(struct radeon_cs_parser *p, struct radeon_bo *bo, |
422 | unsigned offset, unsigned buf_sizes[]) |
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423 | { |
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424 | int32_t *msg, msg_type, handle; |
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425 | unsigned img_size = 0; |
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5271 | serge | 426 | struct fence *f; |
5078 | serge | 427 | void *ptr; |
428 | |||
429 | int i, r; |
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430 | |||
431 | if (offset & 0x3F) { |
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432 | DRM_ERROR("UVD messages must be 64 byte aligned!\n"); |
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433 | return -EINVAL; |
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434 | } |
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435 | |||
5271 | serge | 436 | f = reservation_object_get_excl(bo->tbo.resv); |
437 | if (f) { |
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438 | r = radeon_fence_wait((struct radeon_fence *)f, false); |
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5078 | serge | 439 | if (r) { |
440 | DRM_ERROR("Failed waiting for UVD message (%d)!\n", r); |
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441 | return r; |
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442 | } |
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443 | } |
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444 | |||
445 | r = radeon_bo_kmap(bo, &ptr); |
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446 | if (r) { |
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447 | DRM_ERROR("Failed mapping the UVD message (%d)!\n", r); |
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448 | return r; |
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449 | } |
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450 | |||
451 | msg = ptr + offset; |
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452 | |||
453 | msg_type = msg[1]; |
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454 | handle = msg[2]; |
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455 | |||
456 | if (handle == 0) { |
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457 | DRM_ERROR("Invalid UVD handle!\n"); |
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458 | return -EINVAL; |
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459 | } |
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460 | |||
6104 | serge | 461 | switch (msg_type) { |
462 | case 0: |
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463 | /* it's a create msg, calc image size (width * height) */ |
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464 | img_size = msg[7] * msg[8]; |
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465 | |||
466 | r = radeon_uvd_validate_codec(p, msg[4]); |
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5078 | serge | 467 | radeon_bo_kunmap(bo); |
468 | if (r) |
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469 | return r; |
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470 | |||
6104 | serge | 471 | /* try to alloc a new handle */ |
472 | for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { |
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473 | if (atomic_read(&p->rdev->uvd.handles[i]) == handle) { |
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474 | DRM_ERROR("Handle 0x%x already in use!\n", handle); |
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475 | return -EINVAL; |
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476 | } |
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477 | |||
478 | if (!atomic_cmpxchg(&p->rdev->uvd.handles[i], 0, handle)) { |
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479 | p->rdev->uvd.filp[i] = p->filp; |
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480 | p->rdev->uvd.img_size[i] = img_size; |
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481 | return 0; |
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482 | } |
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483 | } |
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484 | |||
485 | DRM_ERROR("No more free UVD handles!\n"); |
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486 | return -EINVAL; |
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487 | |||
488 | case 1: |
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489 | /* it's a decode msg, validate codec and calc buffer sizes */ |
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490 | r = radeon_uvd_validate_codec(p, msg[4]); |
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491 | if (!r) |
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492 | r = radeon_uvd_cs_msg_decode(msg, buf_sizes); |
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493 | radeon_bo_kunmap(bo); |
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494 | if (r) |
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495 | return r; |
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496 | |||
497 | /* validate the handle */ |
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498 | for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { |
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499 | if (atomic_read(&p->rdev->uvd.handles[i]) == handle) { |
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500 | if (p->rdev->uvd.filp[i] != p->filp) { |
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501 | DRM_ERROR("UVD handle collision detected!\n"); |
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502 | return -EINVAL; |
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503 | } |
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504 | return 0; |
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505 | } |
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506 | } |
||
507 | |||
508 | DRM_ERROR("Invalid UVD handle 0x%x!\n", handle); |
||
509 | return -ENOENT; |
||
510 | |||
511 | case 2: |
||
5078 | serge | 512 | /* it's a destroy msg, free the handle */ |
513 | for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) |
||
514 | atomic_cmpxchg(&p->rdev->uvd.handles[i], handle, 0); |
||
515 | radeon_bo_kunmap(bo); |
||
516 | return 0; |
||
517 | |||
6104 | serge | 518 | default: |
5078 | serge | 519 | |
6104 | serge | 520 | DRM_ERROR("Illegal UVD message type (%d)!\n", msg_type); |
521 | return -EINVAL; |
||
5078 | serge | 522 | } |
523 | |||
6104 | serge | 524 | BUG(); |
5078 | serge | 525 | return -EINVAL; |
526 | } |
||
527 | |||
528 | static int radeon_uvd_cs_reloc(struct radeon_cs_parser *p, |
||
529 | int data0, int data1, |
||
530 | unsigned buf_sizes[], bool *has_msg_cmd) |
||
531 | { |
||
532 | struct radeon_cs_chunk *relocs_chunk; |
||
5271 | serge | 533 | struct radeon_bo_list *reloc; |
5078 | serge | 534 | unsigned idx, cmd, offset; |
535 | uint64_t start, end; |
||
536 | int r; |
||
537 | |||
5271 | serge | 538 | relocs_chunk = p->chunk_relocs; |
5078 | serge | 539 | offset = radeon_get_ib_value(p, data0); |
540 | idx = radeon_get_ib_value(p, data1); |
||
541 | if (idx >= relocs_chunk->length_dw) { |
||
542 | DRM_ERROR("Relocs at %d after relocations chunk end %d !\n", |
||
543 | idx, relocs_chunk->length_dw); |
||
544 | return -EINVAL; |
||
545 | } |
||
546 | |||
5271 | serge | 547 | reloc = &p->relocs[(idx / 4)]; |
5078 | serge | 548 | start = reloc->gpu_offset; |
549 | end = start + radeon_bo_size(reloc->robj); |
||
550 | start += offset; |
||
551 | |||
552 | p->ib.ptr[data0] = start & 0xFFFFFFFF; |
||
553 | p->ib.ptr[data1] = start >> 32; |
||
554 | |||
555 | cmd = radeon_get_ib_value(p, p->idx) >> 1; |
||
556 | |||
557 | if (cmd < 0x4) { |
||
558 | if (end <= start) { |
||
559 | DRM_ERROR("invalid reloc offset %X!\n", offset); |
||
560 | return -EINVAL; |
||
561 | } |
||
562 | if ((end - start) < buf_sizes[cmd]) { |
||
563 | DRM_ERROR("buffer (%d) to small (%d / %d)!\n", cmd, |
||
564 | (unsigned)(end - start), buf_sizes[cmd]); |
||
565 | return -EINVAL; |
||
566 | } |
||
567 | |||
568 | } else if (cmd != 0x100) { |
||
569 | DRM_ERROR("invalid UVD command %X!\n", cmd); |
||
570 | return -EINVAL; |
||
571 | } |
||
572 | |||
573 | if ((start >> 28) != ((end - 1) >> 28)) { |
||
574 | DRM_ERROR("reloc %LX-%LX crossing 256MB boundary!\n", |
||
575 | start, end); |
||
576 | return -EINVAL; |
||
577 | } |
||
578 | |||
579 | /* TODO: is this still necessary on NI+ ? */ |
||
580 | if ((cmd == 0 || cmd == 0x3) && |
||
581 | (start >> 28) != (p->rdev->uvd.gpu_addr >> 28)) { |
||
582 | DRM_ERROR("msg/fb buffer %LX-%LX out of 256MB segment!\n", |
||
583 | start, end); |
||
584 | return -EINVAL; |
||
585 | } |
||
586 | |||
587 | if (cmd == 0) { |
||
588 | if (*has_msg_cmd) { |
||
589 | DRM_ERROR("More than one message in a UVD-IB!\n"); |
||
590 | return -EINVAL; |
||
591 | } |
||
592 | *has_msg_cmd = true; |
||
593 | r = radeon_uvd_cs_msg(p, reloc->robj, offset, buf_sizes); |
||
594 | if (r) |
||
595 | return r; |
||
596 | } else if (!*has_msg_cmd) { |
||
597 | DRM_ERROR("Message needed before other commands are send!\n"); |
||
598 | return -EINVAL; |
||
599 | } |
||
600 | |||
601 | return 0; |
||
602 | } |
||
603 | |||
604 | static int radeon_uvd_cs_reg(struct radeon_cs_parser *p, |
||
605 | struct radeon_cs_packet *pkt, |
||
606 | int *data0, int *data1, |
||
607 | unsigned buf_sizes[], |
||
608 | bool *has_msg_cmd) |
||
609 | { |
||
610 | int i, r; |
||
611 | |||
612 | p->idx++; |
||
613 | for (i = 0; i <= pkt->count; ++i) { |
||
614 | switch (pkt->reg + i*4) { |
||
615 | case UVD_GPCOM_VCPU_DATA0: |
||
616 | *data0 = p->idx; |
||
617 | break; |
||
618 | case UVD_GPCOM_VCPU_DATA1: |
||
619 | *data1 = p->idx; |
||
620 | break; |
||
621 | case UVD_GPCOM_VCPU_CMD: |
||
622 | r = radeon_uvd_cs_reloc(p, *data0, *data1, |
||
623 | buf_sizes, has_msg_cmd); |
||
624 | if (r) |
||
625 | return r; |
||
626 | break; |
||
627 | case UVD_ENGINE_CNTL: |
||
628 | break; |
||
629 | default: |
||
630 | DRM_ERROR("Invalid reg 0x%X!\n", |
||
631 | pkt->reg + i*4); |
||
632 | return -EINVAL; |
||
633 | } |
||
634 | p->idx++; |
||
635 | } |
||
636 | return 0; |
||
637 | } |
||
638 | |||
639 | int radeon_uvd_cs_parse(struct radeon_cs_parser *p) |
||
640 | { |
||
641 | struct radeon_cs_packet pkt; |
||
642 | int r, data0 = 0, data1 = 0; |
||
643 | |||
644 | /* does the IB has a msg command */ |
||
645 | bool has_msg_cmd = false; |
||
646 | |||
647 | /* minimum buffer sizes */ |
||
648 | unsigned buf_sizes[] = { |
||
649 | [0x00000000] = 2048, |
||
650 | [0x00000001] = 32 * 1024 * 1024, |
||
651 | [0x00000002] = 2048 * 1152 * 3, |
||
652 | [0x00000003] = 2048, |
||
653 | }; |
||
654 | |||
5271 | serge | 655 | if (p->chunk_ib->length_dw % 16) { |
5078 | serge | 656 | DRM_ERROR("UVD IB length (%d) not 16 dwords aligned!\n", |
5271 | serge | 657 | p->chunk_ib->length_dw); |
5078 | serge | 658 | return -EINVAL; |
659 | } |
||
660 | |||
5271 | serge | 661 | if (p->chunk_relocs == NULL) { |
5078 | serge | 662 | DRM_ERROR("No relocation chunk !\n"); |
663 | return -EINVAL; |
||
664 | } |
||
665 | |||
666 | |||
667 | do { |
||
668 | r = radeon_cs_packet_parse(p, &pkt, p->idx); |
||
669 | if (r) |
||
670 | return r; |
||
671 | switch (pkt.type) { |
||
672 | case RADEON_PACKET_TYPE0: |
||
673 | r = radeon_uvd_cs_reg(p, &pkt, &data0, &data1, |
||
674 | buf_sizes, &has_msg_cmd); |
||
675 | if (r) |
||
676 | return r; |
||
677 | break; |
||
678 | case RADEON_PACKET_TYPE2: |
||
679 | p->idx += pkt.count + 2; |
||
680 | break; |
||
681 | default: |
||
682 | DRM_ERROR("Unknown packet type %d !\n", pkt.type); |
||
683 | return -EINVAL; |
||
684 | } |
||
5271 | serge | 685 | } while (p->idx < p->chunk_ib->length_dw); |
5078 | serge | 686 | |
687 | if (!has_msg_cmd) { |
||
688 | DRM_ERROR("UVD-IBs need a msg command!\n"); |
||
689 | return -EINVAL; |
||
690 | } |
||
691 | |||
692 | return 0; |
||
693 | } |
||
694 | |||
695 | static int radeon_uvd_send_msg(struct radeon_device *rdev, |
||
5271 | serge | 696 | int ring, uint64_t addr, |
5078 | serge | 697 | struct radeon_fence **fence) |
698 | { |
||
699 | struct radeon_ib ib; |
||
700 | int i, r; |
||
701 | |||
5271 | serge | 702 | r = radeon_ib_get(rdev, ring, &ib, NULL, 64); |
5078 | serge | 703 | if (r) |
704 | return r; |
||
705 | |||
706 | ib.ptr[0] = PACKET0(UVD_GPCOM_VCPU_DATA0, 0); |
||
707 | ib.ptr[1] = addr; |
||
708 | ib.ptr[2] = PACKET0(UVD_GPCOM_VCPU_DATA1, 0); |
||
709 | ib.ptr[3] = addr >> 32; |
||
710 | ib.ptr[4] = PACKET0(UVD_GPCOM_VCPU_CMD, 0); |
||
711 | ib.ptr[5] = 0; |
||
712 | for (i = 6; i < 16; ++i) |
||
713 | ib.ptr[i] = PACKET2(0); |
||
714 | ib.length_dw = 16; |
||
715 | |||
716 | r = radeon_ib_schedule(rdev, &ib, NULL, false); |
||
717 | |||
718 | if (fence) |
||
719 | *fence = radeon_fence_ref(ib.fence); |
||
720 | |||
721 | radeon_ib_free(rdev, &ib); |
||
722 | return r; |
||
723 | } |
||
724 | |||
725 | /* multiple fence commands without any stream commands in between can |
||
726 | crash the vcpu so just try to emmit a dummy create/destroy msg to |
||
727 | avoid this */ |
||
728 | int radeon_uvd_get_create_msg(struct radeon_device *rdev, int ring, |
||
729 | uint32_t handle, struct radeon_fence **fence) |
||
730 | { |
||
5271 | serge | 731 | /* we use the last page of the vcpu bo for the UVD message */ |
732 | uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) - |
||
733 | RADEON_GPU_PAGE_SIZE; |
||
734 | |||
735 | uint32_t *msg = rdev->uvd.cpu_addr + offs; |
||
736 | uint64_t addr = rdev->uvd.gpu_addr + offs; |
||
737 | |||
5078 | serge | 738 | int r, i; |
739 | |||
5271 | serge | 740 | r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true); |
5078 | serge | 741 | if (r) |
742 | return r; |
||
743 | |||
744 | /* stitch together an UVD create msg */ |
||
745 | msg[0] = cpu_to_le32(0x00000de4); |
||
746 | msg[1] = cpu_to_le32(0x00000000); |
||
747 | msg[2] = cpu_to_le32(handle); |
||
748 | msg[3] = cpu_to_le32(0x00000000); |
||
749 | msg[4] = cpu_to_le32(0x00000000); |
||
750 | msg[5] = cpu_to_le32(0x00000000); |
||
751 | msg[6] = cpu_to_le32(0x00000000); |
||
752 | msg[7] = cpu_to_le32(0x00000780); |
||
753 | msg[8] = cpu_to_le32(0x00000440); |
||
754 | msg[9] = cpu_to_le32(0x00000000); |
||
755 | msg[10] = cpu_to_le32(0x01b37000); |
||
756 | for (i = 11; i < 1024; ++i) |
||
757 | msg[i] = cpu_to_le32(0x0); |
||
758 | |||
5271 | serge | 759 | r = radeon_uvd_send_msg(rdev, ring, addr, fence); |
760 | radeon_bo_unreserve(rdev->uvd.vcpu_bo); |
||
761 | return r; |
||
5078 | serge | 762 | } |
763 | |||
764 | int radeon_uvd_get_destroy_msg(struct radeon_device *rdev, int ring, |
||
765 | uint32_t handle, struct radeon_fence **fence) |
||
766 | { |
||
5271 | serge | 767 | /* we use the last page of the vcpu bo for the UVD message */ |
768 | uint64_t offs = radeon_bo_size(rdev->uvd.vcpu_bo) - |
||
769 | RADEON_GPU_PAGE_SIZE; |
||
770 | |||
771 | uint32_t *msg = rdev->uvd.cpu_addr + offs; |
||
772 | uint64_t addr = rdev->uvd.gpu_addr + offs; |
||
773 | |||
5078 | serge | 774 | int r, i; |
775 | |||
5271 | serge | 776 | r = radeon_bo_reserve(rdev->uvd.vcpu_bo, true); |
5078 | serge | 777 | if (r) |
778 | return r; |
||
779 | |||
780 | /* stitch together an UVD destroy msg */ |
||
781 | msg[0] = cpu_to_le32(0x00000de4); |
||
782 | msg[1] = cpu_to_le32(0x00000002); |
||
783 | msg[2] = cpu_to_le32(handle); |
||
784 | msg[3] = cpu_to_le32(0x00000000); |
||
785 | for (i = 4; i < 1024; ++i) |
||
786 | msg[i] = cpu_to_le32(0x0); |
||
787 | |||
5271 | serge | 788 | r = radeon_uvd_send_msg(rdev, ring, addr, fence); |
789 | radeon_bo_unreserve(rdev->uvd.vcpu_bo); |
||
790 | return r; |
||
5078 | serge | 791 | } |
792 | |||
793 | /** |
||
794 | * radeon_uvd_count_handles - count number of open streams |
||
795 | * |
||
796 | * @rdev: radeon_device pointer |
||
797 | * @sd: number of SD streams |
||
798 | * @hd: number of HD streams |
||
799 | * |
||
800 | * Count the number of open SD/HD streams as a hint for power mangement |
||
801 | */ |
||
802 | static void radeon_uvd_count_handles(struct radeon_device *rdev, |
||
803 | unsigned *sd, unsigned *hd) |
||
804 | { |
||
805 | unsigned i; |
||
806 | |||
807 | *sd = 0; |
||
808 | *hd = 0; |
||
809 | |||
810 | for (i = 0; i < RADEON_MAX_UVD_HANDLES; ++i) { |
||
811 | if (!atomic_read(&rdev->uvd.handles[i])) |
||
812 | continue; |
||
813 | |||
814 | if (rdev->uvd.img_size[i] >= 720*576) |
||
815 | ++(*hd); |
||
816 | else |
||
817 | ++(*sd); |
||
818 | } |
||
819 | } |
||
820 | |||
821 | static void radeon_uvd_idle_work_handler(struct work_struct *work) |
||
822 | { |
||
823 | struct radeon_device *rdev = |
||
824 | container_of(work, struct radeon_device, uvd.idle_work.work); |
||
825 | |||
826 | if (radeon_fence_count_emitted(rdev, R600_RING_TYPE_UVD_INDEX) == 0) { |
||
827 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { |
||
828 | radeon_uvd_count_handles(rdev, &rdev->pm.dpm.sd, |
||
829 | &rdev->pm.dpm.hd); |
||
830 | radeon_dpm_enable_uvd(rdev, false); |
||
831 | } else { |
||
832 | radeon_set_uvd_clocks(rdev, 0, 0); |
||
833 | } |
||
834 | } else { |
||
835 | schedule_delayed_work(&rdev->uvd.idle_work, |
||
836 | msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); |
||
837 | } |
||
838 | } |
||
839 | |||
840 | void radeon_uvd_note_usage(struct radeon_device *rdev) |
||
841 | { |
||
842 | bool streams_changed = false; |
||
843 | bool set_clocks = !cancel_delayed_work_sync(&rdev->uvd.idle_work); |
||
844 | set_clocks &= schedule_delayed_work(&rdev->uvd.idle_work, |
||
845 | msecs_to_jiffies(UVD_IDLE_TIMEOUT_MS)); |
||
846 | |||
847 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { |
||
848 | unsigned hd = 0, sd = 0; |
||
849 | radeon_uvd_count_handles(rdev, &sd, &hd); |
||
850 | if ((rdev->pm.dpm.sd != sd) || |
||
851 | (rdev->pm.dpm.hd != hd)) { |
||
852 | rdev->pm.dpm.sd = sd; |
||
853 | rdev->pm.dpm.hd = hd; |
||
854 | /* disable this for now */ |
||
855 | /*streams_changed = true;*/ |
||
856 | } |
||
857 | } |
||
858 | |||
859 | if (set_clocks || streams_changed) { |
||
860 | if ((rdev->pm.pm_method == PM_METHOD_DPM) && rdev->pm.dpm_enabled) { |
||
861 | radeon_dpm_enable_uvd(rdev, true); |
||
862 | } else { |
||
863 | radeon_set_uvd_clocks(rdev, 53300, 40000); |
||
864 | } |
||
865 | } |
||
866 | } |
||
867 | |||
868 | static unsigned radeon_uvd_calc_upll_post_div(unsigned vco_freq, |
||
869 | unsigned target_freq, |
||
870 | unsigned pd_min, |
||
871 | unsigned pd_even) |
||
872 | { |
||
873 | unsigned post_div = vco_freq / target_freq; |
||
874 | |||
875 | /* adjust to post divider minimum value */ |
||
876 | if (post_div < pd_min) |
||
877 | post_div = pd_min; |
||
878 | |||
879 | /* we alway need a frequency less than or equal the target */ |
||
880 | if ((vco_freq / post_div) > target_freq) |
||
881 | post_div += 1; |
||
882 | |||
883 | /* post dividers above a certain value must be even */ |
||
884 | if (post_div > pd_even && post_div % 2) |
||
885 | post_div += 1; |
||
886 | |||
887 | return post_div; |
||
888 | } |
||
889 | |||
890 | /** |
||
891 | * radeon_uvd_calc_upll_dividers - calc UPLL clock dividers |
||
892 | * |
||
893 | * @rdev: radeon_device pointer |
||
894 | * @vclk: wanted VCLK |
||
895 | * @dclk: wanted DCLK |
||
896 | * @vco_min: minimum VCO frequency |
||
897 | * @vco_max: maximum VCO frequency |
||
898 | * @fb_factor: factor to multiply vco freq with |
||
899 | * @fb_mask: limit and bitmask for feedback divider |
||
900 | * @pd_min: post divider minimum |
||
901 | * @pd_max: post divider maximum |
||
902 | * @pd_even: post divider must be even above this value |
||
903 | * @optimal_fb_div: resulting feedback divider |
||
904 | * @optimal_vclk_div: resulting vclk post divider |
||
905 | * @optimal_dclk_div: resulting dclk post divider |
||
906 | * |
||
907 | * Calculate dividers for UVDs UPLL (R6xx-SI, except APUs). |
||
908 | * Returns zero on success -EINVAL on error. |
||
909 | */ |
||
910 | int radeon_uvd_calc_upll_dividers(struct radeon_device *rdev, |
||
911 | unsigned vclk, unsigned dclk, |
||
912 | unsigned vco_min, unsigned vco_max, |
||
913 | unsigned fb_factor, unsigned fb_mask, |
||
914 | unsigned pd_min, unsigned pd_max, |
||
915 | unsigned pd_even, |
||
916 | unsigned *optimal_fb_div, |
||
917 | unsigned *optimal_vclk_div, |
||
918 | unsigned *optimal_dclk_div) |
||
919 | { |
||
920 | unsigned vco_freq, ref_freq = rdev->clock.spll.reference_freq; |
||
921 | |||
922 | /* start off with something large */ |
||
923 | unsigned optimal_score = ~0; |
||
924 | |||
925 | /* loop through vco from low to high */ |
||
926 | vco_min = max(max(vco_min, vclk), dclk); |
||
927 | for (vco_freq = vco_min; vco_freq <= vco_max; vco_freq += 100) { |
||
928 | |||
929 | uint64_t fb_div = (uint64_t)vco_freq * fb_factor; |
||
930 | unsigned vclk_div, dclk_div, score; |
||
931 | |||
932 | do_div(fb_div, ref_freq); |
||
933 | |||
934 | /* fb div out of range ? */ |
||
935 | if (fb_div > fb_mask) |
||
936 | break; /* it can oly get worse */ |
||
937 | |||
938 | fb_div &= fb_mask; |
||
939 | |||
940 | /* calc vclk divider with current vco freq */ |
||
941 | vclk_div = radeon_uvd_calc_upll_post_div(vco_freq, vclk, |
||
942 | pd_min, pd_even); |
||
943 | if (vclk_div > pd_max) |
||
944 | break; /* vco is too big, it has to stop */ |
||
945 | |||
946 | /* calc dclk divider with current vco freq */ |
||
947 | dclk_div = radeon_uvd_calc_upll_post_div(vco_freq, dclk, |
||
948 | pd_min, pd_even); |
||
949 | if (vclk_div > pd_max) |
||
950 | break; /* vco is too big, it has to stop */ |
||
951 | |||
952 | /* calc score with current vco freq */ |
||
953 | score = vclk - (vco_freq / vclk_div) + dclk - (vco_freq / dclk_div); |
||
954 | |||
955 | /* determine if this vco setting is better than current optimal settings */ |
||
956 | if (score < optimal_score) { |
||
957 | *optimal_fb_div = fb_div; |
||
958 | *optimal_vclk_div = vclk_div; |
||
959 | *optimal_dclk_div = dclk_div; |
||
960 | optimal_score = score; |
||
961 | if (optimal_score == 0) |
||
962 | break; /* it can't get better than this */ |
||
963 | } |
||
964 | } |
||
965 | |||
966 | /* did we found a valid setup ? */ |
||
967 | if (optimal_score == ~0) |
||
968 | return -EINVAL; |
||
969 | |||
970 | return 0; |
||
971 | } |
||
972 | |||
973 | int radeon_uvd_send_upll_ctlreq(struct radeon_device *rdev, |
||
974 | unsigned cg_upll_func_cntl) |
||
975 | { |
||
976 | unsigned i; |
||
977 | |||
978 | /* make sure UPLL_CTLREQ is deasserted */ |
||
979 | WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); |
||
980 | |||
981 | mdelay(10); |
||
982 | |||
983 | /* assert UPLL_CTLREQ */ |
||
984 | WREG32_P(cg_upll_func_cntl, UPLL_CTLREQ_MASK, ~UPLL_CTLREQ_MASK); |
||
985 | |||
986 | /* wait for CTLACK and CTLACK2 to get asserted */ |
||
987 | for (i = 0; i < 100; ++i) { |
||
988 | uint32_t mask = UPLL_CTLACK_MASK | UPLL_CTLACK2_MASK; |
||
989 | if ((RREG32(cg_upll_func_cntl) & mask) == mask) |
||
990 | break; |
||
991 | mdelay(10); |
||
992 | } |
||
993 | |||
994 | /* deassert UPLL_CTLREQ */ |
||
995 | WREG32_P(cg_upll_func_cntl, 0, ~UPLL_CTLREQ_MASK); |
||
996 | |||
997 | if (i == 100) { |
||
998 | DRM_ERROR("Timeout setting UVD clocks!\n"); |
||
999 | return -ETIMEDOUT; |
||
1000 | } |
||
1001 | |||
1002 | return 0; |
||
1003 | }>>=>>>>>>>=>>=>>>>>>>>>> |