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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1179 | serge | 28 | #include |
1125 | serge | 29 | #include "drmP.h" |
1117 | serge | 30 | #include "radeon_drm.h" |
31 | #include "radeon_reg.h" |
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32 | #include "radeon.h" |
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33 | #include "atom.h" |
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34 | |||
35 | int radeon_debugfs_ib_init(struct radeon_device *rdev); |
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36 | |||
37 | /* |
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38 | * IB. |
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39 | */ |
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1120 | serge | 40 | |
41 | #if 0 |
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42 | |||
1117 | serge | 43 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib) |
44 | { |
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45 | struct radeon_fence *fence; |
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46 | struct radeon_ib *nib; |
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1428 | serge | 47 | int r = 0, i, c; |
1117 | serge | 48 | |
49 | *ib = NULL; |
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50 | r = radeon_fence_create(rdev, &fence); |
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51 | if (r) { |
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1428 | serge | 52 | dev_err(rdev->dev, "failed to create fence for new IB\n"); |
1117 | serge | 53 | return r; |
54 | } |
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55 | mutex_lock(&rdev->ib_pool.mutex); |
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1428 | serge | 56 | for (i = rdev->ib_pool.head_id, c = 0, nib = NULL; c < RADEON_IB_POOL_SIZE; c++, i++) { |
57 | i &= (RADEON_IB_POOL_SIZE - 1); |
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58 | if (rdev->ib_pool.ibs[i].free) { |
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59 | nib = &rdev->ib_pool.ibs[i]; |
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60 | break; |
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1117 | serge | 61 | } |
1428 | serge | 62 | } |
63 | if (nib == NULL) { |
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64 | /* This should never happen, it means we allocated all |
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65 | * IB and haven't scheduled one yet, return EBUSY to |
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66 | * userspace hoping that on ioctl recall we get better |
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67 | * luck |
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68 | */ |
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69 | dev_err(rdev->dev, "no free indirect buffer !\n"); |
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1179 | serge | 70 | mutex_unlock(&rdev->ib_pool.mutex); |
1428 | serge | 71 | radeon_fence_unref(&fence); |
72 | return -EBUSY; |
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1117 | serge | 73 | } |
1428 | serge | 74 | rdev->ib_pool.head_id = (nib->idx + 1) & (RADEON_IB_POOL_SIZE - 1); |
75 | nib->free = false; |
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76 | if (nib->fence) { |
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1179 | serge | 77 | mutex_unlock(&rdev->ib_pool.mutex); |
1117 | serge | 78 | r = radeon_fence_wait(nib->fence, false); |
79 | if (r) { |
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1428 | serge | 80 | dev_err(rdev->dev, "error waiting fence of IB(%u:0x%016lX:%u)\n", |
81 | nib->idx, (unsigned long)nib->gpu_addr, nib->length_dw); |
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82 | mutex_lock(&rdev->ib_pool.mutex); |
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83 | nib->free = true; |
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84 | mutex_unlock(&rdev->ib_pool.mutex); |
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85 | radeon_fence_unref(&fence); |
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86 | return r; |
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1117 | serge | 87 | } |
1428 | serge | 88 | mutex_lock(&rdev->ib_pool.mutex); |
89 | } |
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1117 | serge | 90 | radeon_fence_unref(&nib->fence); |
1428 | serge | 91 | nib->fence = fence; |
1117 | serge | 92 | nib->length_dw = 0; |
1179 | serge | 93 | mutex_unlock(&rdev->ib_pool.mutex); |
1117 | serge | 94 | *ib = nib; |
1428 | serge | 95 | return 0; |
1117 | serge | 96 | } |
97 | |||
98 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib) |
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99 | { |
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100 | struct radeon_ib *tmp = *ib; |
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101 | |||
102 | *ib = NULL; |
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103 | if (tmp == NULL) { |
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104 | return; |
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105 | } |
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1428 | serge | 106 | if (!tmp->fence->emited) |
107 | radeon_fence_unref(&tmp->fence); |
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1117 | serge | 108 | mutex_lock(&rdev->ib_pool.mutex); |
1428 | serge | 109 | tmp->free = true; |
1117 | serge | 110 | mutex_unlock(&rdev->ib_pool.mutex); |
111 | } |
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112 | |||
113 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib) |
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114 | { |
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115 | int r = 0; |
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116 | |||
117 | if (!ib->length_dw || !rdev->cp.ready) { |
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118 | /* TODO: Nothings in the ib we should report. */ |
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1428 | serge | 119 | DRM_ERROR("radeon: couldn't schedule IB(%u).\n", ib->idx); |
1117 | serge | 120 | return -EINVAL; |
121 | } |
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1179 | serge | 122 | |
123 | /* 64 dwords should be enough for fence too */ |
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1117 | serge | 124 | r = radeon_ring_lock(rdev, 64); |
125 | if (r) { |
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126 | DRM_ERROR("radeon: scheduling IB failled (%d).\n", r); |
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127 | return r; |
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128 | } |
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1179 | serge | 129 | radeon_ring_ib_execute(rdev, ib); |
1117 | serge | 130 | radeon_fence_emit(rdev, ib->fence); |
1179 | serge | 131 | mutex_lock(&rdev->ib_pool.mutex); |
1428 | serge | 132 | /* once scheduled IB is considered free and protected by the fence */ |
133 | ib->free = true; |
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1117 | serge | 134 | mutex_unlock(&rdev->ib_pool.mutex); |
1179 | serge | 135 | radeon_ring_unlock_commit(rdev); |
1117 | serge | 136 | return 0; |
137 | } |
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1120 | serge | 138 | #endif |
1117 | serge | 139 | |
140 | int radeon_ib_pool_init(struct radeon_device *rdev) |
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141 | { |
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142 | void *ptr; |
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143 | uint64_t gpu_addr; |
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144 | int i; |
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145 | int r = 0; |
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146 | |||
1179 | serge | 147 | if (rdev->ib_pool.robj) |
148 | return 0; |
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1117 | serge | 149 | /* Allocate 1M object buffer */ |
1404 | serge | 150 | r = radeon_bo_create(rdev, NULL, RADEON_IB_POOL_SIZE*64*1024, |
1117 | serge | 151 | true, RADEON_GEM_DOMAIN_GTT, |
1404 | serge | 152 | &rdev->ib_pool.robj); |
1117 | serge | 153 | if (r) { |
154 | DRM_ERROR("radeon: failed to ib pool (%d).\n", r); |
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155 | return r; |
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156 | } |
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1404 | serge | 157 | r = radeon_bo_reserve(rdev->ib_pool.robj, false); |
158 | if (unlikely(r != 0)) |
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159 | return r; |
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160 | r = radeon_bo_pin(rdev->ib_pool.robj, RADEON_GEM_DOMAIN_GTT, &gpu_addr); |
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1117 | serge | 161 | if (r) { |
1404 | serge | 162 | radeon_bo_unreserve(rdev->ib_pool.robj); |
1117 | serge | 163 | DRM_ERROR("radeon: failed to pin ib pool (%d).\n", r); |
164 | return r; |
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165 | } |
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1404 | serge | 166 | r = radeon_bo_kmap(rdev->ib_pool.robj, &ptr); |
167 | radeon_bo_unreserve(rdev->ib_pool.robj); |
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1117 | serge | 168 | if (r) { |
169 | DRM_ERROR("radeon: failed to map ib poll (%d).\n", r); |
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170 | return r; |
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171 | } |
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172 | for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { |
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173 | unsigned offset; |
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174 | |||
175 | offset = i * 64 * 1024; |
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176 | rdev->ib_pool.ibs[i].gpu_addr = gpu_addr + offset; |
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177 | rdev->ib_pool.ibs[i].ptr = ptr + offset; |
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178 | rdev->ib_pool.ibs[i].idx = i; |
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179 | rdev->ib_pool.ibs[i].length_dw = 0; |
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1428 | serge | 180 | rdev->ib_pool.ibs[i].free = true; |
1117 | serge | 181 | } |
1428 | serge | 182 | rdev->ib_pool.head_id = 0; |
1117 | serge | 183 | rdev->ib_pool.ready = true; |
184 | DRM_INFO("radeon: ib pool ready.\n"); |
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1129 | serge | 185 | if (radeon_debugfs_ib_init(rdev)) { |
186 | DRM_ERROR("Failed to register debugfs file for IB !\n"); |
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187 | } |
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1117 | serge | 188 | return r; |
189 | } |
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190 | |||
191 | void radeon_ib_pool_fini(struct radeon_device *rdev) |
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192 | { |
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1404 | serge | 193 | int r; |
194 | |||
1117 | serge | 195 | if (!rdev->ib_pool.ready) { |
196 | return; |
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197 | } |
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1179 | serge | 198 | mutex_lock(&rdev->ib_pool.mutex); |
1117 | serge | 199 | if (rdev->ib_pool.robj) { |
1404 | serge | 200 | r = radeon_bo_reserve(rdev->ib_pool.robj, false); |
201 | if (likely(r == 0)) { |
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202 | radeon_bo_kunmap(rdev->ib_pool.robj); |
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203 | radeon_bo_unpin(rdev->ib_pool.robj); |
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204 | radeon_bo_unreserve(rdev->ib_pool.robj); |
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205 | } |
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206 | radeon_bo_unref(&rdev->ib_pool.robj); |
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1117 | serge | 207 | rdev->ib_pool.robj = NULL; |
208 | } |
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1179 | serge | 209 | mutex_unlock(&rdev->ib_pool.mutex); |
1117 | serge | 210 | } |
211 | |||
1120 | serge | 212 | |
1117 | serge | 213 | /* |
214 | * Ring. |
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215 | */ |
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216 | void radeon_ring_free_size(struct radeon_device *rdev) |
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217 | { |
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1179 | serge | 218 | if (rdev->family >= CHIP_R600) |
219 | rdev->cp.rptr = RREG32(R600_CP_RB_RPTR); |
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220 | else |
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1117 | serge | 221 | rdev->cp.rptr = RREG32(RADEON_CP_RB_RPTR); |
222 | /* This works because ring_size is a power of 2 */ |
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223 | rdev->cp.ring_free_dw = (rdev->cp.rptr + (rdev->cp.ring_size / 4)); |
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224 | rdev->cp.ring_free_dw -= rdev->cp.wptr; |
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225 | rdev->cp.ring_free_dw &= rdev->cp.ptr_mask; |
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226 | if (!rdev->cp.ring_free_dw) { |
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227 | rdev->cp.ring_free_dw = rdev->cp.ring_size / 4; |
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228 | } |
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229 | } |
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230 | |||
231 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw) |
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232 | { |
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233 | int r; |
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234 | |||
235 | /* Align requested size with padding so unlock_commit can |
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236 | * pad safely */ |
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237 | ndw = (ndw + rdev->cp.align_mask) & ~rdev->cp.align_mask; |
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1179 | serge | 238 | mutex_lock(&rdev->cp.mutex); |
1117 | serge | 239 | while (ndw > (rdev->cp.ring_free_dw - 1)) { |
240 | radeon_ring_free_size(rdev); |
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241 | if (ndw < rdev->cp.ring_free_dw) { |
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242 | break; |
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243 | } |
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244 | // r = radeon_fence_wait_next(rdev); |
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245 | // if (r) { |
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246 | // mutex_unlock(&rdev->cp.mutex); |
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247 | // return r; |
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248 | // } |
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249 | } |
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250 | rdev->cp.count_dw = ndw; |
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251 | rdev->cp.wptr_old = rdev->cp.wptr; |
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252 | return 0; |
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253 | } |
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254 | |||
255 | void radeon_ring_unlock_commit(struct radeon_device *rdev) |
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256 | { |
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257 | unsigned count_dw_pad; |
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258 | unsigned i; |
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259 | |||
260 | /* We pad to match fetch size */ |
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261 | count_dw_pad = (rdev->cp.align_mask + 1) - |
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262 | (rdev->cp.wptr & rdev->cp.align_mask); |
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263 | for (i = 0; i < count_dw_pad; i++) { |
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1179 | serge | 264 | radeon_ring_write(rdev, 2 << 30); |
1117 | serge | 265 | } |
266 | DRM_MEMORYBARRIER(); |
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1179 | serge | 267 | radeon_cp_commit(rdev); |
268 | mutex_unlock(&rdev->cp.mutex); |
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1117 | serge | 269 | } |
270 | |||
271 | void radeon_ring_unlock_undo(struct radeon_device *rdev) |
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272 | { |
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273 | rdev->cp.wptr = rdev->cp.wptr_old; |
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1179 | serge | 274 | mutex_unlock(&rdev->cp.mutex); |
1117 | serge | 275 | } |
276 | |||
277 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size) |
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278 | { |
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279 | int r; |
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280 | |||
1179 | serge | 281 | ENTER(); |
1117 | serge | 282 | |
283 | rdev->cp.ring_size = ring_size; |
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1120 | serge | 284 | /* Allocate ring buffer */ |
1117 | serge | 285 | if (rdev->cp.ring_obj == NULL) { |
1404 | serge | 286 | r = radeon_bo_create(rdev, NULL, rdev->cp.ring_size, true, |
1117 | serge | 287 | RADEON_GEM_DOMAIN_GTT, |
288 | &rdev->cp.ring_obj); |
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289 | if (r) { |
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1404 | serge | 290 | dev_err(rdev->dev, "(%d) ring create failed\n", r); |
1117 | serge | 291 | return r; |
292 | } |
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1404 | serge | 293 | r = radeon_bo_reserve(rdev->cp.ring_obj, false); |
294 | if (unlikely(r != 0)) |
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295 | return r; |
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296 | r = radeon_bo_pin(rdev->cp.ring_obj, RADEON_GEM_DOMAIN_GTT, |
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1117 | serge | 297 | &rdev->cp.gpu_addr); |
298 | if (r) { |
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1404 | serge | 299 | radeon_bo_unreserve(rdev->cp.ring_obj); |
300 | dev_err(rdev->dev, "(%d) ring pin failed\n", r); |
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1117 | serge | 301 | return r; |
302 | } |
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1404 | serge | 303 | r = radeon_bo_kmap(rdev->cp.ring_obj, |
1117 | serge | 304 | (void **)&rdev->cp.ring); |
1404 | serge | 305 | radeon_bo_unreserve(rdev->cp.ring_obj); |
1117 | serge | 306 | if (r) { |
1404 | serge | 307 | dev_err(rdev->dev, "(%d) ring map failed\n", r); |
1117 | serge | 308 | return r; |
309 | } |
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310 | } |
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311 | rdev->cp.ptr_mask = (rdev->cp.ring_size / 4) - 1; |
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312 | rdev->cp.ring_free_dw = rdev->cp.ring_size / 4; |
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1119 | serge | 313 | |
1179 | serge | 314 | LEAVE(); |
1119 | serge | 315 | |
1117 | serge | 316 | return 0; |
317 | } |
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318 | |||
319 | void radeon_ring_fini(struct radeon_device *rdev) |
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320 | { |
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1404 | serge | 321 | int r; |
322 | |||
1179 | serge | 323 | mutex_lock(&rdev->cp.mutex); |
1117 | serge | 324 | if (rdev->cp.ring_obj) { |
1404 | serge | 325 | r = radeon_bo_reserve(rdev->cp.ring_obj, false); |
326 | if (likely(r == 0)) { |
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327 | radeon_bo_kunmap(rdev->cp.ring_obj); |
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328 | radeon_bo_unpin(rdev->cp.ring_obj); |
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329 | radeon_bo_unreserve(rdev->cp.ring_obj); |
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330 | } |
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331 | radeon_bo_unref(&rdev->cp.ring_obj); |
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1117 | serge | 332 | rdev->cp.ring = NULL; |
333 | rdev->cp.ring_obj = NULL; |
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334 | } |
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1179 | serge | 335 | mutex_unlock(&rdev->cp.mutex); |
1117 | serge | 336 | } |
337 | |||
338 | |||
339 | /* |
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340 | * Debugfs info |
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341 | */ |
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342 | #if defined(CONFIG_DEBUG_FS) |
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343 | static int radeon_debugfs_ib_info(struct seq_file *m, void *data) |
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344 | { |
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345 | struct drm_info_node *node = (struct drm_info_node *) m->private; |
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346 | struct radeon_ib *ib = node->info_ent->data; |
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347 | unsigned i; |
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348 | |||
349 | if (ib == NULL) { |
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350 | return 0; |
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351 | } |
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1428 | serge | 352 | seq_printf(m, "IB %04u\n", ib->idx); |
1117 | serge | 353 | seq_printf(m, "IB fence %p\n", ib->fence); |
354 | seq_printf(m, "IB size %05u dwords\n", ib->length_dw); |
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355 | for (i = 0; i < ib->length_dw; i++) { |
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356 | seq_printf(m, "[%05u]=0x%08X\n", i, ib->ptr[i]); |
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357 | } |
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358 | return 0; |
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359 | } |
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360 | |||
361 | static struct drm_info_list radeon_debugfs_ib_list[RADEON_IB_POOL_SIZE]; |
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362 | static char radeon_debugfs_ib_names[RADEON_IB_POOL_SIZE][32]; |
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363 | #endif |
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364 | |||
365 | int radeon_debugfs_ib_init(struct radeon_device *rdev) |
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366 | { |
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367 | #if defined(CONFIG_DEBUG_FS) |
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368 | unsigned i; |
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369 | |||
370 | for (i = 0; i < RADEON_IB_POOL_SIZE; i++) { |
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371 | sprintf(radeon_debugfs_ib_names[i], "radeon_ib_%04u", i); |
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372 | radeon_debugfs_ib_list[i].name = radeon_debugfs_ib_names[i]; |
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373 | radeon_debugfs_ib_list[i].show = &radeon_debugfs_ib_info; |
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374 | radeon_debugfs_ib_list[i].driver_features = 0; |
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375 | radeon_debugfs_ib_list[i].data = &rdev->ib_pool.ibs[i]; |
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376 | } |
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377 | return radeon_debugfs_add_files(rdev, radeon_debugfs_ib_list, |
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378 | RADEON_IB_POOL_SIZE); |
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379 | #else |
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380 | return 0; |
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381 | #endif |
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382 | }>>><>>>>> |