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Rev | Author | Line No. | Line |
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1123 | serge | 1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be included in |
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13 | * all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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21 | * OTHER DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: Dave Airlie |
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24 | * Alex Deucher |
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25 | */ |
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2997 | Serge | 26 | #include |
27 | |||
28 | #include |
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29 | #include |
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30 | #include |
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1123 | serge | 31 | #include "radeon.h" |
1430 | serge | 32 | #include "atom.h" |
1123 | serge | 33 | |
2997 | Serge | 34 | extern int radeon_atom_hw_i2c_xfer(struct i2c_adapter *i2c_adap, |
35 | struct i2c_msg *msgs, int num); |
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36 | extern u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap); |
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37 | |||
1123 | serge | 38 | /** |
39 | * radeon_ddc_probe |
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40 | * |
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41 | */ |
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3192 | Serge | 42 | bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux) |
1123 | serge | 43 | { |
2160 | serge | 44 | u8 out = 0x0; |
45 | u8 buf[8]; |
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1123 | serge | 46 | int ret; |
47 | struct i2c_msg msgs[] = { |
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48 | { |
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2997 | Serge | 49 | .addr = DDC_ADDR, |
1123 | serge | 50 | .flags = 0, |
51 | .len = 1, |
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2160 | serge | 52 | .buf = &out, |
1123 | serge | 53 | }, |
54 | { |
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2997 | Serge | 55 | .addr = DDC_ADDR, |
1123 | serge | 56 | .flags = I2C_M_RD, |
2997 | Serge | 57 | .len = 8, |
1123 | serge | 58 | .buf = buf, |
59 | } |
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60 | }; |
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61 | |||
1963 | serge | 62 | /* on hw with routers, select right port */ |
63 | if (radeon_connector->router.ddc_valid) |
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64 | radeon_router_select_ddc_port(radeon_connector); |
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65 | |||
3192 | Serge | 66 | if (use_aux) { |
5078 | serge | 67 | ret = i2c_transfer(&radeon_connector->ddc_bus->aux.ddc, msgs, 2); |
3192 | Serge | 68 | } else { |
6104 | serge | 69 | ret = i2c_transfer(&radeon_connector->ddc_bus->adapter, msgs, 2); |
3192 | Serge | 70 | } |
71 | |||
2160 | serge | 72 | if (ret != 2) |
73 | /* Couldn't find an accessible DDC on this connector */ |
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74 | return false; |
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6104 | serge | 75 | /* Probe also for valid EDID header |
76 | * EDID header starts with: |
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77 | * 0x00,0xFF,0xFF,0xFF,0xFF,0xFF,0xFF,0x00. |
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78 | * Only the first 6 bytes must be valid as |
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79 | * drm_edid_block_valid() can fix the last 2 bytes */ |
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80 | if (drm_edid_header_is_valid(buf) < 6) { |
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81 | /* Couldn't find an accessible EDID on this |
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82 | * connector */ |
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83 | return false; |
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84 | } |
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85 | return true; |
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1123 | serge | 86 | } |
87 | |||
1963 | serge | 88 | /* bit banging i2c */ |
1123 | serge | 89 | |
2997 | Serge | 90 | static int pre_xfer(struct i2c_adapter *i2c_adap) |
1123 | serge | 91 | { |
2997 | Serge | 92 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); |
1321 | serge | 93 | struct radeon_device *rdev = i2c->dev->dev_private; |
94 | struct radeon_i2c_bus_rec *rec = &i2c->rec; |
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1123 | serge | 95 | uint32_t temp; |
96 | |||
5078 | serge | 97 | mutex_lock(&i2c->mutex); |
98 | |||
1123 | serge | 99 | /* RV410 appears to have a bug where the hw i2c in reset |
100 | * holds the i2c port in a bad state - switch hw i2c away before |
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101 | * doing DDC - do this for all r200s/r300s/r400s for safety sake |
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102 | */ |
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1321 | serge | 103 | if (rec->hw_capable) { |
6104 | serge | 104 | if ((rdev->family >= CHIP_R200) && !ASIC_IS_AVIVO(rdev)) { |
1430 | serge | 105 | u32 reg; |
106 | |||
107 | if (rdev->family >= CHIP_RV350) |
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108 | reg = RADEON_GPIO_MONID; |
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109 | else if ((rdev->family == CHIP_R300) || |
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110 | (rdev->family == CHIP_R350)) |
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111 | reg = RADEON_GPIO_DVI_DDC; |
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112 | else |
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113 | reg = RADEON_GPIO_CRT2_DDC; |
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114 | |||
115 | mutex_lock(&rdev->dc_hw_i2c_mutex); |
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116 | if (rec->a_clk_reg == reg) { |
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6104 | serge | 117 | WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | |
118 | R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1))); |
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119 | } else { |
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120 | WREG32(RADEON_DVI_I2C_CNTL_0, (RADEON_I2C_SOFT_RST | |
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121 | R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3))); |
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122 | } |
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123 | mutex_unlock(&rdev->dc_hw_i2c_mutex); |
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1123 | serge | 124 | } |
125 | } |
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1321 | serge | 126 | |
1963 | serge | 127 | /* switch the pads to ddc mode */ |
128 | if (ASIC_IS_DCE3(rdev) && rec->hw_capable) { |
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129 | temp = RREG32(rec->mask_clk_reg); |
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130 | temp &= ~(1 << 16); |
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131 | WREG32(rec->mask_clk_reg, temp); |
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132 | } |
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133 | |||
1321 | serge | 134 | /* clear the output pin values */ |
135 | temp = RREG32(rec->a_clk_reg) & ~rec->a_clk_mask; |
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6104 | serge | 136 | WREG32(rec->a_clk_reg, temp); |
1123 | serge | 137 | |
1321 | serge | 138 | temp = RREG32(rec->a_data_reg) & ~rec->a_data_mask; |
6104 | serge | 139 | WREG32(rec->a_data_reg, temp); |
1123 | serge | 140 | |
1321 | serge | 141 | /* set the pins to input */ |
142 | temp = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; |
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143 | WREG32(rec->en_clk_reg, temp); |
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144 | |||
145 | temp = RREG32(rec->en_data_reg) & ~rec->en_data_mask; |
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146 | WREG32(rec->en_data_reg, temp); |
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147 | |||
148 | /* mask the gpio pins for software use */ |
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2997 | Serge | 149 | temp = RREG32(rec->mask_clk_reg) | rec->mask_clk_mask; |
150 | WREG32(rec->mask_clk_reg, temp); |
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1123 | serge | 151 | temp = RREG32(rec->mask_clk_reg); |
2997 | Serge | 152 | |
153 | temp = RREG32(rec->mask_data_reg) | rec->mask_data_mask; |
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154 | WREG32(rec->mask_data_reg, temp); |
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155 | temp = RREG32(rec->mask_data_reg); |
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156 | |||
157 | return 0; |
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158 | } |
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159 | |||
160 | static void post_xfer(struct i2c_adapter *i2c_adap) |
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161 | { |
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162 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); |
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163 | struct radeon_device *rdev = i2c->dev->dev_private; |
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164 | struct radeon_i2c_bus_rec *rec = &i2c->rec; |
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165 | uint32_t temp; |
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166 | |||
167 | /* unmask the gpio pins for software use */ |
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168 | temp = RREG32(rec->mask_clk_reg) & ~rec->mask_clk_mask; |
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1123 | serge | 169 | WREG32(rec->mask_clk_reg, temp); |
170 | temp = RREG32(rec->mask_clk_reg); |
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171 | |||
2997 | Serge | 172 | temp = RREG32(rec->mask_data_reg) & ~rec->mask_data_mask; |
1123 | serge | 173 | WREG32(rec->mask_data_reg, temp); |
174 | temp = RREG32(rec->mask_data_reg); |
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5078 | serge | 175 | |
176 | mutex_unlock(&i2c->mutex); |
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1123 | serge | 177 | } |
178 | |||
179 | static int get_clock(void *i2c_priv) |
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180 | { |
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181 | struct radeon_i2c_chan *i2c = i2c_priv; |
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182 | struct radeon_device *rdev = i2c->dev->dev_private; |
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183 | struct radeon_i2c_bus_rec *rec = &i2c->rec; |
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184 | uint32_t val; |
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185 | |||
1321 | serge | 186 | /* read the value off the pin */ |
187 | val = RREG32(rec->y_clk_reg); |
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188 | val &= rec->y_clk_mask; |
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1123 | serge | 189 | |
190 | return (val != 0); |
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191 | } |
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192 | |||
193 | |||
194 | static int get_data(void *i2c_priv) |
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195 | { |
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196 | struct radeon_i2c_chan *i2c = i2c_priv; |
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197 | struct radeon_device *rdev = i2c->dev->dev_private; |
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198 | struct radeon_i2c_bus_rec *rec = &i2c->rec; |
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199 | uint32_t val; |
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200 | |||
1321 | serge | 201 | /* read the value off the pin */ |
202 | val = RREG32(rec->y_data_reg); |
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203 | val &= rec->y_data_mask; |
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204 | |||
1123 | serge | 205 | return (val != 0); |
206 | } |
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207 | |||
208 | static void set_clock(void *i2c_priv, int clock) |
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209 | { |
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210 | struct radeon_i2c_chan *i2c = i2c_priv; |
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211 | struct radeon_device *rdev = i2c->dev->dev_private; |
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212 | struct radeon_i2c_bus_rec *rec = &i2c->rec; |
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213 | uint32_t val; |
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214 | |||
1321 | serge | 215 | /* set pin direction */ |
216 | val = RREG32(rec->en_clk_reg) & ~rec->en_clk_mask; |
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217 | val |= clock ? 0 : rec->en_clk_mask; |
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218 | WREG32(rec->en_clk_reg, val); |
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1123 | serge | 219 | } |
220 | |||
221 | static void set_data(void *i2c_priv, int data) |
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222 | { |
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223 | struct radeon_i2c_chan *i2c = i2c_priv; |
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224 | struct radeon_device *rdev = i2c->dev->dev_private; |
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225 | struct radeon_i2c_bus_rec *rec = &i2c->rec; |
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226 | uint32_t val; |
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227 | |||
1321 | serge | 228 | /* set pin direction */ |
229 | val = RREG32(rec->en_data_reg) & ~rec->en_data_mask; |
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230 | val |= data ? 0 : rec->en_data_mask; |
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231 | WREG32(rec->en_data_reg, val); |
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1123 | serge | 232 | } |
233 | |||
1963 | serge | 234 | /* hw i2c */ |
235 | |||
1430 | serge | 236 | static u32 radeon_get_i2c_prescale(struct radeon_device *rdev) |
237 | { |
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1963 | serge | 238 | u32 sclk = rdev->pm.current_sclk; |
1430 | serge | 239 | u32 prescale = 0; |
1963 | serge | 240 | u32 nm; |
241 | u8 n, m, loop; |
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1430 | serge | 242 | int i2c_clock; |
243 | |||
244 | switch (rdev->family) { |
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245 | case CHIP_R100: |
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246 | case CHIP_RV100: |
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247 | case CHIP_RS100: |
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248 | case CHIP_RV200: |
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249 | case CHIP_RS200: |
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250 | case CHIP_R200: |
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251 | case CHIP_RV250: |
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252 | case CHIP_RS300: |
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253 | case CHIP_RV280: |
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254 | case CHIP_R300: |
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255 | case CHIP_R350: |
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256 | case CHIP_RV350: |
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1963 | serge | 257 | i2c_clock = 60; |
258 | nm = (sclk * 10) / (i2c_clock * 4); |
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1430 | serge | 259 | for (loop = 1; loop < 255; loop++) { |
1963 | serge | 260 | if ((nm / loop) < loop) |
1430 | serge | 261 | break; |
262 | } |
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1963 | serge | 263 | n = loop - 1; |
264 | m = loop - 2; |
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265 | prescale = m | (n << 8); |
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1430 | serge | 266 | break; |
267 | case CHIP_RV380: |
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268 | case CHIP_RS400: |
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269 | case CHIP_RS480: |
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270 | case CHIP_R420: |
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271 | case CHIP_R423: |
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272 | case CHIP_RV410: |
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273 | prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; |
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274 | break; |
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275 | case CHIP_RS600: |
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276 | case CHIP_RS690: |
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277 | case CHIP_RS740: |
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278 | /* todo */ |
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279 | break; |
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280 | case CHIP_RV515: |
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281 | case CHIP_R520: |
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282 | case CHIP_RV530: |
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283 | case CHIP_RV560: |
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284 | case CHIP_RV570: |
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285 | case CHIP_R580: |
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286 | i2c_clock = 50; |
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287 | if (rdev->family == CHIP_R520) |
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288 | prescale = (127 << 8) + ((sclk * 10) / (4 * 127 * i2c_clock)); |
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289 | else |
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290 | prescale = (((sclk * 10)/(4 * 128 * 100) + 1) << 8) + 128; |
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291 | break; |
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292 | case CHIP_R600: |
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293 | case CHIP_RV610: |
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294 | case CHIP_RV630: |
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295 | case CHIP_RV670: |
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296 | /* todo */ |
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297 | break; |
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298 | case CHIP_RV620: |
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299 | case CHIP_RV635: |
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300 | case CHIP_RS780: |
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301 | case CHIP_RS880: |
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302 | case CHIP_RV770: |
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303 | case CHIP_RV730: |
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304 | case CHIP_RV710: |
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305 | case CHIP_RV740: |
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306 | /* todo */ |
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307 | break; |
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308 | case CHIP_CEDAR: |
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309 | case CHIP_REDWOOD: |
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310 | case CHIP_JUNIPER: |
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311 | case CHIP_CYPRESS: |
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312 | case CHIP_HEMLOCK: |
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313 | /* todo */ |
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314 | break; |
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315 | default: |
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316 | DRM_ERROR("i2c: unhandled radeon chip\n"); |
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317 | break; |
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318 | } |
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319 | return prescale; |
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320 | } |
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321 | |||
322 | |||
323 | /* hw i2c engine for r1xx-4xx hardware |
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324 | * hw can buffer up to 15 bytes |
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325 | */ |
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326 | static int r100_hw_i2c_xfer(struct i2c_adapter *i2c_adap, |
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327 | struct i2c_msg *msgs, int num) |
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328 | { |
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329 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); |
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330 | struct radeon_device *rdev = i2c->dev->dev_private; |
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331 | struct radeon_i2c_bus_rec *rec = &i2c->rec; |
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332 | struct i2c_msg *p; |
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333 | int i, j, k, ret = num; |
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334 | u32 prescale; |
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335 | u32 i2c_cntl_0, i2c_cntl_1, i2c_data; |
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336 | u32 tmp, reg; |
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337 | |||
338 | mutex_lock(&rdev->dc_hw_i2c_mutex); |
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339 | /* take the pm lock since we need a constant sclk */ |
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340 | mutex_lock(&rdev->pm.mutex); |
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341 | |||
342 | prescale = radeon_get_i2c_prescale(rdev); |
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343 | |||
344 | reg = ((prescale << RADEON_I2C_PRESCALE_SHIFT) | |
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1963 | serge | 345 | RADEON_I2C_DRIVE_EN | |
1430 | serge | 346 | RADEON_I2C_START | |
347 | RADEON_I2C_STOP | |
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348 | RADEON_I2C_GO); |
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349 | |||
350 | if (rdev->is_atom_bios) { |
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351 | tmp = RREG32(RADEON_BIOS_6_SCRATCH); |
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352 | WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); |
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353 | } |
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354 | |||
355 | if (rec->mm_i2c) { |
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356 | i2c_cntl_0 = RADEON_I2C_CNTL_0; |
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357 | i2c_cntl_1 = RADEON_I2C_CNTL_1; |
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358 | i2c_data = RADEON_I2C_DATA; |
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359 | } else { |
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360 | i2c_cntl_0 = RADEON_DVI_I2C_CNTL_0; |
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361 | i2c_cntl_1 = RADEON_DVI_I2C_CNTL_1; |
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362 | i2c_data = RADEON_DVI_I2C_DATA; |
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363 | |||
364 | switch (rdev->family) { |
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365 | case CHIP_R100: |
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366 | case CHIP_RV100: |
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367 | case CHIP_RS100: |
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368 | case CHIP_RV200: |
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369 | case CHIP_RS200: |
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370 | case CHIP_RS300: |
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371 | switch (rec->mask_clk_reg) { |
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372 | case RADEON_GPIO_DVI_DDC: |
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373 | /* no gpio select bit */ |
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374 | break; |
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375 | default: |
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376 | DRM_ERROR("gpio not supported with hw i2c\n"); |
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377 | ret = -EINVAL; |
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378 | goto done; |
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379 | } |
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380 | break; |
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381 | case CHIP_R200: |
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382 | /* only bit 4 on r200 */ |
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383 | switch (rec->mask_clk_reg) { |
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384 | case RADEON_GPIO_DVI_DDC: |
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385 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); |
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386 | break; |
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387 | case RADEON_GPIO_MONID: |
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388 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); |
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389 | break; |
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390 | default: |
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391 | DRM_ERROR("gpio not supported with hw i2c\n"); |
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392 | ret = -EINVAL; |
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393 | goto done; |
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394 | } |
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395 | break; |
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396 | case CHIP_RV250: |
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397 | case CHIP_RV280: |
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398 | /* bits 3 and 4 */ |
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399 | switch (rec->mask_clk_reg) { |
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400 | case RADEON_GPIO_DVI_DDC: |
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401 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); |
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402 | break; |
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403 | case RADEON_GPIO_VGA_DDC: |
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404 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); |
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405 | break; |
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406 | case RADEON_GPIO_CRT2_DDC: |
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407 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); |
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408 | break; |
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409 | default: |
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410 | DRM_ERROR("gpio not supported with hw i2c\n"); |
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411 | ret = -EINVAL; |
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412 | goto done; |
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413 | } |
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414 | break; |
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415 | case CHIP_R300: |
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416 | case CHIP_R350: |
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417 | /* only bit 4 on r300/r350 */ |
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418 | switch (rec->mask_clk_reg) { |
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419 | case RADEON_GPIO_VGA_DDC: |
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420 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); |
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421 | break; |
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422 | case RADEON_GPIO_DVI_DDC: |
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423 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); |
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424 | break; |
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425 | default: |
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426 | DRM_ERROR("gpio not supported with hw i2c\n"); |
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427 | ret = -EINVAL; |
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428 | goto done; |
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429 | } |
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430 | break; |
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431 | case CHIP_RV350: |
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432 | case CHIP_RV380: |
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433 | case CHIP_R420: |
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434 | case CHIP_R423: |
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435 | case CHIP_RV410: |
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436 | case CHIP_RS400: |
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437 | case CHIP_RS480: |
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438 | /* bits 3 and 4 */ |
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439 | switch (rec->mask_clk_reg) { |
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440 | case RADEON_GPIO_VGA_DDC: |
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441 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC1); |
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442 | break; |
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443 | case RADEON_GPIO_DVI_DDC: |
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444 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC2); |
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445 | break; |
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446 | case RADEON_GPIO_MONID: |
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447 | reg |= R200_DVI_I2C_PIN_SEL(R200_SEL_DDC3); |
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448 | break; |
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449 | default: |
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450 | DRM_ERROR("gpio not supported with hw i2c\n"); |
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451 | ret = -EINVAL; |
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452 | goto done; |
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453 | } |
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454 | break; |
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455 | default: |
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456 | DRM_ERROR("unsupported asic\n"); |
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457 | ret = -EINVAL; |
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458 | goto done; |
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459 | break; |
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460 | } |
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461 | } |
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462 | |||
463 | /* check for bus probe */ |
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464 | p = &msgs[0]; |
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465 | if ((num == 1) && (p->len == 0)) { |
||
466 | WREG32(i2c_cntl_0, (RADEON_I2C_DONE | |
||
467 | RADEON_I2C_NACK | |
||
468 | RADEON_I2C_HALT | |
||
469 | RADEON_I2C_SOFT_RST)); |
||
470 | WREG32(i2c_data, (p->addr << 1) & 0xff); |
||
471 | WREG32(i2c_data, 0); |
||
472 | WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | |
||
473 | (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | |
||
474 | RADEON_I2C_EN | |
||
475 | (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); |
||
476 | WREG32(i2c_cntl_0, reg); |
||
477 | for (k = 0; k < 32; k++) { |
||
478 | udelay(10); |
||
479 | tmp = RREG32(i2c_cntl_0); |
||
480 | if (tmp & RADEON_I2C_GO) |
||
481 | continue; |
||
482 | tmp = RREG32(i2c_cntl_0); |
||
483 | if (tmp & RADEON_I2C_DONE) |
||
484 | break; |
||
485 | else { |
||
486 | DRM_DEBUG("i2c write error 0x%08x\n", tmp); |
||
487 | WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); |
||
488 | ret = -EIO; |
||
489 | goto done; |
||
490 | } |
||
491 | } |
||
492 | goto done; |
||
493 | } |
||
494 | |||
495 | for (i = 0; i < num; i++) { |
||
496 | p = &msgs[i]; |
||
497 | for (j = 0; j < p->len; j++) { |
||
498 | if (p->flags & I2C_M_RD) { |
||
499 | WREG32(i2c_cntl_0, (RADEON_I2C_DONE | |
||
500 | RADEON_I2C_NACK | |
||
501 | RADEON_I2C_HALT | |
||
502 | RADEON_I2C_SOFT_RST)); |
||
503 | WREG32(i2c_data, ((p->addr << 1) & 0xff) | 0x1); |
||
504 | WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | |
||
505 | (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | |
||
506 | RADEON_I2C_EN | |
||
507 | (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); |
||
508 | WREG32(i2c_cntl_0, reg | RADEON_I2C_RECEIVE); |
||
509 | for (k = 0; k < 32; k++) { |
||
510 | udelay(10); |
||
511 | tmp = RREG32(i2c_cntl_0); |
||
512 | if (tmp & RADEON_I2C_GO) |
||
513 | continue; |
||
514 | tmp = RREG32(i2c_cntl_0); |
||
515 | if (tmp & RADEON_I2C_DONE) |
||
516 | break; |
||
517 | else { |
||
518 | DRM_DEBUG("i2c read error 0x%08x\n", tmp); |
||
519 | WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); |
||
520 | ret = -EIO; |
||
521 | goto done; |
||
522 | } |
||
523 | } |
||
524 | p->buf[j] = RREG32(i2c_data) & 0xff; |
||
525 | } else { |
||
526 | WREG32(i2c_cntl_0, (RADEON_I2C_DONE | |
||
527 | RADEON_I2C_NACK | |
||
528 | RADEON_I2C_HALT | |
||
529 | RADEON_I2C_SOFT_RST)); |
||
530 | WREG32(i2c_data, (p->addr << 1) & 0xff); |
||
531 | WREG32(i2c_data, p->buf[j]); |
||
532 | WREG32(i2c_cntl_1, ((1 << RADEON_I2C_DATA_COUNT_SHIFT) | |
||
533 | (1 << RADEON_I2C_ADDR_COUNT_SHIFT) | |
||
534 | RADEON_I2C_EN | |
||
535 | (48 << RADEON_I2C_TIME_LIMIT_SHIFT))); |
||
536 | WREG32(i2c_cntl_0, reg); |
||
537 | for (k = 0; k < 32; k++) { |
||
538 | udelay(10); |
||
539 | tmp = RREG32(i2c_cntl_0); |
||
540 | if (tmp & RADEON_I2C_GO) |
||
541 | continue; |
||
542 | tmp = RREG32(i2c_cntl_0); |
||
543 | if (tmp & RADEON_I2C_DONE) |
||
544 | break; |
||
545 | else { |
||
546 | DRM_DEBUG("i2c write error 0x%08x\n", tmp); |
||
547 | WREG32(i2c_cntl_0, tmp | RADEON_I2C_ABORT); |
||
548 | ret = -EIO; |
||
549 | goto done; |
||
550 | } |
||
551 | } |
||
552 | } |
||
553 | } |
||
554 | } |
||
555 | |||
556 | done: |
||
557 | WREG32(i2c_cntl_0, 0); |
||
558 | WREG32(i2c_cntl_1, 0); |
||
559 | WREG32(i2c_cntl_0, (RADEON_I2C_DONE | |
||
560 | RADEON_I2C_NACK | |
||
561 | RADEON_I2C_HALT | |
||
562 | RADEON_I2C_SOFT_RST)); |
||
563 | |||
564 | if (rdev->is_atom_bios) { |
||
565 | tmp = RREG32(RADEON_BIOS_6_SCRATCH); |
||
566 | tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; |
||
567 | WREG32(RADEON_BIOS_6_SCRATCH, tmp); |
||
568 | } |
||
569 | |||
570 | mutex_unlock(&rdev->pm.mutex); |
||
571 | mutex_unlock(&rdev->dc_hw_i2c_mutex); |
||
572 | |||
573 | return ret; |
||
574 | } |
||
575 | |||
576 | /* hw i2c engine for r5xx hardware |
||
577 | * hw can buffer up to 15 bytes |
||
578 | */ |
||
579 | static int r500_hw_i2c_xfer(struct i2c_adapter *i2c_adap, |
||
580 | struct i2c_msg *msgs, int num) |
||
581 | { |
||
582 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); |
||
583 | struct radeon_device *rdev = i2c->dev->dev_private; |
||
584 | struct radeon_i2c_bus_rec *rec = &i2c->rec; |
||
585 | struct i2c_msg *p; |
||
586 | int i, j, remaining, current_count, buffer_offset, ret = num; |
||
587 | u32 prescale; |
||
588 | u32 tmp, reg; |
||
589 | u32 saved1, saved2; |
||
590 | |||
591 | mutex_lock(&rdev->dc_hw_i2c_mutex); |
||
592 | /* take the pm lock since we need a constant sclk */ |
||
593 | mutex_lock(&rdev->pm.mutex); |
||
594 | |||
595 | prescale = radeon_get_i2c_prescale(rdev); |
||
596 | |||
597 | /* clear gpio mask bits */ |
||
598 | tmp = RREG32(rec->mask_clk_reg); |
||
599 | tmp &= ~rec->mask_clk_mask; |
||
600 | WREG32(rec->mask_clk_reg, tmp); |
||
601 | tmp = RREG32(rec->mask_clk_reg); |
||
602 | |||
603 | tmp = RREG32(rec->mask_data_reg); |
||
604 | tmp &= ~rec->mask_data_mask; |
||
605 | WREG32(rec->mask_data_reg, tmp); |
||
606 | tmp = RREG32(rec->mask_data_reg); |
||
607 | |||
608 | /* clear pin values */ |
||
609 | tmp = RREG32(rec->a_clk_reg); |
||
610 | tmp &= ~rec->a_clk_mask; |
||
611 | WREG32(rec->a_clk_reg, tmp); |
||
612 | tmp = RREG32(rec->a_clk_reg); |
||
613 | |||
614 | tmp = RREG32(rec->a_data_reg); |
||
615 | tmp &= ~rec->a_data_mask; |
||
616 | WREG32(rec->a_data_reg, tmp); |
||
617 | tmp = RREG32(rec->a_data_reg); |
||
618 | |||
619 | /* set the pins to input */ |
||
620 | tmp = RREG32(rec->en_clk_reg); |
||
621 | tmp &= ~rec->en_clk_mask; |
||
622 | WREG32(rec->en_clk_reg, tmp); |
||
623 | tmp = RREG32(rec->en_clk_reg); |
||
624 | |||
625 | tmp = RREG32(rec->en_data_reg); |
||
626 | tmp &= ~rec->en_data_mask; |
||
627 | WREG32(rec->en_data_reg, tmp); |
||
628 | tmp = RREG32(rec->en_data_reg); |
||
629 | |||
630 | /* */ |
||
631 | tmp = RREG32(RADEON_BIOS_6_SCRATCH); |
||
632 | WREG32(RADEON_BIOS_6_SCRATCH, tmp | ATOM_S6_HW_I2C_BUSY_STATE); |
||
633 | saved1 = RREG32(AVIVO_DC_I2C_CONTROL1); |
||
634 | saved2 = RREG32(0x494); |
||
635 | WREG32(0x494, saved2 | 0x1); |
||
636 | |||
637 | WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_WANTS_TO_USE_I2C); |
||
638 | for (i = 0; i < 50; i++) { |
||
639 | udelay(1); |
||
640 | if (RREG32(AVIVO_DC_I2C_ARBITRATION) & AVIVO_DC_I2C_SW_CAN_USE_I2C) |
||
641 | break; |
||
642 | } |
||
643 | if (i == 50) { |
||
644 | DRM_ERROR("failed to get i2c bus\n"); |
||
645 | ret = -EBUSY; |
||
646 | goto done; |
||
647 | } |
||
648 | |||
649 | reg = AVIVO_DC_I2C_START | AVIVO_DC_I2C_STOP | AVIVO_DC_I2C_EN; |
||
650 | switch (rec->mask_clk_reg) { |
||
651 | case AVIVO_DC_GPIO_DDC1_MASK: |
||
652 | reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC1); |
||
653 | break; |
||
654 | case AVIVO_DC_GPIO_DDC2_MASK: |
||
655 | reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC2); |
||
656 | break; |
||
657 | case AVIVO_DC_GPIO_DDC3_MASK: |
||
658 | reg |= AVIVO_DC_I2C_PIN_SELECT(AVIVO_SEL_DDC3); |
||
659 | break; |
||
660 | default: |
||
661 | DRM_ERROR("gpio not supported with hw i2c\n"); |
||
662 | ret = -EINVAL; |
||
663 | goto done; |
||
664 | } |
||
665 | |||
666 | /* check for bus probe */ |
||
667 | p = &msgs[0]; |
||
668 | if ((num == 1) && (p->len == 0)) { |
||
669 | WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | |
||
670 | AVIVO_DC_I2C_NACK | |
||
671 | AVIVO_DC_I2C_HALT)); |
||
672 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); |
||
673 | udelay(1); |
||
674 | WREG32(AVIVO_DC_I2C_RESET, 0); |
||
675 | |||
676 | WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); |
||
677 | WREG32(AVIVO_DC_I2C_DATA, 0); |
||
678 | |||
679 | WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); |
||
680 | WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | |
||
681 | AVIVO_DC_I2C_DATA_COUNT(1) | |
||
682 | (prescale << 16))); |
||
683 | WREG32(AVIVO_DC_I2C_CONTROL1, reg); |
||
684 | WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); |
||
685 | for (j = 0; j < 200; j++) { |
||
686 | udelay(50); |
||
687 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); |
||
688 | if (tmp & AVIVO_DC_I2C_GO) |
||
689 | continue; |
||
690 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); |
||
691 | if (tmp & AVIVO_DC_I2C_DONE) |
||
692 | break; |
||
693 | else { |
||
694 | DRM_DEBUG("i2c write error 0x%08x\n", tmp); |
||
695 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); |
||
696 | ret = -EIO; |
||
697 | goto done; |
||
698 | } |
||
699 | } |
||
700 | goto done; |
||
701 | } |
||
702 | |||
703 | for (i = 0; i < num; i++) { |
||
704 | p = &msgs[i]; |
||
705 | remaining = p->len; |
||
706 | buffer_offset = 0; |
||
707 | if (p->flags & I2C_M_RD) { |
||
708 | while (remaining) { |
||
709 | if (remaining > 15) |
||
710 | current_count = 15; |
||
711 | else |
||
712 | current_count = remaining; |
||
713 | WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | |
||
714 | AVIVO_DC_I2C_NACK | |
||
715 | AVIVO_DC_I2C_HALT)); |
||
716 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); |
||
717 | udelay(1); |
||
718 | WREG32(AVIVO_DC_I2C_RESET, 0); |
||
719 | |||
720 | WREG32(AVIVO_DC_I2C_DATA, ((p->addr << 1) & 0xff) | 0x1); |
||
721 | WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); |
||
722 | WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | |
||
723 | AVIVO_DC_I2C_DATA_COUNT(current_count) | |
||
724 | (prescale << 16))); |
||
725 | WREG32(AVIVO_DC_I2C_CONTROL1, reg | AVIVO_DC_I2C_RECEIVE); |
||
726 | WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); |
||
727 | for (j = 0; j < 200; j++) { |
||
728 | udelay(50); |
||
729 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); |
||
730 | if (tmp & AVIVO_DC_I2C_GO) |
||
731 | continue; |
||
732 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); |
||
733 | if (tmp & AVIVO_DC_I2C_DONE) |
||
734 | break; |
||
735 | else { |
||
736 | DRM_DEBUG("i2c read error 0x%08x\n", tmp); |
||
737 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); |
||
738 | ret = -EIO; |
||
739 | goto done; |
||
740 | } |
||
741 | } |
||
742 | for (j = 0; j < current_count; j++) |
||
743 | p->buf[buffer_offset + j] = RREG32(AVIVO_DC_I2C_DATA) & 0xff; |
||
744 | remaining -= current_count; |
||
745 | buffer_offset += current_count; |
||
746 | } |
||
747 | } else { |
||
748 | while (remaining) { |
||
749 | if (remaining > 15) |
||
750 | current_count = 15; |
||
751 | else |
||
752 | current_count = remaining; |
||
753 | WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | |
||
754 | AVIVO_DC_I2C_NACK | |
||
755 | AVIVO_DC_I2C_HALT)); |
||
756 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); |
||
757 | udelay(1); |
||
758 | WREG32(AVIVO_DC_I2C_RESET, 0); |
||
759 | |||
760 | WREG32(AVIVO_DC_I2C_DATA, (p->addr << 1) & 0xff); |
||
761 | for (j = 0; j < current_count; j++) |
||
762 | WREG32(AVIVO_DC_I2C_DATA, p->buf[buffer_offset + j]); |
||
763 | |||
764 | WREG32(AVIVO_DC_I2C_CONTROL3, AVIVO_DC_I2C_TIME_LIMIT(48)); |
||
765 | WREG32(AVIVO_DC_I2C_CONTROL2, (AVIVO_DC_I2C_ADDR_COUNT(1) | |
||
766 | AVIVO_DC_I2C_DATA_COUNT(current_count) | |
||
767 | (prescale << 16))); |
||
768 | WREG32(AVIVO_DC_I2C_CONTROL1, reg); |
||
769 | WREG32(AVIVO_DC_I2C_STATUS1, AVIVO_DC_I2C_GO); |
||
770 | for (j = 0; j < 200; j++) { |
||
771 | udelay(50); |
||
772 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); |
||
773 | if (tmp & AVIVO_DC_I2C_GO) |
||
774 | continue; |
||
775 | tmp = RREG32(AVIVO_DC_I2C_STATUS1); |
||
776 | if (tmp & AVIVO_DC_I2C_DONE) |
||
777 | break; |
||
778 | else { |
||
779 | DRM_DEBUG("i2c write error 0x%08x\n", tmp); |
||
780 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_ABORT); |
||
781 | ret = -EIO; |
||
782 | goto done; |
||
783 | } |
||
784 | } |
||
785 | remaining -= current_count; |
||
786 | buffer_offset += current_count; |
||
787 | } |
||
788 | } |
||
789 | } |
||
790 | |||
791 | done: |
||
792 | WREG32(AVIVO_DC_I2C_STATUS1, (AVIVO_DC_I2C_DONE | |
||
793 | AVIVO_DC_I2C_NACK | |
||
794 | AVIVO_DC_I2C_HALT)); |
||
795 | WREG32(AVIVO_DC_I2C_RESET, AVIVO_DC_I2C_SOFT_RESET); |
||
796 | udelay(1); |
||
797 | WREG32(AVIVO_DC_I2C_RESET, 0); |
||
798 | |||
799 | WREG32(AVIVO_DC_I2C_ARBITRATION, AVIVO_DC_I2C_SW_DONE_USING_I2C); |
||
800 | WREG32(AVIVO_DC_I2C_CONTROL1, saved1); |
||
801 | WREG32(0x494, saved2); |
||
802 | tmp = RREG32(RADEON_BIOS_6_SCRATCH); |
||
803 | tmp &= ~ATOM_S6_HW_I2C_BUSY_STATE; |
||
804 | WREG32(RADEON_BIOS_6_SCRATCH, tmp); |
||
805 | |||
806 | mutex_unlock(&rdev->pm.mutex); |
||
807 | mutex_unlock(&rdev->dc_hw_i2c_mutex); |
||
808 | |||
809 | return ret; |
||
810 | } |
||
811 | |||
1963 | serge | 812 | static int radeon_hw_i2c_xfer(struct i2c_adapter *i2c_adap, |
1430 | serge | 813 | struct i2c_msg *msgs, int num) |
814 | { |
||
815 | struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap); |
||
816 | struct radeon_device *rdev = i2c->dev->dev_private; |
||
817 | struct radeon_i2c_bus_rec *rec = &i2c->rec; |
||
1963 | serge | 818 | int ret = 0; |
1430 | serge | 819 | |
5078 | serge | 820 | mutex_lock(&i2c->mutex); |
821 | |||
1430 | serge | 822 | switch (rdev->family) { |
823 | case CHIP_R100: |
||
824 | case CHIP_RV100: |
||
825 | case CHIP_RS100: |
||
826 | case CHIP_RV200: |
||
827 | case CHIP_RS200: |
||
828 | case CHIP_R200: |
||
829 | case CHIP_RV250: |
||
830 | case CHIP_RS300: |
||
831 | case CHIP_RV280: |
||
832 | case CHIP_R300: |
||
833 | case CHIP_R350: |
||
834 | case CHIP_RV350: |
||
835 | case CHIP_RV380: |
||
836 | case CHIP_R420: |
||
837 | case CHIP_R423: |
||
838 | case CHIP_RV410: |
||
839 | case CHIP_RS400: |
||
840 | case CHIP_RS480: |
||
6104 | serge | 841 | ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); |
1430 | serge | 842 | break; |
843 | case CHIP_RS600: |
||
844 | case CHIP_RS690: |
||
845 | case CHIP_RS740: |
||
846 | /* XXX fill in hw i2c implementation */ |
||
847 | break; |
||
848 | case CHIP_RV515: |
||
849 | case CHIP_R520: |
||
850 | case CHIP_RV530: |
||
851 | case CHIP_RV560: |
||
852 | case CHIP_RV570: |
||
853 | case CHIP_R580: |
||
6104 | serge | 854 | if (rec->mm_i2c) |
855 | ret = r100_hw_i2c_xfer(i2c_adap, msgs, num); |
||
856 | else |
||
857 | ret = r500_hw_i2c_xfer(i2c_adap, msgs, num); |
||
1430 | serge | 858 | break; |
859 | case CHIP_R600: |
||
860 | case CHIP_RV610: |
||
861 | case CHIP_RV630: |
||
862 | case CHIP_RV670: |
||
863 | /* XXX fill in hw i2c implementation */ |
||
864 | break; |
||
865 | case CHIP_RV620: |
||
866 | case CHIP_RV635: |
||
867 | case CHIP_RS780: |
||
868 | case CHIP_RS880: |
||
869 | case CHIP_RV770: |
||
870 | case CHIP_RV730: |
||
871 | case CHIP_RV710: |
||
872 | case CHIP_RV740: |
||
873 | /* XXX fill in hw i2c implementation */ |
||
874 | break; |
||
875 | case CHIP_CEDAR: |
||
876 | case CHIP_REDWOOD: |
||
877 | case CHIP_JUNIPER: |
||
878 | case CHIP_CYPRESS: |
||
879 | case CHIP_HEMLOCK: |
||
880 | /* XXX fill in hw i2c implementation */ |
||
881 | break; |
||
882 | default: |
||
883 | DRM_ERROR("i2c: unhandled radeon chip\n"); |
||
884 | ret = -EIO; |
||
885 | break; |
||
886 | } |
||
887 | |||
5078 | serge | 888 | mutex_unlock(&i2c->mutex); |
889 | |||
1430 | serge | 890 | return ret; |
891 | } |
||
892 | |||
1963 | serge | 893 | static u32 radeon_hw_i2c_func(struct i2c_adapter *adap) |
1430 | serge | 894 | { |
895 | return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; |
||
896 | } |
||
897 | |||
898 | static const struct i2c_algorithm radeon_i2c_algo = { |
||
1963 | serge | 899 | .master_xfer = radeon_hw_i2c_xfer, |
900 | .functionality = radeon_hw_i2c_func, |
||
1430 | serge | 901 | }; |
902 | |||
2997 | Serge | 903 | static const struct i2c_algorithm radeon_atom_i2c_algo = { |
904 | .master_xfer = radeon_atom_hw_i2c_xfer, |
||
905 | .functionality = radeon_atom_hw_i2c_func, |
||
906 | }; |
||
907 | |||
1123 | serge | 908 | struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev, |
6104 | serge | 909 | struct radeon_i2c_bus_rec *rec, |
910 | const char *name) |
||
1123 | serge | 911 | { |
1963 | serge | 912 | struct radeon_device *rdev = dev->dev_private; |
1123 | serge | 913 | struct radeon_i2c_chan *i2c; |
914 | int ret; |
||
915 | |||
2997 | Serge | 916 | /* don't add the mm_i2c bus unless hw_i2c is enabled */ |
917 | if (rec->mm_i2c && (radeon_hw_i2c == 0)) |
||
918 | return NULL; |
||
919 | |||
1123 | serge | 920 | i2c = kzalloc(sizeof(struct radeon_i2c_chan), GFP_KERNEL); |
921 | if (i2c == NULL) |
||
922 | return NULL; |
||
923 | |||
1963 | serge | 924 | i2c->rec = *rec; |
2997 | Serge | 925 | i2c->adapter.owner = THIS_MODULE; |
926 | i2c->adapter.class = I2C_CLASS_DDC; |
||
6104 | serge | 927 | i2c->adapter.dev.parent = &dev->pdev->dev; |
1963 | serge | 928 | i2c->dev = dev; |
929 | i2c_set_adapdata(&i2c->adapter, i2c); |
||
5078 | serge | 930 | mutex_init(&i2c->mutex); |
1963 | serge | 931 | if (rec->mm_i2c || |
932 | (rec->hw_capable && |
||
933 | radeon_hw_i2c && |
||
934 | ((rdev->family <= CHIP_RS480) || |
||
935 | ((rdev->family >= CHIP_RV515) && (rdev->family <= CHIP_R580))))) { |
||
936 | /* set the radeon hw i2c adapter */ |
||
937 | snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), |
||
938 | "Radeon i2c hw bus %s", name); |
||
939 | i2c->adapter.algo = &radeon_i2c_algo; |
||
3192 | Serge | 940 | ret = i2c_add_adapter(&i2c->adapter); |
941 | if (ret) { |
||
942 | DRM_ERROR("Failed to register hw i2c %s\n", name); |
||
943 | goto out_free; |
||
944 | } |
||
2997 | Serge | 945 | } else if (rec->hw_capable && |
946 | radeon_hw_i2c && |
||
947 | ASIC_IS_DCE3(rdev)) { |
||
948 | /* hw i2c using atom */ |
||
949 | snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), |
||
950 | "Radeon i2c hw bus %s", name); |
||
951 | i2c->adapter.algo = &radeon_atom_i2c_algo; |
||
3192 | Serge | 952 | ret = i2c_add_adapter(&i2c->adapter); |
953 | if (ret) { |
||
954 | DRM_ERROR("Failed to register hw i2c %s\n", name); |
||
955 | goto out_free; |
||
956 | } |
||
1963 | serge | 957 | } else { |
958 | /* set the radeon bit adapter */ |
||
959 | snprintf(i2c->adapter.name, sizeof(i2c->adapter.name), |
||
960 | "Radeon i2c bit bus %s", name); |
||
5078 | serge | 961 | i2c->adapter.algo_data = &i2c->bit; |
962 | i2c->bit.pre_xfer = pre_xfer; |
||
963 | i2c->bit.post_xfer = post_xfer; |
||
964 | i2c->bit.setsda = set_data; |
||
965 | i2c->bit.setscl = set_clock; |
||
966 | i2c->bit.getsda = get_data; |
||
967 | i2c->bit.getscl = get_clock; |
||
968 | i2c->bit.udelay = 10; |
||
969 | i2c->bit.timeout = usecs_to_jiffies(2200); /* from VESA */ |
||
970 | i2c->bit.data = i2c; |
||
1963 | serge | 971 | ret = i2c_bit_add_bus(&i2c->adapter); |
6104 | serge | 972 | if (ret) { |
1963 | serge | 973 | DRM_ERROR("Failed to register bit i2c %s\n", name); |
6104 | serge | 974 | goto out_free; |
975 | } |
||
1123 | serge | 976 | } |
977 | |||
978 | return i2c; |
||
979 | out_free: |
||
980 | kfree(i2c); |
||
981 | return NULL; |
||
982 | |||
983 | } |
||
984 | |||
985 | void radeon_i2c_destroy(struct radeon_i2c_chan *i2c) |
||
986 | { |
||
987 | if (!i2c) |
||
988 | return; |
||
3192 | Serge | 989 | i2c_del_adapter(&i2c->adapter); |
5078 | serge | 990 | if (i2c->has_aux) |
991 | drm_dp_aux_unregister(&i2c->aux); |
||
1430 | serge | 992 | kfree(i2c); |
993 | } |
||
1123 | serge | 994 | |
1963 | serge | 995 | /* Add the default buses */ |
996 | void radeon_i2c_init(struct radeon_device *rdev) |
||
1430 | serge | 997 | { |
5078 | serge | 998 | if (radeon_hw_i2c) |
999 | DRM_INFO("hw_i2c forced on, you may experience display detection problems!\n"); |
||
1000 | |||
1963 | serge | 1001 | if (rdev->is_atom_bios) |
1002 | radeon_atombios_i2c_init(rdev); |
||
1003 | else |
||
1004 | radeon_combios_i2c_init(rdev); |
||
1005 | } |
||
1430 | serge | 1006 | |
1963 | serge | 1007 | /* remove all the buses */ |
1008 | void radeon_i2c_fini(struct radeon_device *rdev) |
||
1009 | { |
||
1010 | int i; |
||
1011 | |||
1012 | for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { |
||
1013 | if (rdev->i2c_bus[i]) { |
||
1014 | radeon_i2c_destroy(rdev->i2c_bus[i]); |
||
1015 | rdev->i2c_bus[i] = NULL; |
||
1016 | } |
||
1017 | } |
||
1123 | serge | 1018 | } |
1019 | |||
1963 | serge | 1020 | /* Add additional buses */ |
1021 | void radeon_i2c_add(struct radeon_device *rdev, |
||
1022 | struct radeon_i2c_bus_rec *rec, |
||
1023 | const char *name) |
||
1024 | { |
||
1025 | struct drm_device *dev = rdev->ddev; |
||
1026 | int i; |
||
1027 | |||
1028 | for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { |
||
1029 | if (!rdev->i2c_bus[i]) { |
||
1030 | rdev->i2c_bus[i] = radeon_i2c_create(dev, rec, name); |
||
1031 | return; |
||
1032 | } |
||
1033 | } |
||
1034 | } |
||
1035 | |||
1036 | /* looks up bus based on id */ |
||
1037 | struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev, |
||
1038 | struct radeon_i2c_bus_rec *i2c_bus) |
||
1039 | { |
||
1040 | int i; |
||
1041 | |||
1042 | for (i = 0; i < RADEON_MAX_I2C_BUS; i++) { |
||
1043 | if (rdev->i2c_bus[i] && |
||
1044 | (rdev->i2c_bus[i]->rec.i2c_id == i2c_bus->i2c_id)) { |
||
1045 | return rdev->i2c_bus[i]; |
||
1046 | } |
||
1047 | } |
||
1048 | return NULL; |
||
1049 | } |
||
1050 | |||
1430 | serge | 1051 | void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus, |
6104 | serge | 1052 | u8 slave_addr, |
1053 | u8 addr, |
||
1054 | u8 *val) |
||
1321 | serge | 1055 | { |
1056 | u8 out_buf[2]; |
||
1057 | u8 in_buf[2]; |
||
1058 | struct i2c_msg msgs[] = { |
||
1059 | { |
||
1060 | .addr = slave_addr, |
||
1061 | .flags = 0, |
||
1062 | .len = 1, |
||
1063 | .buf = out_buf, |
||
1064 | }, |
||
1065 | { |
||
1066 | .addr = slave_addr, |
||
1067 | .flags = I2C_M_RD, |
||
1068 | .len = 1, |
||
1069 | .buf = in_buf, |
||
1070 | } |
||
1071 | }; |
||
1072 | |||
1073 | out_buf[0] = addr; |
||
1074 | out_buf[1] = 0; |
||
1075 | |||
1076 | if (i2c_transfer(&i2c_bus->adapter, msgs, 2) == 2) { |
||
1077 | *val = in_buf[0]; |
||
1078 | DRM_DEBUG("val = 0x%02x\n", *val); |
||
1079 | } else { |
||
1963 | serge | 1080 | DRM_DEBUG("i2c 0x%02x 0x%02x read failed\n", |
1321 | serge | 1081 | addr, *val); |
1082 | } |
||
1083 | } |
||
1084 | |||
1430 | serge | 1085 | void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c_bus, |
6104 | serge | 1086 | u8 slave_addr, |
1087 | u8 addr, |
||
1088 | u8 val) |
||
1321 | serge | 1089 | { |
1090 | uint8_t out_buf[2]; |
||
1091 | struct i2c_msg msg = { |
||
1092 | .addr = slave_addr, |
||
1093 | .flags = 0, |
||
1094 | .len = 2, |
||
1095 | .buf = out_buf, |
||
1096 | }; |
||
1097 | |||
1098 | out_buf[0] = addr; |
||
1099 | out_buf[1] = val; |
||
1100 | |||
1101 | if (i2c_transfer(&i2c_bus->adapter, &msg, 1) != 1) |
||
1963 | serge | 1102 | DRM_DEBUG("i2c 0x%02x 0x%02x write failed\n", |
1321 | serge | 1103 | addr, val); |
1104 | } |
||
1105 | |||
1963 | serge | 1106 | /* ddc router switching */ |
1107 | void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector) |
||
1108 | { |
||
1109 | u8 val; |
||
1110 | |||
6104 | serge | 1111 | if (!radeon_connector->router.ddc_valid) |
1963 | serge | 1112 | return; |
1113 | |||
1114 | if (!radeon_connector->router_bus) |
||
1115 | return; |
||
1116 | |||
1117 | radeon_i2c_get_byte(radeon_connector->router_bus, |
||
1118 | radeon_connector->router.i2c_addr, |
||
1119 | 0x3, &val); |
||
1120 | val &= ~radeon_connector->router.ddc_mux_control_pin; |
||
1121 | radeon_i2c_put_byte(radeon_connector->router_bus, |
||
1122 | radeon_connector->router.i2c_addr, |
||
1123 | 0x3, val); |
||
1124 | radeon_i2c_get_byte(radeon_connector->router_bus, |
||
1125 | radeon_connector->router.i2c_addr, |
||
1126 | 0x1, &val); |
||
1127 | val &= ~radeon_connector->router.ddc_mux_control_pin; |
||
1128 | val |= radeon_connector->router.ddc_mux_state; |
||
1129 | radeon_i2c_put_byte(radeon_connector->router_bus, |
||
1130 | radeon_connector->router.i2c_addr, |
||
1131 | 0x1, val); |
||
1132 | } |
||
1133 | |||
1134 | /* clock/data router switching */ |
||
1135 | void radeon_router_select_cd_port(struct radeon_connector *radeon_connector) |
||
1136 | { |
||
1137 | u8 val; |
||
1138 | |||
1139 | if (!radeon_connector->router.cd_valid) |
||
1140 | return; |
||
1141 | |||
1142 | if (!radeon_connector->router_bus) |
||
1143 | return; |
||
1144 | |||
1145 | radeon_i2c_get_byte(radeon_connector->router_bus, |
||
1146 | radeon_connector->router.i2c_addr, |
||
1147 | 0x3, &val); |
||
1148 | val &= ~radeon_connector->router.cd_mux_control_pin; |
||
1149 | radeon_i2c_put_byte(radeon_connector->router_bus, |
||
1150 | radeon_connector->router.i2c_addr, |
||
1151 | 0x3, val); |
||
1152 | radeon_i2c_get_byte(radeon_connector->router_bus, |
||
1153 | radeon_connector->router.i2c_addr, |
||
1154 | 0x1, &val); |
||
1155 | val &= ~radeon_connector->router.cd_mux_control_pin; |
||
1156 | val |= radeon_connector->router.cd_mux_state; |
||
1157 | radeon_i2c_put_byte(radeon_connector->router_bus, |
||
1158 | radeon_connector->router.i2c_addr, |
||
1159 | 0x1, val); |
||
1160 | }>>>=>=>>><>>><>>>><>><>>>><>><>>>><>><>><>><>>><>><>><>><>>>>><>><>><>><>><>><>><>><>><>>>><>> |
||
1161 |