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1120 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | //#include "drmP.h" |
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29 | #include "radeon_drm.h" |
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30 | #include "radeon.h" |
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31 | #include "radeon_reg.h" |
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32 | |||
33 | #if 0 |
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34 | /* |
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35 | * Common GART table functions. |
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36 | */ |
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37 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev) |
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38 | { |
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39 | void *ptr; |
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40 | |||
41 | ptr = pci_alloc_consistent(rdev->pdev, rdev->gart.table_size, |
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42 | &rdev->gart.table_addr); |
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43 | if (ptr == NULL) { |
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44 | return -ENOMEM; |
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45 | } |
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46 | #ifdef CONFIG_X86 |
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47 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 || |
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48 | rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { |
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49 | set_memory_uc((unsigned long)ptr, |
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50 | rdev->gart.table_size >> PAGE_SHIFT); |
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51 | } |
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52 | #endif |
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53 | rdev->gart.table.ram.ptr = ptr; |
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54 | memset((void *)rdev->gart.table.ram.ptr, 0, rdev->gart.table_size); |
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55 | return 0; |
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56 | } |
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57 | |||
58 | void radeon_gart_table_ram_free(struct radeon_device *rdev) |
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59 | { |
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60 | if (rdev->gart.table.ram.ptr == NULL) { |
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61 | return; |
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62 | } |
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63 | #ifdef CONFIG_X86 |
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64 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480 || |
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65 | rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { |
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66 | set_memory_wb((unsigned long)rdev->gart.table.ram.ptr, |
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67 | rdev->gart.table_size >> PAGE_SHIFT); |
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68 | } |
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69 | #endif |
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70 | pci_free_consistent(rdev->pdev, rdev->gart.table_size, |
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71 | (void *)rdev->gart.table.ram.ptr, |
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72 | rdev->gart.table_addr); |
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73 | rdev->gart.table.ram.ptr = NULL; |
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74 | rdev->gart.table_addr = 0; |
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75 | } |
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76 | #endif |
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77 | |||
78 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev) |
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79 | { |
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80 | uint32_t gpu_addr; |
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81 | int r; |
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82 | |||
83 | |||
84 | if (rdev->gart.table.vram.robj == NULL) { |
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85 | r = radeon_object_create(rdev, NULL, |
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86 | rdev->gart.table_size, |
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87 | true, |
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88 | RADEON_GEM_DOMAIN_VRAM, |
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89 | false, &rdev->gart.table.vram.robj); |
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90 | if (r) { |
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91 | return r; |
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92 | } |
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93 | } |
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94 | r = radeon_object_pin(rdev->gart.table.vram.robj, |
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95 | RADEON_GEM_DOMAIN_VRAM, &gpu_addr); |
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96 | if (r) { |
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97 | // radeon_object_unref(&rdev->gart.table.vram.robj); |
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98 | return r; |
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99 | } |
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100 | r = radeon_object_kmap(rdev->gart.table.vram.robj, |
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101 | (void **)&rdev->gart.table.vram.ptr); |
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102 | if (r) { |
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103 | // radeon_object_unpin(rdev->gart.table.vram.robj); |
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104 | // radeon_object_unref(&rdev->gart.table.vram.robj); |
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105 | DRM_ERROR("radeon: failed to map gart vram table.\n"); |
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106 | return r; |
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107 | } |
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108 | |||
109 | rdev->gart.table_addr = gpu_addr; |
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110 | |||
111 | dbgprintf("alloc gart vram: gpu_base %x lin_addr %x\n", |
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112 | rdev->gart.table_addr, rdev->gart.table.vram.ptr); |
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113 | |||
114 | // gpu_addr = 0x800000; |
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115 | |||
116 | // u32_t pci_addr = rdev->mc.aper_base + gpu_addr; |
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117 | |||
118 | // rdev->gart.table.vram.ptr = (void*)MapIoMem(pci_addr, rdev->gart.table_size, PG_SW); |
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119 | |||
120 | |||
121 | // dbgprintf("alloc gart vram:\n gpu_base %x pci_base %x lin_addr %x", |
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122 | // gpu_addr, pci_addr, rdev->gart.table.vram.ptr); |
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123 | |||
124 | return 0; |
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125 | } |
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126 | |||
127 | void radeon_gart_table_vram_free(struct radeon_device *rdev) |
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128 | { |
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129 | if (rdev->gart.table.vram.robj == NULL) { |
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130 | return; |
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131 | } |
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132 | // radeon_object_kunmap(rdev->gart.table.vram.robj); |
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133 | // radeon_object_unpin(rdev->gart.table.vram.robj); |
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134 | // radeon_object_unref(&rdev->gart.table.vram.robj); |
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135 | } |
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136 | |||
137 | |||
138 | |||
139 | |||
140 | /* |
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141 | * Common gart functions. |
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142 | */ |
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143 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
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144 | int pages) |
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145 | { |
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146 | unsigned t; |
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147 | unsigned p; |
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148 | int i, j; |
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149 | |||
150 | if (!rdev->gart.ready) { |
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151 | // WARN(1, "trying to unbind memory to unitialized GART !\n"); |
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152 | return; |
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153 | } |
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154 | t = offset / 4096; |
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155 | p = t / (PAGE_SIZE / 4096); |
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156 | for (i = 0; i < pages; i++, p++) { |
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157 | if (rdev->gart.pages[p]) { |
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158 | // pci_unmap_page(rdev->pdev, rdev->gart.pages_addr[p], |
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159 | // PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
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160 | rdev->gart.pages[p] = NULL; |
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161 | rdev->gart.pages_addr[p] = 0; |
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162 | for (j = 0; j < (PAGE_SIZE / 4096); j++, t++) { |
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163 | radeon_gart_set_page(rdev, t, 0); |
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164 | } |
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165 | } |
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166 | } |
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167 | mb(); |
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168 | radeon_gart_tlb_flush(rdev); |
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169 | } |
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170 | |||
171 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
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172 | int pages, u32_t *pagelist) |
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173 | { |
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174 | unsigned t; |
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175 | unsigned p; |
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176 | uint64_t page_base; |
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177 | int i, j; |
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178 | |||
179 | dbgprintf("%s ",__FUNCTION__); |
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180 | dbgprintf("offset %x pages %x list %x\n", |
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181 | offset, pages, pagelist); |
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182 | |||
183 | if (!rdev->gart.ready) { |
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184 | DRM_ERROR("trying to bind memory to unitialized GART !\n"); |
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185 | return -EINVAL; |
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186 | } |
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187 | t = offset / 4096; |
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188 | p = t / (PAGE_SIZE / 4096); |
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189 | |||
190 | for (i = 0; i < pages; i++, p++) { |
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191 | /* we need to support large memory configurations */ |
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192 | /* assume that unbind have already been call on the range */ |
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193 | |||
194 | rdev->gart.pages_addr[p] = pagelist[i] & ~4095; |
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195 | |||
196 | //if (pci_dma_mapping_error(rdev->pdev, rdev->gart.pages_addr[p])) { |
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197 | // /* FIXME: failed to map page (return -ENOMEM?) */ |
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198 | // radeon_gart_unbind(rdev, offset, pages); |
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199 | // return -ENOMEM; |
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200 | //} |
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201 | rdev->gart.pages[p] = pagelist[i]; |
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202 | page_base = (uint32_t)rdev->gart.pages_addr[p]; |
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203 | for (j = 0; j < (PAGE_SIZE / 4096); j++, t++) { |
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204 | radeon_gart_set_page(rdev, t, page_base); |
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205 | page_base += 4096; |
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206 | } |
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207 | } |
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208 | mb(); |
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209 | radeon_gart_tlb_flush(rdev); |
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210 | |||
211 | dbgprintf("done %s\n",__FUNCTION__); |
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212 | |||
213 | return 0; |
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214 | } |
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215 | |||
216 | int radeon_gart_init(struct radeon_device *rdev) |
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217 | { |
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218 | |||
219 | dbgprintf("%s\n",__FUNCTION__); |
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220 | |||
221 | if (rdev->gart.pages) { |
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222 | return 0; |
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223 | } |
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224 | /* We need PAGE_SIZE >= 4096 */ |
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225 | if (PAGE_SIZE < 4096) { |
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226 | DRM_ERROR("Page size is smaller than GPU page size!\n"); |
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227 | return -EINVAL; |
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228 | } |
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229 | /* Compute table size */ |
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230 | rdev->gart.num_cpu_pages = rdev->mc.gtt_size / PAGE_SIZE; |
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231 | rdev->gart.num_gpu_pages = rdev->mc.gtt_size / 4096; |
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232 | DRM_INFO("GART: num cpu pages %u, num gpu pages %u\n", |
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233 | rdev->gart.num_cpu_pages, rdev->gart.num_gpu_pages); |
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234 | /* Allocate pages table */ |
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235 | rdev->gart.pages = kzalloc(sizeof(void *) * rdev->gart.num_cpu_pages, |
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236 | GFP_KERNEL); |
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237 | if (rdev->gart.pages == NULL) { |
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238 | // radeon_gart_fini(rdev); |
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239 | return -ENOMEM; |
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240 | } |
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241 | rdev->gart.pages_addr = kzalloc(sizeof(u32_t) * |
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242 | rdev->gart.num_cpu_pages, GFP_KERNEL); |
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243 | if (rdev->gart.pages_addr == NULL) { |
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244 | // radeon_gart_fini(rdev); |
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245 | return -ENOMEM; |
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246 | } |
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247 | return 0; |
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248 | } |
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249 | |||
250 | void radeon_gart_fini(struct radeon_device *rdev) |
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251 | { |
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252 | if (rdev->gart.pages && rdev->gart.pages_addr && rdev->gart.ready) { |
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253 | /* unbind pages */ |
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254 | radeon_gart_unbind(rdev, 0, rdev->gart.num_cpu_pages); |
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255 | } |
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256 | rdev->gart.ready = false; |
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257 | kfree(rdev->gart.pages); |
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258 | kfree(rdev->gart.pages_addr); |
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259 | rdev->gart.pages = NULL; |
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260 | rdev->gart.pages_addr = NULL; |
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261 | }>>>>> |