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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | //#include |
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2997 | Serge | 29 | #include |
1179 | serge | 30 | #include |
31 | #include |
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1221 | serge | 32 | #include |
1117 | serge | 33 | #include "radeon_reg.h" |
34 | #include "radeon.h" |
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35 | #include "atom.h" |
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3120 | serge | 36 | |
37 | #include "bitmap.h" |
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1428 | serge | 38 | #include "display.h" |
1117 | serge | 39 | |
3120 | serge | 40 | |
1221 | serge | 41 | #include |
42 | |||
1117 | serge | 43 | |
2160 | serge | 44 | int radeon_no_wb = 1; |
1430 | serge | 45 | int radeon_modeset = -1; |
46 | int radeon_dynclks = -1; |
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47 | int radeon_r4xx_atom = 0; |
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48 | int radeon_agpmode = 0; |
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49 | int radeon_vram_limit = 0; |
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50 | int radeon_gart_size = 512; /* default gart size */ |
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51 | int radeon_benchmarking = 0; |
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52 | int radeon_testing = 0; |
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53 | int radeon_connector_table = 0; |
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54 | int radeon_tv = 1; |
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55 | int radeon_new_pll = -1; |
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56 | int radeon_dynpm = -1; |
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57 | int radeon_audio = 1; |
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1963 | serge | 58 | int radeon_hw_i2c = 0; |
59 | int radeon_pcie_gen2 = 0; |
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60 | int radeon_disp_priority = 0; |
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2997 | Serge | 61 | int radeon_lockup_timeout = 10000; |
1117 | serge | 62 | |
2997 | Serge | 63 | |
2160 | serge | 64 | int irq_override = 0; |
1430 | serge | 65 | |
1963 | serge | 66 | |
1428 | serge | 67 | extern display_t *rdisplay; |
3120 | serge | 68 | struct drm_device *main_drm_device; |
1246 | serge | 69 | |
3120 | serge | 70 | |
1404 | serge | 71 | void parse_cmdline(char *cmdline, videomode_t *mode, char *log, int *kms); |
72 | int init_display(struct radeon_device *rdev, videomode_t *mode); |
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73 | int init_display_kms(struct radeon_device *rdev, videomode_t *mode); |
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1117 | serge | 74 | |
2997 | Serge | 75 | int get_modes(videomode_t *mode, u32_t *count); |
1404 | serge | 76 | int set_user_mode(videomode_t *mode); |
1428 | serge | 77 | int r100_2D_test(struct radeon_device *rdev); |
1239 | serge | 78 | |
1404 | serge | 79 | |
1233 | serge | 80 | /* Legacy VGA regions */ |
81 | #define VGA_RSRC_NONE 0x00 |
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82 | #define VGA_RSRC_LEGACY_IO 0x01 |
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83 | #define VGA_RSRC_LEGACY_MEM 0x02 |
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84 | #define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM) |
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85 | /* Non-legacy access */ |
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86 | #define VGA_RSRC_NORMAL_IO 0x04 |
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87 | #define VGA_RSRC_NORMAL_MEM 0x08 |
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88 | |||
89 | |||
1963 | serge | 90 | static const char radeon_family_name[][16] = { |
91 | "R100", |
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92 | "RV100", |
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93 | "RS100", |
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94 | "RV200", |
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95 | "RS200", |
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96 | "R200", |
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97 | "RV250", |
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98 | "RS300", |
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99 | "RV280", |
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100 | "R300", |
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101 | "R350", |
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102 | "RV350", |
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103 | "RV380", |
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104 | "R420", |
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105 | "R423", |
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106 | "RV410", |
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107 | "RS400", |
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108 | "RS480", |
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109 | "RS600", |
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110 | "RS690", |
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111 | "RS740", |
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112 | "RV515", |
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113 | "R520", |
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114 | "RV530", |
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115 | "RV560", |
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116 | "RV570", |
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117 | "R580", |
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118 | "R600", |
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119 | "RV610", |
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120 | "RV630", |
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121 | "RV670", |
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122 | "RV620", |
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123 | "RV635", |
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124 | "RS780", |
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125 | "RS880", |
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126 | "RV770", |
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127 | "RV730", |
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128 | "RV710", |
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129 | "RV740", |
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130 | "CEDAR", |
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131 | "REDWOOD", |
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132 | "JUNIPER", |
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133 | "CYPRESS", |
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134 | "HEMLOCK", |
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135 | "PALM", |
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1986 | serge | 136 | "SUMO", |
137 | "SUMO2", |
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1963 | serge | 138 | "BARTS", |
139 | "TURKS", |
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140 | "CAICOS", |
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141 | "CAYMAN", |
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2997 | Serge | 142 | "ARUBA", |
143 | "TAHITI", |
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144 | "PITCAIRN", |
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145 | "VERDE", |
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1963 | serge | 146 | "LAST", |
147 | }; |
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1233 | serge | 148 | |
2997 | Serge | 149 | /** |
150 | * radeon_surface_init - Clear GPU surface registers. |
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151 | * |
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152 | * @rdev: radeon_device pointer |
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153 | * |
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154 | * Clear GPU surface registers (r1xx-r5xx). |
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1117 | serge | 155 | */ |
1179 | serge | 156 | void radeon_surface_init(struct radeon_device *rdev) |
1117 | serge | 157 | { |
158 | /* FIXME: check this out */ |
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159 | if (rdev->family < CHIP_R600) { |
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160 | int i; |
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161 | |||
1321 | serge | 162 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
1404 | serge | 163 | radeon_clear_surface_reg(rdev, i); |
1117 | serge | 164 | } |
1179 | serge | 165 | /* enable surfaces */ |
166 | WREG32(RADEON_SURFACE_CNTL, 0); |
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1117 | serge | 167 | } |
168 | } |
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169 | |||
170 | /* |
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171 | * GPU scratch registers helpers function. |
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172 | */ |
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2997 | Serge | 173 | /** |
174 | * radeon_scratch_init - Init scratch register driver information. |
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175 | * |
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176 | * @rdev: radeon_device pointer |
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177 | * |
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178 | * Init CP scratch register driver information (r1xx-r5xx) |
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179 | */ |
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1179 | serge | 180 | void radeon_scratch_init(struct radeon_device *rdev) |
1117 | serge | 181 | { |
182 | int i; |
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183 | |||
184 | /* FIXME: check this out */ |
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185 | if (rdev->family < CHIP_R300) { |
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186 | rdev->scratch.num_reg = 5; |
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187 | } else { |
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188 | rdev->scratch.num_reg = 7; |
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189 | } |
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1963 | serge | 190 | rdev->scratch.reg_base = RADEON_SCRATCH_REG0; |
1117 | serge | 191 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
192 | rdev->scratch.free[i] = true; |
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1963 | serge | 193 | rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); |
1117 | serge | 194 | } |
195 | } |
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196 | |||
2997 | Serge | 197 | /** |
198 | * radeon_scratch_get - Allocate a scratch register |
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199 | * |
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200 | * @rdev: radeon_device pointer |
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201 | * @reg: scratch register mmio offset |
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202 | * |
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203 | * Allocate a CP scratch register for use by the driver (all asics). |
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204 | * Returns 0 on success or -EINVAL on failure. |
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205 | */ |
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1117 | serge | 206 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) |
207 | { |
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208 | int i; |
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209 | |||
210 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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211 | if (rdev->scratch.free[i]) { |
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212 | rdev->scratch.free[i] = false; |
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213 | *reg = rdev->scratch.reg[i]; |
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214 | return 0; |
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215 | } |
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216 | } |
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217 | return -EINVAL; |
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218 | } |
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219 | |||
2997 | Serge | 220 | /** |
221 | * radeon_scratch_free - Free a scratch register |
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222 | * |
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223 | * @rdev: radeon_device pointer |
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224 | * @reg: scratch register mmio offset |
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225 | * |
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226 | * Free a CP scratch register allocated for use by the driver (all asics) |
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227 | */ |
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1117 | serge | 228 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) |
229 | { |
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230 | int i; |
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231 | |||
232 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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233 | if (rdev->scratch.reg[i] == reg) { |
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234 | rdev->scratch.free[i] = true; |
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235 | return; |
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236 | } |
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237 | } |
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238 | } |
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239 | |||
2997 | Serge | 240 | /* |
241 | * radeon_wb_*() |
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242 | * Writeback is the the method by which the the GPU updates special pages |
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243 | * in memory with the status of certain GPU events (fences, ring pointers, |
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244 | * etc.). |
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245 | */ |
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246 | |||
247 | /** |
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248 | * radeon_wb_disable - Disable Writeback |
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249 | * |
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250 | * @rdev: radeon_device pointer |
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251 | * |
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252 | * Disables Writeback (all asics). Used for suspend. |
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253 | */ |
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2004 | serge | 254 | void radeon_wb_disable(struct radeon_device *rdev) |
255 | { |
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256 | int r; |
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257 | |||
258 | if (rdev->wb.wb_obj) { |
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259 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
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260 | if (unlikely(r != 0)) |
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261 | return; |
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262 | radeon_bo_kunmap(rdev->wb.wb_obj); |
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263 | radeon_bo_unpin(rdev->wb.wb_obj); |
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264 | radeon_bo_unreserve(rdev->wb.wb_obj); |
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265 | } |
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266 | rdev->wb.enabled = false; |
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267 | } |
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268 | |||
2997 | Serge | 269 | /** |
270 | * radeon_wb_fini - Disable Writeback and free memory |
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271 | * |
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272 | * @rdev: radeon_device pointer |
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273 | * |
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274 | * Disables Writeback and frees the Writeback memory (all asics). |
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275 | * Used at driver shutdown. |
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276 | */ |
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2004 | serge | 277 | void radeon_wb_fini(struct radeon_device *rdev) |
278 | { |
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279 | radeon_wb_disable(rdev); |
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280 | if (rdev->wb.wb_obj) { |
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281 | radeon_bo_unref(&rdev->wb.wb_obj); |
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282 | rdev->wb.wb = NULL; |
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283 | rdev->wb.wb_obj = NULL; |
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284 | } |
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285 | } |
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286 | |||
2997 | Serge | 287 | /** |
288 | * radeon_wb_init- Init Writeback driver info and allocate memory |
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289 | * |
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290 | * @rdev: radeon_device pointer |
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291 | * |
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292 | * Disables Writeback and frees the Writeback memory (all asics). |
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293 | * Used at driver startup. |
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294 | * Returns 0 on success or an -error on failure. |
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295 | */ |
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2004 | serge | 296 | int radeon_wb_init(struct radeon_device *rdev) |
297 | { |
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298 | int r; |
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299 | |||
300 | if (rdev->wb.wb_obj == NULL) { |
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301 | r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, |
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2997 | Serge | 302 | RADEON_GEM_DOMAIN_GTT, NULL, &rdev->wb.wb_obj); |
2004 | serge | 303 | if (r) { |
304 | dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); |
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305 | return r; |
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306 | } |
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307 | } |
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308 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
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309 | if (unlikely(r != 0)) { |
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310 | radeon_wb_fini(rdev); |
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311 | return r; |
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312 | } |
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313 | r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, |
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314 | &rdev->wb.gpu_addr); |
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315 | if (r) { |
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316 | radeon_bo_unreserve(rdev->wb.wb_obj); |
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317 | dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); |
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318 | radeon_wb_fini(rdev); |
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319 | return r; |
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320 | } |
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321 | r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); |
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322 | radeon_bo_unreserve(rdev->wb.wb_obj); |
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323 | if (r) { |
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324 | dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); |
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325 | radeon_wb_fini(rdev); |
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326 | return r; |
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327 | } |
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328 | |||
329 | /* clear wb memory */ |
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330 | memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE); |
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331 | /* disable event_write fences */ |
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332 | rdev->wb.use_event = false; |
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333 | /* disabled via module param */ |
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2997 | Serge | 334 | if (radeon_no_wb == 1) { |
2004 | serge | 335 | rdev->wb.enabled = false; |
2997 | Serge | 336 | } else { |
337 | if (rdev->flags & RADEON_IS_AGP) { |
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2004 | serge | 338 | /* often unreliable on AGP */ |
2997 | Serge | 339 | rdev->wb.enabled = false; |
340 | } else if (rdev->family < CHIP_R300) { |
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341 | /* often unreliable on pre-r300 */ |
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342 | rdev->wb.enabled = false; |
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343 | } else { |
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2004 | serge | 344 | rdev->wb.enabled = true; |
345 | /* event_write fences are only available on r600+ */ |
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2997 | Serge | 346 | if (rdev->family >= CHIP_R600) { |
2004 | serge | 347 | rdev->wb.use_event = true; |
348 | } |
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2997 | Serge | 349 | } |
350 | } |
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351 | /* always use writeback/events on NI, APUs */ |
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352 | if (rdev->family >= CHIP_PALM) { |
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2004 | serge | 353 | rdev->wb.enabled = true; |
354 | rdev->wb.use_event = true; |
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355 | } |
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356 | |||
357 | dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); |
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358 | |||
359 | return 0; |
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360 | } |
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361 | |||
1430 | serge | 362 | /** |
363 | * radeon_vram_location - try to find VRAM location |
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364 | * @rdev: radeon device structure holding all necessary informations |
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365 | * @mc: memory controller structure holding memory informations |
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366 | * @base: base address at which to put VRAM |
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367 | * |
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368 | * Function will place try to place VRAM at base address provided |
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369 | * as parameter (which is so far either PCI aperture address or |
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370 | * for IGP TOM base address). |
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371 | * |
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372 | * If there is not enough space to fit the unvisible VRAM in the 32bits |
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373 | * address space then we limit the VRAM size to the aperture. |
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374 | * |
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375 | * If we are using AGP and if the AGP aperture doesn't allow us to have |
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376 | * room for all the VRAM than we restrict the VRAM to the PCI aperture |
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377 | * size and print a warning. |
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378 | * |
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379 | * This function will never fails, worst case are limiting VRAM. |
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380 | * |
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381 | * Note: GTT start, end, size should be initialized before calling this |
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382 | * function on AGP platform. |
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383 | * |
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1963 | serge | 384 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, |
1430 | serge | 385 | * this shouldn't be a problem as we are using the PCI aperture as a reference. |
386 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but |
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387 | * not IGP. |
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388 | * |
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389 | * Note: we use mc_vram_size as on some board we need to program the mc to |
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390 | * cover the whole aperture even if VRAM size is inferior to aperture size |
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391 | * Novell bug 204882 + along with lots of ubuntu ones |
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392 | * |
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393 | * Note: when limiting vram it's safe to overwritte real_vram_size because |
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394 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie |
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395 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu |
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396 | * ones) |
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397 | * |
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398 | * Note: IGP TOM addr should be the same as the aperture addr, we don't |
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399 | * explicitly check for that thought. |
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400 | * |
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401 | * FIXME: when reducing VRAM size align new size on power of 2. |
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1117 | serge | 402 | */ |
1430 | serge | 403 | void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) |
1117 | serge | 404 | { |
2997 | Serge | 405 | uint64_t limit = (uint64_t)radeon_vram_limit << 20; |
406 | |||
1430 | serge | 407 | mc->vram_start = base; |
408 | if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) { |
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409 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
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410 | mc->real_vram_size = mc->aper_size; |
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411 | mc->mc_vram_size = mc->aper_size; |
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412 | } |
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413 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
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1963 | serge | 414 | if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { |
1430 | serge | 415 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
416 | mc->real_vram_size = mc->aper_size; |
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417 | mc->mc_vram_size = mc->aper_size; |
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418 | } |
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419 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
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2997 | Serge | 420 | if (limit && limit < mc->real_vram_size) |
421 | mc->real_vram_size = limit; |
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1963 | serge | 422 | dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", |
1430 | serge | 423 | mc->mc_vram_size >> 20, mc->vram_start, |
424 | mc->vram_end, mc->real_vram_size >> 20); |
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425 | } |
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1117 | serge | 426 | |
1430 | serge | 427 | /** |
428 | * radeon_gtt_location - try to find GTT location |
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429 | * @rdev: radeon device structure holding all necessary informations |
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430 | * @mc: memory controller structure holding memory informations |
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431 | * |
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432 | * Function will place try to place GTT before or after VRAM. |
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433 | * |
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434 | * If GTT size is bigger than space left then we ajust GTT size. |
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435 | * Thus function will never fails. |
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436 | * |
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437 | * FIXME: when reducing GTT size align new size on power of 2. |
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438 | */ |
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439 | void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
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440 | { |
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441 | u64 size_af, size_bf; |
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442 | |||
1963 | serge | 443 | size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; |
444 | size_bf = mc->vram_start & ~mc->gtt_base_align; |
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1430 | serge | 445 | if (size_bf > size_af) { |
446 | if (mc->gtt_size > size_bf) { |
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447 | dev_warn(rdev->dev, "limiting GTT\n"); |
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448 | mc->gtt_size = size_bf; |
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1117 | serge | 449 | } |
1963 | serge | 450 | mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; |
1430 | serge | 451 | } else { |
452 | if (mc->gtt_size > size_af) { |
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453 | dev_warn(rdev->dev, "limiting GTT\n"); |
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454 | mc->gtt_size = size_af; |
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1117 | serge | 455 | } |
1963 | serge | 456 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; |
1117 | serge | 457 | } |
1430 | serge | 458 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; |
1963 | serge | 459 | dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", |
1430 | serge | 460 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); |
1117 | serge | 461 | } |
462 | |||
463 | /* |
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464 | * GPU helpers function. |
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465 | */ |
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2997 | Serge | 466 | /** |
467 | * radeon_card_posted - check if the hw has already been initialized |
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468 | * |
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469 | * @rdev: radeon_device pointer |
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470 | * |
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471 | * Check if the asic has been initialized (all asics). |
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472 | * Used at driver startup. |
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473 | * Returns true if initialized or false if not. |
||
474 | */ |
||
1179 | serge | 475 | bool radeon_card_posted(struct radeon_device *rdev) |
1117 | serge | 476 | { |
477 | uint32_t reg; |
||
478 | |||
479 | /* first check CRTCs */ |
||
1963 | serge | 480 | if (ASIC_IS_DCE41(rdev)) { |
1430 | serge | 481 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
1963 | serge | 482 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); |
483 | if (reg & EVERGREEN_CRTC_MASTER_EN) |
||
484 | return true; |
||
485 | } else if (ASIC_IS_DCE4(rdev)) { |
||
486 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
||
1430 | serge | 487 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | |
488 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | |
||
489 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | |
||
490 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | |
||
491 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); |
||
492 | if (reg & EVERGREEN_CRTC_MASTER_EN) |
||
493 | return true; |
||
494 | } else if (ASIC_IS_AVIVO(rdev)) { |
||
1117 | serge | 495 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
496 | RREG32(AVIVO_D2CRTC_CONTROL); |
||
497 | if (reg & AVIVO_CRTC_EN) { |
||
498 | return true; |
||
499 | } |
||
500 | } else { |
||
501 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | |
||
502 | RREG32(RADEON_CRTC2_GEN_CNTL); |
||
503 | if (reg & RADEON_CRTC_EN) { |
||
504 | return true; |
||
505 | } |
||
506 | } |
||
507 | |||
508 | /* then check MEM_SIZE, in case the crtcs are off */ |
||
509 | if (rdev->family >= CHIP_R600) |
||
510 | reg = RREG32(R600_CONFIG_MEMSIZE); |
||
511 | else |
||
512 | reg = RREG32(RADEON_CONFIG_MEMSIZE); |
||
513 | |||
514 | if (reg) |
||
515 | return true; |
||
516 | |||
517 | return false; |
||
518 | |||
519 | } |
||
520 | |||
2997 | Serge | 521 | /** |
522 | * radeon_update_bandwidth_info - update display bandwidth params |
||
523 | * |
||
524 | * @rdev: radeon_device pointer |
||
525 | * |
||
526 | * Used when sclk/mclk are switched or display modes are set. |
||
527 | * params are used to calculate display watermarks (all asics) |
||
528 | */ |
||
1963 | serge | 529 | void radeon_update_bandwidth_info(struct radeon_device *rdev) |
530 | { |
||
531 | fixed20_12 a; |
||
532 | u32 sclk = rdev->pm.current_sclk; |
||
533 | u32 mclk = rdev->pm.current_mclk; |
||
534 | |||
535 | /* sclk/mclk in Mhz */ |
||
536 | a.full = dfixed_const(100); |
||
537 | rdev->pm.sclk.full = dfixed_const(sclk); |
||
538 | rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); |
||
539 | rdev->pm.mclk.full = dfixed_const(mclk); |
||
540 | rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); |
||
541 | |||
542 | if (rdev->flags & RADEON_IS_IGP) { |
||
543 | a.full = dfixed_const(16); |
||
544 | /* core_bandwidth = sclk(Mhz) * 16 */ |
||
545 | rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); |
||
546 | } |
||
547 | } |
||
548 | |||
2997 | Serge | 549 | /** |
550 | * radeon_boot_test_post_card - check and possibly initialize the hw |
||
551 | * |
||
552 | * @rdev: radeon_device pointer |
||
553 | * |
||
554 | * Check if the asic is initialized and if not, attempt to initialize |
||
555 | * it (all asics). |
||
556 | * Returns true if initialized or false if not. |
||
557 | */ |
||
1321 | serge | 558 | bool radeon_boot_test_post_card(struct radeon_device *rdev) |
559 | { |
||
560 | if (radeon_card_posted(rdev)) |
||
561 | return true; |
||
562 | |||
563 | if (rdev->bios) { |
||
564 | DRM_INFO("GPU not posted. posting now...\n"); |
||
565 | if (rdev->is_atom_bios) |
||
566 | atom_asic_init(rdev->mode_info.atom_context); |
||
567 | else |
||
568 | radeon_combios_asic_init(rdev->ddev); |
||
569 | return true; |
||
570 | } else { |
||
571 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
||
572 | return false; |
||
573 | } |
||
574 | } |
||
575 | |||
2997 | Serge | 576 | /** |
577 | * radeon_dummy_page_init - init dummy page used by the driver |
||
578 | * |
||
579 | * @rdev: radeon_device pointer |
||
580 | * |
||
581 | * Allocate the dummy page used by the driver (all asics). |
||
582 | * This dummy page is used by the driver as a filler for gart entries |
||
583 | * when pages are taken out of the GART |
||
584 | * Returns 0 on sucess, -ENOMEM on failure. |
||
585 | */ |
||
1233 | serge | 586 | int radeon_dummy_page_init(struct radeon_device *rdev) |
587 | { |
||
1430 | serge | 588 | if (rdev->dummy_page.page) |
589 | return 0; |
||
2997 | Serge | 590 | rdev->dummy_page.page = (void*)AllocPage(); |
1233 | serge | 591 | if (rdev->dummy_page.page == NULL) |
592 | return -ENOMEM; |
||
2997 | Serge | 593 | rdev->dummy_page.addr = MapIoMem((addr_t)rdev->dummy_page.page, 4096, 3); |
1233 | serge | 594 | if (!rdev->dummy_page.addr) { |
595 | // __free_page(rdev->dummy_page.page); |
||
596 | rdev->dummy_page.page = NULL; |
||
597 | return -ENOMEM; |
||
598 | } |
||
599 | return 0; |
||
600 | } |
||
1117 | serge | 601 | |
2997 | Serge | 602 | /** |
603 | * radeon_dummy_page_fini - free dummy page used by the driver |
||
604 | * |
||
605 | * @rdev: radeon_device pointer |
||
606 | * |
||
607 | * Frees the dummy page used by the driver (all asics). |
||
608 | */ |
||
1233 | serge | 609 | void radeon_dummy_page_fini(struct radeon_device *rdev) |
610 | { |
||
611 | if (rdev->dummy_page.page == NULL) |
||
612 | return; |
||
2997 | Serge | 613 | KernelFree((void*)rdev->dummy_page.addr); |
1233 | serge | 614 | rdev->dummy_page.page = NULL; |
615 | } |
||
616 | |||
617 | |||
1117 | serge | 618 | /* ATOM accessor methods */ |
2997 | Serge | 619 | /* |
620 | * ATOM is an interpreted byte code stored in tables in the vbios. The |
||
621 | * driver registers callbacks to access registers and the interpreter |
||
622 | * in the driver parses the tables and executes then to program specific |
||
623 | * actions (set display modes, asic init, etc.). See radeon_atombios.c, |
||
624 | * atombios.h, and atom.c |
||
625 | */ |
||
626 | |||
627 | /** |
||
628 | * cail_pll_read - read PLL register |
||
629 | * |
||
630 | * @info: atom card_info pointer |
||
631 | * @reg: PLL register offset |
||
632 | * |
||
633 | * Provides a PLL register accessor for the atom interpreter (r4xx+). |
||
634 | * Returns the value of the PLL register. |
||
635 | */ |
||
1117 | serge | 636 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) |
637 | { |
||
638 | struct radeon_device *rdev = info->dev->dev_private; |
||
639 | uint32_t r; |
||
640 | |||
641 | r = rdev->pll_rreg(rdev, reg); |
||
642 | return r; |
||
643 | } |
||
644 | |||
2997 | Serge | 645 | /** |
646 | * cail_pll_write - write PLL register |
||
647 | * |
||
648 | * @info: atom card_info pointer |
||
649 | * @reg: PLL register offset |
||
650 | * @val: value to write to the pll register |
||
651 | * |
||
652 | * Provides a PLL register accessor for the atom interpreter (r4xx+). |
||
653 | */ |
||
1117 | serge | 654 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) |
655 | { |
||
656 | struct radeon_device *rdev = info->dev->dev_private; |
||
657 | |||
658 | rdev->pll_wreg(rdev, reg, val); |
||
659 | } |
||
660 | |||
2997 | Serge | 661 | /** |
662 | * cail_mc_read - read MC (Memory Controller) register |
||
663 | * |
||
664 | * @info: atom card_info pointer |
||
665 | * @reg: MC register offset |
||
666 | * |
||
667 | * Provides an MC register accessor for the atom interpreter (r4xx+). |
||
668 | * Returns the value of the MC register. |
||
669 | */ |
||
1117 | serge | 670 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) |
671 | { |
||
672 | struct radeon_device *rdev = info->dev->dev_private; |
||
673 | uint32_t r; |
||
674 | |||
675 | r = rdev->mc_rreg(rdev, reg); |
||
676 | return r; |
||
677 | } |
||
678 | |||
2997 | Serge | 679 | /** |
680 | * cail_mc_write - write MC (Memory Controller) register |
||
681 | * |
||
682 | * @info: atom card_info pointer |
||
683 | * @reg: MC register offset |
||
684 | * @val: value to write to the pll register |
||
685 | * |
||
686 | * Provides a MC register accessor for the atom interpreter (r4xx+). |
||
687 | */ |
||
1117 | serge | 688 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) |
689 | { |
||
690 | struct radeon_device *rdev = info->dev->dev_private; |
||
691 | |||
692 | rdev->mc_wreg(rdev, reg, val); |
||
693 | } |
||
694 | |||
2997 | Serge | 695 | /** |
696 | * cail_reg_write - write MMIO register |
||
697 | * |
||
698 | * @info: atom card_info pointer |
||
699 | * @reg: MMIO register offset |
||
700 | * @val: value to write to the pll register |
||
701 | * |
||
702 | * Provides a MMIO register accessor for the atom interpreter (r4xx+). |
||
703 | */ |
||
1117 | serge | 704 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) |
705 | { |
||
706 | struct radeon_device *rdev = info->dev->dev_private; |
||
707 | |||
708 | WREG32(reg*4, val); |
||
709 | } |
||
710 | |||
2997 | Serge | 711 | /** |
712 | * cail_reg_read - read MMIO register |
||
713 | * |
||
714 | * @info: atom card_info pointer |
||
715 | * @reg: MMIO register offset |
||
716 | * |
||
717 | * Provides an MMIO register accessor for the atom interpreter (r4xx+). |
||
718 | * Returns the value of the MMIO register. |
||
719 | */ |
||
1117 | serge | 720 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) |
721 | { |
||
722 | struct radeon_device *rdev = info->dev->dev_private; |
||
723 | uint32_t r; |
||
724 | |||
725 | r = RREG32(reg*4); |
||
726 | return r; |
||
727 | } |
||
728 | |||
2997 | Serge | 729 | /** |
730 | * cail_ioreg_write - write IO register |
||
731 | * |
||
732 | * @info: atom card_info pointer |
||
733 | * @reg: IO register offset |
||
734 | * @val: value to write to the pll register |
||
735 | * |
||
736 | * Provides a IO register accessor for the atom interpreter (r4xx+). |
||
737 | */ |
||
1963 | serge | 738 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) |
739 | { |
||
740 | struct radeon_device *rdev = info->dev->dev_private; |
||
741 | |||
742 | WREG32_IO(reg*4, val); |
||
743 | } |
||
744 | |||
2997 | Serge | 745 | /** |
746 | * cail_ioreg_read - read IO register |
||
747 | * |
||
748 | * @info: atom card_info pointer |
||
749 | * @reg: IO register offset |
||
750 | * |
||
751 | * Provides an IO register accessor for the atom interpreter (r4xx+). |
||
752 | * Returns the value of the IO register. |
||
753 | */ |
||
1963 | serge | 754 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) |
755 | { |
||
756 | struct radeon_device *rdev = info->dev->dev_private; |
||
757 | uint32_t r; |
||
758 | |||
759 | r = RREG32_IO(reg*4); |
||
760 | return r; |
||
761 | } |
||
762 | |||
2997 | Serge | 763 | /** |
764 | * radeon_atombios_init - init the driver info and callbacks for atombios |
||
765 | * |
||
766 | * @rdev: radeon_device pointer |
||
767 | * |
||
768 | * Initializes the driver info and register access callbacks for the |
||
769 | * ATOM interpreter (r4xx+). |
||
770 | * Returns 0 on sucess, -ENOMEM on failure. |
||
771 | * Called at driver startup. |
||
772 | */ |
||
1117 | serge | 773 | int radeon_atombios_init(struct radeon_device *rdev) |
774 | { |
||
1268 | serge | 775 | struct card_info *atom_card_info = |
776 | kzalloc(sizeof(struct card_info), GFP_KERNEL); |
||
1117 | serge | 777 | |
1268 | serge | 778 | if (!atom_card_info) |
779 | return -ENOMEM; |
||
780 | |||
781 | rdev->mode_info.atom_card_info = atom_card_info; |
||
782 | atom_card_info->dev = rdev->ddev; |
||
783 | atom_card_info->reg_read = cail_reg_read; |
||
784 | atom_card_info->reg_write = cail_reg_write; |
||
1963 | serge | 785 | /* needed for iio ops */ |
786 | if (rdev->rio_mem) { |
||
787 | atom_card_info->ioreg_read = cail_ioreg_read; |
||
788 | atom_card_info->ioreg_write = cail_ioreg_write; |
||
789 | } else { |
||
790 | DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); |
||
791 | atom_card_info->ioreg_read = cail_reg_read; |
||
792 | atom_card_info->ioreg_write = cail_reg_write; |
||
793 | } |
||
1268 | serge | 794 | atom_card_info->mc_read = cail_mc_read; |
795 | atom_card_info->mc_write = cail_mc_write; |
||
796 | atom_card_info->pll_read = cail_pll_read; |
||
797 | atom_card_info->pll_write = cail_pll_write; |
||
798 | |||
799 | rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); |
||
1630 | serge | 800 | mutex_init(&rdev->mode_info.atom_context->mutex); |
1117 | serge | 801 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
1321 | serge | 802 | atom_allocate_fb_scratch(rdev->mode_info.atom_context); |
1117 | serge | 803 | return 0; |
804 | } |
||
805 | |||
2997 | Serge | 806 | /** |
807 | * radeon_atombios_fini - free the driver info and callbacks for atombios |
||
808 | * |
||
809 | * @rdev: radeon_device pointer |
||
810 | * |
||
811 | * Frees the driver info and register access callbacks for the ATOM |
||
812 | * interpreter (r4xx+). |
||
813 | * Called at driver shutdown. |
||
814 | */ |
||
1117 | serge | 815 | void radeon_atombios_fini(struct radeon_device *rdev) |
816 | { |
||
1321 | serge | 817 | if (rdev->mode_info.atom_context) { |
818 | kfree(rdev->mode_info.atom_context->scratch); |
||
1119 | serge | 819 | kfree(rdev->mode_info.atom_context); |
1321 | serge | 820 | } |
1268 | serge | 821 | kfree(rdev->mode_info.atom_card_info); |
1117 | serge | 822 | } |
823 | |||
2997 | Serge | 824 | /* COMBIOS */ |
825 | /* |
||
826 | * COMBIOS is the bios format prior to ATOM. It provides |
||
827 | * command tables similar to ATOM, but doesn't have a unified |
||
828 | * parser. See radeon_combios.c |
||
829 | */ |
||
830 | |||
831 | /** |
||
832 | * radeon_combios_init - init the driver info for combios |
||
833 | * |
||
834 | * @rdev: radeon_device pointer |
||
835 | * |
||
836 | * Initializes the driver info for combios (r1xx-r3xx). |
||
837 | * Returns 0 on sucess. |
||
838 | * Called at driver startup. |
||
839 | */ |
||
1117 | serge | 840 | int radeon_combios_init(struct radeon_device *rdev) |
841 | { |
||
1128 | serge | 842 | radeon_combios_initialize_bios_scratch_regs(rdev->ddev); |
1117 | serge | 843 | return 0; |
844 | } |
||
845 | |||
2997 | Serge | 846 | /** |
847 | * radeon_combios_fini - free the driver info for combios |
||
848 | * |
||
849 | * @rdev: radeon_device pointer |
||
850 | * |
||
851 | * Frees the driver info for combios (r1xx-r3xx). |
||
852 | * Called at driver shutdown. |
||
853 | */ |
||
1117 | serge | 854 | void radeon_combios_fini(struct radeon_device *rdev) |
855 | { |
||
856 | } |
||
857 | |||
2997 | Serge | 858 | /* if we get transitioned to only one device, take VGA back */ |
859 | /** |
||
860 | * radeon_vga_set_decode - enable/disable vga decode |
||
861 | * |
||
862 | * @cookie: radeon_device pointer |
||
863 | * @state: enable/disable vga decode |
||
864 | * |
||
865 | * Enable/disable vga decode (all asics). |
||
866 | * Returns VGA resource flags. |
||
867 | */ |
||
1233 | serge | 868 | static unsigned int radeon_vga_set_decode(void *cookie, bool state) |
869 | { |
||
870 | struct radeon_device *rdev = cookie; |
||
871 | radeon_vga_set_state(rdev, state); |
||
872 | if (state) |
||
873 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | |
||
874 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
||
875 | else |
||
876 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
||
877 | } |
||
1117 | serge | 878 | |
2997 | Serge | 879 | /** |
880 | * radeon_check_pot_argument - check that argument is a power of two |
||
881 | * |
||
882 | * @arg: value to check |
||
883 | * |
||
884 | * Validates that a certain argument is a power of two (all asics). |
||
885 | * Returns true if argument is valid. |
||
886 | */ |
||
887 | static bool radeon_check_pot_argument(int arg) |
||
1404 | serge | 888 | { |
2997 | Serge | 889 | return (arg & (arg - 1)) == 0; |
890 | } |
||
891 | |||
892 | /** |
||
893 | * radeon_check_arguments - validate module params |
||
894 | * |
||
895 | * @rdev: radeon_device pointer |
||
896 | * |
||
897 | * Validates certain module parameters and updates |
||
898 | * the associated values used by the driver (all asics). |
||
899 | */ |
||
900 | static void radeon_check_arguments(struct radeon_device *rdev) |
||
901 | { |
||
1404 | serge | 902 | /* vramlimit must be a power of two */ |
2997 | Serge | 903 | if (!radeon_check_pot_argument(radeon_vram_limit)) { |
1404 | serge | 904 | dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", |
905 | radeon_vram_limit); |
||
906 | radeon_vram_limit = 0; |
||
907 | } |
||
2997 | Serge | 908 | |
1404 | serge | 909 | /* gtt size must be power of two and greater or equal to 32M */ |
2997 | Serge | 910 | if (radeon_gart_size < 32) { |
1404 | serge | 911 | dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n", |
912 | radeon_gart_size); |
||
913 | radeon_gart_size = 512; |
||
2997 | Serge | 914 | |
915 | } else if (!radeon_check_pot_argument(radeon_gart_size)) { |
||
1404 | serge | 916 | dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", |
917 | radeon_gart_size); |
||
918 | radeon_gart_size = 512; |
||
919 | } |
||
2997 | Serge | 920 | rdev->mc.gtt_size = (uint64_t)radeon_gart_size << 20; |
921 | |||
1404 | serge | 922 | /* AGP mode can only be -1, 1, 2, 4, 8 */ |
923 | switch (radeon_agpmode) { |
||
924 | case -1: |
||
925 | case 0: |
||
926 | case 1: |
||
927 | case 2: |
||
928 | case 4: |
||
929 | case 8: |
||
930 | break; |
||
931 | default: |
||
932 | dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " |
||
933 | "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); |
||
934 | radeon_agpmode = 0; |
||
935 | break; |
||
936 | } |
||
937 | } |
||
938 | |||
1117 | serge | 939 | int radeon_device_init(struct radeon_device *rdev, |
940 | struct drm_device *ddev, |
||
941 | struct pci_dev *pdev, |
||
942 | uint32_t flags) |
||
943 | { |
||
1963 | serge | 944 | int r, i; |
1179 | serge | 945 | int dma_bits; |
1117 | serge | 946 | |
947 | rdev->shutdown = false; |
||
948 | rdev->ddev = ddev; |
||
949 | rdev->pdev = pdev; |
||
950 | rdev->flags = flags; |
||
951 | rdev->family = flags & RADEON_FAMILY_MASK; |
||
952 | rdev->is_atom_bios = false; |
||
953 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; |
||
954 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
||
1221 | serge | 955 | rdev->accel_working = false; |
2997 | Serge | 956 | /* set up ring ids */ |
957 | for (i = 0; i < RADEON_NUM_RINGS; i++) { |
||
958 | rdev->ring[i].idx = i; |
||
959 | } |
||
1963 | serge | 960 | |
2997 | Serge | 961 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X 0x%04X:0x%04X).\n", |
962 | radeon_family_name[rdev->family], pdev->vendor, pdev->device, |
||
963 | pdev->subsystem_vendor, pdev->subsystem_device); |
||
1963 | serge | 964 | |
1117 | serge | 965 | /* mutex initialization are all done here so we |
966 | * can recall function without having locking issues */ |
||
2997 | Serge | 967 | mutex_init(&rdev->ring_lock); |
1630 | serge | 968 | mutex_init(&rdev->dc_hw_i2c_mutex); |
2997 | Serge | 969 | atomic_set(&rdev->ih.lock, 0); |
1630 | serge | 970 | mutex_init(&rdev->gem.mutex); |
971 | mutex_init(&rdev->pm.mutex); |
||
2997 | Serge | 972 | mutex_init(&rdev->gpu_clock_mutex); |
973 | init_rwsem(&rdev->pm.mclk_lock); |
||
974 | init_rwsem(&rdev->exclusive_lock); |
||
975 | init_waitqueue_head(&rdev->irq.vblank_queue); |
||
976 | r = radeon_gem_init(rdev); |
||
977 | if (r) |
||
978 | return r; |
||
979 | /* initialize vm here */ |
||
980 | mutex_init(&rdev->vm_manager.lock); |
||
981 | /* Adjust VM size here. |
||
982 | * Currently set to 4GB ((1 << 20) 4k pages). |
||
983 | * Max GPUVM size for cayman and SI is 40 bits. |
||
984 | */ |
||
985 | rdev->vm_manager.max_pfn = 1 << 20; |
||
986 | INIT_LIST_HEAD(&rdev->vm_manager.lru_vm); |
||
1117 | serge | 987 | |
1179 | serge | 988 | /* Set asic functions */ |
989 | r = radeon_asic_init(rdev); |
||
1404 | serge | 990 | if (r) |
1179 | serge | 991 | return r; |
1404 | serge | 992 | radeon_check_arguments(rdev); |
1179 | serge | 993 | |
1963 | serge | 994 | /* all of the newer IGP chips have an internal gart |
995 | * However some rs4xx report as AGP, so remove that here. |
||
996 | */ |
||
997 | if ((rdev->family >= CHIP_RS400) && |
||
998 | (rdev->flags & RADEON_IS_IGP)) { |
||
999 | rdev->flags &= ~RADEON_IS_AGP; |
||
1000 | } |
||
1001 | |||
1321 | serge | 1002 | if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { |
1221 | serge | 1003 | radeon_agp_disable(rdev); |
1117 | serge | 1004 | } |
1005 | |||
1179 | serge | 1006 | /* set DMA mask + need_dma32 flags. |
1007 | * PCIE - can handle 40-bits. |
||
2997 | Serge | 1008 | * IGP - can handle 40-bits |
1179 | serge | 1009 | * AGP - generally dma32 is safest |
2997 | Serge | 1010 | * PCI - dma32 for legacy pci gart, 40 bits on newer asics |
1179 | serge | 1011 | */ |
1012 | rdev->need_dma32 = false; |
||
1013 | if (rdev->flags & RADEON_IS_AGP) |
||
1014 | rdev->need_dma32 = true; |
||
2997 | Serge | 1015 | if ((rdev->flags & RADEON_IS_PCI) && |
1016 | (rdev->family <= CHIP_RS740)) |
||
1179 | serge | 1017 | rdev->need_dma32 = true; |
1117 | serge | 1018 | |
1179 | serge | 1019 | dma_bits = rdev->need_dma32 ? 32 : 40; |
1020 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); |
||
1117 | serge | 1021 | if (r) { |
1986 | serge | 1022 | rdev->need_dma32 = true; |
2997 | Serge | 1023 | dma_bits = 32; |
1119 | serge | 1024 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
1025 | } |
||
1117 | serge | 1026 | |
1027 | /* Registers mapping */ |
||
1028 | /* TODO: block userspace mapping of io register */ |
||
1029 | rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); |
||
1030 | rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); |
||
2997 | Serge | 1031 | rdev->rmmio = ioremap(rdev->rmmio_base, rdev->rmmio_size); |
1117 | serge | 1032 | if (rdev->rmmio == NULL) { |
1033 | return -ENOMEM; |
||
1034 | } |
||
1035 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); |
||
1036 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); |
||
1037 | |||
2997 | Serge | 1038 | /* io port mapping */ |
1039 | for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) { |
||
1040 | if (pci_resource_flags(rdev->pdev, i) & IORESOURCE_IO) { |
||
1041 | rdev->rio_mem_size = pci_resource_len(rdev->pdev, i); |
||
1042 | rdev->rio_mem = pci_iomap(rdev->pdev, i, rdev->rio_mem_size); |
||
1043 | break; |
||
1044 | } |
||
1045 | } |
||
1046 | if (rdev->rio_mem == NULL) |
||
1047 | DRM_ERROR("Unable to find PCI I/O BAR\n"); |
||
1048 | |||
1049 | |||
1179 | serge | 1050 | r = radeon_init(rdev); |
1221 | serge | 1051 | if (r) |
1963 | serge | 1052 | return r; |
1117 | serge | 1053 | |
1221 | serge | 1054 | if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { |
1055 | /* Acceleration not working on AGP card try again |
||
1056 | * with fallback to PCI or PCIE GART |
||
1057 | */ |
||
1963 | serge | 1058 | radeon_asic_reset(rdev); |
1221 | serge | 1059 | radeon_fini(rdev); |
1060 | radeon_agp_disable(rdev); |
||
1061 | r = radeon_init(rdev); |
||
1062 | if (r) |
||
1179 | serge | 1063 | return r; |
1126 | serge | 1064 | } |
1179 | serge | 1065 | // if (radeon_testing) { |
1066 | // radeon_test_moves(rdev); |
||
1125 | serge | 1067 | // } |
2997 | Serge | 1068 | // if ((radeon_testing & 2)) { |
1069 | // radeon_test_syncing(rdev); |
||
1070 | // } |
||
2005 | serge | 1071 | if (radeon_benchmarking) { |
2997 | Serge | 1072 | radeon_benchmark(rdev, radeon_benchmarking); |
2005 | serge | 1073 | } |
1179 | serge | 1074 | return 0; |
1117 | serge | 1075 | } |
1076 | |||
2997 | Serge | 1077 | /** |
1078 | * radeon_gpu_reset - reset the asic |
||
1079 | * |
||
1080 | * @rdev: radeon device pointer |
||
1081 | * |
||
1082 | * Attempt the reset the GPU if it has hung (all asics). |
||
1083 | * Returns 0 for success or an error on failure. |
||
1084 | */ |
||
1085 | int radeon_gpu_reset(struct radeon_device *rdev) |
||
1086 | { |
||
1087 | unsigned ring_sizes[RADEON_NUM_RINGS]; |
||
1088 | uint32_t *ring_data[RADEON_NUM_RINGS]; |
||
1179 | serge | 1089 | |
2997 | Serge | 1090 | bool saved = false; |
1091 | |||
1092 | int i, r; |
||
1093 | int resched; |
||
1094 | |||
1095 | // down_write(&rdev->exclusive_lock); |
||
1096 | radeon_save_bios_scratch_regs(rdev); |
||
1097 | /* block TTM */ |
||
1098 | // resched = ttm_bo_lock_delayed_workqueue(&rdev->mman.bdev); |
||
1099 | radeon_suspend(rdev); |
||
1100 | |||
1101 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
||
1102 | ring_sizes[i] = radeon_ring_backup(rdev, &rdev->ring[i], |
||
1103 | &ring_data[i]); |
||
1104 | if (ring_sizes[i]) { |
||
1105 | saved = true; |
||
1106 | dev_info(rdev->dev, "Saved %d dwords of commands " |
||
1107 | "on ring %d.\n", ring_sizes[i], i); |
||
1108 | } |
||
1109 | } |
||
1110 | |||
1111 | retry: |
||
1112 | r = radeon_asic_reset(rdev); |
||
1113 | if (!r) { |
||
1114 | dev_info(rdev->dev, "GPU reset succeeded, trying to resume\n"); |
||
1115 | radeon_resume(rdev); |
||
1116 | } |
||
1117 | |||
1118 | radeon_restore_bios_scratch_regs(rdev); |
||
1119 | drm_helper_resume_force_mode(rdev->ddev); |
||
1120 | |||
1121 | if (!r) { |
||
1122 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
||
1123 | radeon_ring_restore(rdev, &rdev->ring[i], |
||
1124 | ring_sizes[i], ring_data[i]); |
||
1125 | ring_sizes[i] = 0; |
||
1126 | ring_data[i] = NULL; |
||
1127 | } |
||
1128 | |||
1129 | r = radeon_ib_ring_tests(rdev); |
||
1130 | if (r) { |
||
1131 | dev_err(rdev->dev, "ib ring test failed (%d).\n", r); |
||
1132 | if (saved) { |
||
1133 | saved = false; |
||
1134 | radeon_suspend(rdev); |
||
1135 | goto retry; |
||
1136 | } |
||
1137 | } |
||
1138 | } else { |
||
1139 | for (i = 0; i < RADEON_NUM_RINGS; ++i) { |
||
1140 | kfree(ring_data[i]); |
||
1141 | } |
||
1142 | } |
||
1143 | |||
1144 | // ttm_bo_unlock_delayed_workqueue(&rdev->mman.bdev, resched); |
||
1145 | if (r) { |
||
1146 | /* bad news, how to tell it to userspace ? */ |
||
1147 | dev_info(rdev->dev, "GPU reset failed\n"); |
||
1148 | } |
||
1149 | |||
1150 | // up_write(&rdev->exclusive_lock); |
||
1151 | return r; |
||
1152 | } |
||
1153 | |||
1154 | |||
1155 | |||
1117 | serge | 1156 | /* |
1157 | * Driver load/unload |
||
1158 | */ |
||
1159 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
||
1160 | { |
||
1161 | struct radeon_device *rdev; |
||
1162 | int r; |
||
1163 | |||
1182 | serge | 1164 | ENTER(); |
1117 | serge | 1165 | |
1120 | serge | 1166 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); |
1117 | serge | 1167 | if (rdev == NULL) { |
1168 | return -ENOMEM; |
||
1169 | }; |
||
1170 | |||
1171 | dev->dev_private = (void *)rdev; |
||
1172 | |||
1173 | /* update BUS flag */ |
||
1239 | serge | 1174 | if (drm_device_is_agp(dev)) { |
1117 | serge | 1175 | flags |= RADEON_IS_AGP; |
1239 | serge | 1176 | } else if (drm_device_is_pcie(dev)) { |
1177 | flags |= RADEON_IS_PCIE; |
||
1178 | } else { |
||
1179 | flags |= RADEON_IS_PCI; |
||
1180 | } |
||
1117 | serge | 1181 | |
1182 | serge | 1182 | /* radeon_device_init should report only fatal error |
1183 | * like memory allocation failure or iomapping failure, |
||
1184 | * or memory manager initialization failure, it must |
||
1185 | * properly initialize the GPU MC controller and permit |
||
1186 | * VRAM allocation |
||
1187 | */ |
||
1117 | serge | 1188 | r = radeon_device_init(rdev, dev, dev->pdev, flags); |
1189 | if (r) { |
||
1182 | serge | 1190 | DRM_ERROR("Fatal error while trying to initialize radeon.\n"); |
1117 | serge | 1191 | return r; |
1192 | } |
||
1182 | serge | 1193 | /* Again modeset_init should fail only on fatal error |
1194 | * otherwise it should provide enough functionalities |
||
1195 | * for shadowfb to run |
||
1196 | */ |
||
1246 | serge | 1197 | if( radeon_modeset ) |
1198 | { |
||
1268 | serge | 1199 | r = radeon_modeset_init(rdev); |
1200 | if (r) { |
||
1201 | return r; |
||
1202 | } |
||
1246 | serge | 1203 | }; |
1117 | serge | 1204 | return 0; |
1205 | } |
||
1206 | |||
1404 | serge | 1207 | videomode_t usermode; |
1230 | serge | 1208 | |
1239 | serge | 1209 | |
1117 | serge | 1210 | int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent) |
1211 | { |
||
1246 | serge | 1212 | static struct drm_device *dev; |
1117 | serge | 1213 | int ret; |
1214 | |||
1221 | serge | 1215 | ENTER(); |
1117 | serge | 1216 | |
1246 | serge | 1217 | dev = kzalloc(sizeof(*dev), 0); |
1117 | serge | 1218 | if (!dev) |
1219 | return -ENOMEM; |
||
1220 | |||
1221 | // ret = pci_enable_device(pdev); |
||
1222 | // if (ret) |
||
1223 | // goto err_g1; |
||
1224 | |||
1225 | // pci_set_master(pdev); |
||
1226 | |||
1227 | // if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) { |
||
1228 | // printk(KERN_ERR "DRM: Fill_in_dev failed.\n"); |
||
1229 | // goto err_g2; |
||
1230 | // } |
||
1231 | |||
1232 | dev->pdev = pdev; |
||
1233 | dev->pci_device = pdev->device; |
||
1234 | dev->pci_vendor = pdev->vendor; |
||
1235 | |||
1630 | serge | 1236 | INIT_LIST_HEAD(&dev->filelist); |
1237 | INIT_LIST_HEAD(&dev->ctxlist); |
||
1238 | INIT_LIST_HEAD(&dev->vmalist); |
||
1239 | INIT_LIST_HEAD(&dev->maplist); |
||
1240 | |||
1241 | spin_lock_init(&dev->count_lock); |
||
1242 | mutex_init(&dev->struct_mutex); |
||
1243 | mutex_init(&dev->ctxlist_mutex); |
||
1244 | |||
1245 | |||
1221 | serge | 1246 | ret = radeon_driver_load_kms(dev, ent->driver_data ); |
1247 | if (ret) |
||
1117 | serge | 1248 | goto err_g4; |
1249 | |||
3120 | serge | 1250 | main_drm_device = dev; |
1251 | |||
1986 | serge | 1252 | if( radeon_modeset ) |
1253 | init_display_kms(dev->dev_private, &usermode); |
||
1254 | else |
||
1268 | serge | 1255 | init_display(dev->dev_private, &usermode); |
1126 | serge | 1256 | |
2160 | serge | 1257 | |
1221 | serge | 1258 | LEAVE(); |
1259 | |||
1117 | serge | 1260 | return 0; |
1261 | |||
1262 | err_g4: |
||
1263 | // drm_put_minor(&dev->primary); |
||
1264 | //err_g3: |
||
1265 | // if (drm_core_check_feature(dev, DRIVER_MODESET)) |
||
1266 | // drm_put_minor(&dev->control); |
||
1267 | //err_g2: |
||
1268 | // pci_disable_device(pdev); |
||
1269 | //err_g1: |
||
1270 | free(dev); |
||
1271 | |||
1221 | serge | 1272 | LEAVE(); |
1273 | |||
1117 | serge | 1274 | return ret; |
1275 | } |
||
1276 | |||
1277 | resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource) |
||
1278 | { |
||
1279 | return pci_resource_start(dev->pdev, resource); |
||
1280 | } |
||
1281 | |||
1282 | resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource) |
||
1283 | { |
||
1284 | return pci_resource_len(dev->pdev, resource); |
||
1285 | } |
||
1286 | |||
1123 | serge | 1287 | |
1288 | uint32_t __div64_32(uint64_t *n, uint32_t base) |
||
1289 | { |
||
1290 | uint64_t rem = *n; |
||
1291 | uint64_t b = base; |
||
1292 | uint64_t res, d = 1; |
||
1293 | uint32_t high = rem >> 32; |
||
1294 | |||
1295 | /* Reduce the thing a bit first */ |
||
1296 | res = 0; |
||
1297 | if (high >= base) { |
||
1298 | high /= base; |
||
1299 | res = (uint64_t) high << 32; |
||
1300 | rem -= (uint64_t) (high*base) << 32; |
||
1301 | } |
||
1302 | |||
1303 | while ((int64_t)b > 0 && b < rem) { |
||
1304 | b = b+b; |
||
1305 | d = d+d; |
||
1306 | } |
||
1307 | |||
1308 | do { |
||
1309 | if (rem >= b) { |
||
1310 | rem -= b; |
||
1311 | res += d; |
||
1312 | } |
||
1313 | b >>= 1; |
||
1314 | d >>= 1; |
||
1315 | } while (d); |
||
1316 | |||
1317 | *n = res; |
||
1318 | return rem; |
||
1319 | } |
||
1320 | |||
1239 | serge | 1321 | |
1322 | static struct pci_device_id pciidlist[] = { |
||
1323 | radeon_PCI_IDS |
||
1324 | }; |
||
1325 | |||
1326 | |||
3120 | serge | 1327 | #define CURRENT_API 0x0200 /* 2.00 */ |
1328 | #define COMPATIBLE_API 0x0100 /* 1.00 */ |
||
1239 | serge | 1329 | |
3120 | serge | 1330 | #define API_VERSION (COMPATIBLE_API << 16) | CURRENT_API |
1331 | |||
2997 | Serge | 1332 | #define SRV_GETVERSION 0 |
1333 | #define SRV_ENUM_MODES 1 |
||
1334 | #define SRV_SET_MODE 2 |
||
3120 | serge | 1335 | #define SRV_GET_CAPS 3 |
1239 | serge | 1336 | |
3120 | serge | 1337 | #define SRV_CREATE_SURFACE 10 |
1338 | #define SRV_DESTROY_SURFACE 11 |
||
1339 | #define SRV_LOCK_SURFACE 12 |
||
1340 | #define SRV_UNLOCK_SURFACE 13 |
||
1341 | #define SRV_RESIZE_SURFACE 14 |
||
1342 | #define SRV_BLIT_BITMAP 15 |
||
1343 | #define SRV_BLIT_TEXTURE 16 |
||
1344 | #define SRV_BLIT_VIDEO 17 |
||
2007 | serge | 1345 | |
2175 | serge | 1346 | |
3120 | serge | 1347 | |
2007 | serge | 1348 | int r600_video_blit(uint64_t src_offset, int x, int y, |
1349 | int w, int h, int pitch); |
||
1350 | |||
2175 | serge | 1351 | #define check_input(size) \ |
1352 | if( unlikely((inp==NULL)||(io->inp_size != (size))) ) \ |
||
1353 | break; |
||
1354 | |||
1355 | #define check_output(size) \ |
||
1356 | if( unlikely((outp==NULL)||(io->out_size != (size))) ) \ |
||
1357 | break; |
||
1358 | |||
1239 | serge | 1359 | int _stdcall display_handler(ioctl_t *io) |
1360 | { |
||
1361 | int retval = -1; |
||
1362 | u32_t *inp; |
||
1363 | u32_t *outp; |
||
1364 | |||
1365 | inp = io->input; |
||
1366 | outp = io->output; |
||
1367 | |||
1368 | switch(io->io_code) |
||
1369 | { |
||
1370 | case SRV_GETVERSION: |
||
2175 | serge | 1371 | check_output(4); |
2997 | Serge | 1372 | *outp = API_VERSION; |
1373 | retval = 0; |
||
1239 | serge | 1374 | break; |
1375 | |||
1376 | case SRV_ENUM_MODES: |
||
1377 | dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n", |
||
1378 | inp, io->inp_size, io->out_size ); |
||
2175 | serge | 1379 | check_output(4); |
1380 | if( radeon_modeset) |
||
1404 | serge | 1381 | retval = get_modes((videomode_t*)inp, outp); |
1239 | serge | 1382 | break; |
1383 | |||
1384 | case SRV_SET_MODE: |
||
1246 | serge | 1385 | dbgprintf("SRV_SET_MODE inp %x inp_size %x\n", |
1386 | inp, io->inp_size); |
||
2175 | serge | 1387 | check_input(sizeof(videomode_t)); |
1388 | if( radeon_modeset ) |
||
1404 | serge | 1389 | retval = set_user_mode((videomode_t*)inp); |
1239 | serge | 1390 | break; |
2007 | serge | 1391 | |
3120 | serge | 1392 | case SRV_GET_CAPS: |
1393 | retval = get_driver_caps((hwcaps_t*)inp); |
||
2007 | serge | 1394 | break; |
1395 | |||
3120 | serge | 1396 | case SRV_CREATE_SURFACE: |
1397 | // check_input(8); |
||
1398 | retval = create_surface(main_drm_device, (struct io_call_10*)inp); |
||
2007 | serge | 1399 | break; |
1400 | |||
3120 | serge | 1401 | case SRV_LOCK_SURFACE: |
1402 | retval = lock_surface((struct io_call_12*)inp); |
||
2175 | serge | 1403 | break; |
1404 | |||
3120 | serge | 1405 | case SRV_BLIT_BITMAP: |
1406 | srv_blit_bitmap( inp[0], inp[1], inp[2], |
||
1407 | inp[3], inp[4], inp[5], inp[6]); |
||
1408 | |||
1239 | serge | 1409 | }; |
1410 | |||
1411 | return retval; |
||
1412 | } |
||
1413 | |||
1246 | serge | 1414 | static char log[256]; |
1404 | serge | 1415 | static pci_dev_t device; |
1246 | serge | 1416 | |
2160 | serge | 1417 | u32_t drvEntry(int action, char *cmdline) |
1239 | serge | 1418 | { |
1428 | serge | 1419 | struct radeon_device *rdev = NULL; |
1420 | |||
2997 | Serge | 1421 | const struct pci_device_id *ent; |
1239 | serge | 1422 | |
1423 | int err; |
||
1424 | u32_t retval = 0; |
||
1425 | |||
1426 | if(action != 1) |
||
1427 | return 0; |
||
1428 | |||
1429 | if( GetService("DISPLAY") != 0 ) |
||
1430 | return 0; |
||
1431 | |||
1432 | if( cmdline && *cmdline ) |
||
1268 | serge | 1433 | parse_cmdline(cmdline, &usermode, log, &radeon_modeset); |
1239 | serge | 1434 | |
1435 | if(!dbg_open(log)) |
||
1436 | { |
||
1990 | serge | 1437 | strcpy(log, "/RD/1/DRIVERS/atikms.log"); |
1239 | serge | 1438 | |
1439 | if(!dbg_open(log)) |
||
1440 | { |
||
1441 | printf("Can't open %s\nExit\n", log); |
||
1442 | return 0; |
||
1443 | }; |
||
1444 | } |
||
2997 | Serge | 1445 | dbgprintf("Radeon RC12 preview 1 cmdline %s\n", cmdline); |
1239 | serge | 1446 | |
1447 | enum_pci_devices(); |
||
1963 | serge | 1448 | |
1239 | serge | 1449 | ent = find_pci_device(&device, pciidlist); |
1450 | |||
1451 | if( unlikely(ent == NULL) ) |
||
1452 | { |
||
1453 | dbgprintf("device not found\n"); |
||
1454 | return 0; |
||
1455 | }; |
||
1456 | |||
1457 | dbgprintf("device %x:%x\n", device.pci_dev.vendor, |
||
1458 | device.pci_dev.device); |
||
1459 | |||
1460 | err = drm_get_dev(&device.pci_dev, ent); |
||
1461 | |||
1428 | serge | 1462 | rdev = rdisplay->ddev->dev_private; |
1463 | |||
1246 | serge | 1464 | err = RegService("DISPLAY", display_handler); |
1239 | serge | 1465 | |
1246 | serge | 1466 | if( err != 0) |
1467 | dbgprintf("Set DISPLAY handler\n"); |
||
1468 | |||
1469 | return err; |
||
1239 | serge | 1470 | }; |
1430 | serge | 1471 | |
2997 | Serge | 1472 | #define PCI_CLASS_REVISION 0x08 |
1473 | #define PCI_CLASS_DISPLAY_VGA 0x0300 |
||
1474 | |||
1475 | int pci_scan_filter(u32_t id, u32_t busnr, u32_t devfn) |
||
1476 | { |
||
1477 | u16_t vendor, device; |
||
1478 | u32_t class; |
||
1479 | int ret = 0; |
||
1480 | |||
1481 | vendor = id & 0xffff; |
||
1482 | device = (id >> 16) & 0xffff; |
||
1483 | |||
1484 | if(vendor == 0x1002) |
||
1485 | { |
||
1486 | class = PciRead32(busnr, devfn, PCI_CLASS_REVISION); |
||
1487 | class >>= 16; |
||
1488 | |||
1489 | if( class == PCI_CLASS_DISPLAY_VGA) |
||
1490 | ret = 1; |
||
1491 | } |
||
1492 | return ret; |
||
1493 | }><>>><>><>>>>>=>><>><>>><>>>=>><>>>>>>>> |