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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | //#include |
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1123 | serge | 29 | |
1179 | serge | 30 | #include |
31 | #include |
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1221 | serge | 32 | #include |
1117 | serge | 33 | #include "radeon_reg.h" |
34 | #include "radeon.h" |
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35 | #include "atom.h" |
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1428 | serge | 36 | #include "display.h" |
1117 | serge | 37 | |
1221 | serge | 38 | #include |
39 | |||
1117 | serge | 40 | |
1430 | serge | 41 | int radeon_no_wb; |
42 | int radeon_modeset = -1; |
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43 | int radeon_dynclks = -1; |
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44 | int radeon_r4xx_atom = 0; |
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45 | int radeon_agpmode = 0; |
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46 | int radeon_vram_limit = 0; |
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47 | int radeon_gart_size = 512; /* default gart size */ |
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48 | int radeon_benchmarking = 0; |
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49 | int radeon_testing = 0; |
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50 | int radeon_connector_table = 0; |
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51 | int radeon_tv = 1; |
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52 | int radeon_new_pll = -1; |
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53 | int radeon_dynpm = -1; |
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54 | int radeon_audio = 1; |
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1963 | serge | 55 | int radeon_hw_i2c = 0; |
56 | int radeon_pcie_gen2 = 0; |
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57 | int radeon_disp_priority = 0; |
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1117 | serge | 58 | |
1430 | serge | 59 | |
1963 | serge | 60 | |
1428 | serge | 61 | extern display_t *rdisplay; |
1246 | serge | 62 | |
1404 | serge | 63 | void parse_cmdline(char *cmdline, videomode_t *mode, char *log, int *kms); |
64 | int init_display(struct radeon_device *rdev, videomode_t *mode); |
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65 | int init_display_kms(struct radeon_device *rdev, videomode_t *mode); |
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1117 | serge | 66 | |
1404 | serge | 67 | int get_modes(videomode_t *mode, int *count); |
68 | int set_user_mode(videomode_t *mode); |
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1428 | serge | 69 | int r100_2D_test(struct radeon_device *rdev); |
1239 | serge | 70 | |
1404 | serge | 71 | |
1233 | serge | 72 | /* Legacy VGA regions */ |
73 | #define VGA_RSRC_NONE 0x00 |
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74 | #define VGA_RSRC_LEGACY_IO 0x01 |
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75 | #define VGA_RSRC_LEGACY_MEM 0x02 |
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76 | #define VGA_RSRC_LEGACY_MASK (VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM) |
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77 | /* Non-legacy access */ |
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78 | #define VGA_RSRC_NORMAL_IO 0x04 |
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79 | #define VGA_RSRC_NORMAL_MEM 0x08 |
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80 | |||
81 | |||
1963 | serge | 82 | static const char radeon_family_name[][16] = { |
83 | "R100", |
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84 | "RV100", |
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85 | "RS100", |
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86 | "RV200", |
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87 | "RS200", |
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88 | "R200", |
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89 | "RV250", |
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90 | "RS300", |
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91 | "RV280", |
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92 | "R300", |
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93 | "R350", |
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94 | "RV350", |
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95 | "RV380", |
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96 | "R420", |
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97 | "R423", |
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98 | "RV410", |
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99 | "RS400", |
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100 | "RS480", |
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101 | "RS600", |
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102 | "RS690", |
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103 | "RS740", |
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104 | "RV515", |
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105 | "R520", |
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106 | "RV530", |
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107 | "RV560", |
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108 | "RV570", |
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109 | "R580", |
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110 | "R600", |
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111 | "RV610", |
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112 | "RV630", |
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113 | "RV670", |
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114 | "RV620", |
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115 | "RV635", |
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116 | "RS780", |
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117 | "RS880", |
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118 | "RV770", |
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119 | "RV730", |
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120 | "RV710", |
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121 | "RV740", |
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122 | "CEDAR", |
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123 | "REDWOOD", |
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124 | "JUNIPER", |
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125 | "CYPRESS", |
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126 | "HEMLOCK", |
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127 | "PALM", |
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1986 | serge | 128 | "SUMO", |
129 | "SUMO2", |
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1963 | serge | 130 | "BARTS", |
131 | "TURKS", |
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132 | "CAICOS", |
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133 | "CAYMAN", |
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134 | "LAST", |
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135 | }; |
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1233 | serge | 136 | |
1117 | serge | 137 | /* |
138 | * Clear GPU surface registers. |
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139 | */ |
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1179 | serge | 140 | void radeon_surface_init(struct radeon_device *rdev) |
1117 | serge | 141 | { |
142 | /* FIXME: check this out */ |
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143 | if (rdev->family < CHIP_R600) { |
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144 | int i; |
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145 | |||
1321 | serge | 146 | for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) { |
1404 | serge | 147 | radeon_clear_surface_reg(rdev, i); |
1117 | serge | 148 | } |
1179 | serge | 149 | /* enable surfaces */ |
150 | WREG32(RADEON_SURFACE_CNTL, 0); |
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1117 | serge | 151 | } |
152 | } |
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153 | |||
154 | /* |
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155 | * GPU scratch registers helpers function. |
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156 | */ |
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1179 | serge | 157 | void radeon_scratch_init(struct radeon_device *rdev) |
1117 | serge | 158 | { |
159 | int i; |
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160 | |||
161 | /* FIXME: check this out */ |
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162 | if (rdev->family < CHIP_R300) { |
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163 | rdev->scratch.num_reg = 5; |
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164 | } else { |
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165 | rdev->scratch.num_reg = 7; |
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166 | } |
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1963 | serge | 167 | rdev->scratch.reg_base = RADEON_SCRATCH_REG0; |
1117 | serge | 168 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
169 | rdev->scratch.free[i] = true; |
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1963 | serge | 170 | rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); |
1117 | serge | 171 | } |
172 | } |
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173 | |||
174 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) |
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175 | { |
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176 | int i; |
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177 | |||
178 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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179 | if (rdev->scratch.free[i]) { |
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180 | rdev->scratch.free[i] = false; |
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181 | *reg = rdev->scratch.reg[i]; |
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182 | return 0; |
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183 | } |
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184 | } |
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185 | return -EINVAL; |
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186 | } |
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187 | |||
188 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) |
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189 | { |
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190 | int i; |
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191 | |||
192 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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193 | if (rdev->scratch.reg[i] == reg) { |
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194 | rdev->scratch.free[i] = true; |
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195 | return; |
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196 | } |
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197 | } |
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198 | } |
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199 | |||
2004 | serge | 200 | void radeon_wb_disable(struct radeon_device *rdev) |
201 | { |
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202 | int r; |
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203 | |||
204 | if (rdev->wb.wb_obj) { |
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205 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
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206 | if (unlikely(r != 0)) |
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207 | return; |
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208 | radeon_bo_kunmap(rdev->wb.wb_obj); |
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209 | radeon_bo_unpin(rdev->wb.wb_obj); |
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210 | radeon_bo_unreserve(rdev->wb.wb_obj); |
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211 | } |
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212 | rdev->wb.enabled = false; |
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213 | } |
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214 | |||
215 | void radeon_wb_fini(struct radeon_device *rdev) |
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216 | { |
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217 | radeon_wb_disable(rdev); |
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218 | if (rdev->wb.wb_obj) { |
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219 | radeon_bo_unref(&rdev->wb.wb_obj); |
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220 | rdev->wb.wb = NULL; |
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221 | rdev->wb.wb_obj = NULL; |
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222 | } |
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223 | } |
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224 | |||
225 | int radeon_wb_init(struct radeon_device *rdev) |
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226 | { |
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227 | int r; |
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228 | |||
229 | if (rdev->wb.wb_obj == NULL) { |
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230 | r = radeon_bo_create(rdev, RADEON_GPU_PAGE_SIZE, PAGE_SIZE, true, |
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231 | RADEON_GEM_DOMAIN_GTT, &rdev->wb.wb_obj); |
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232 | if (r) { |
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233 | dev_warn(rdev->dev, "(%d) create WB bo failed\n", r); |
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234 | return r; |
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235 | } |
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236 | } |
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237 | r = radeon_bo_reserve(rdev->wb.wb_obj, false); |
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238 | if (unlikely(r != 0)) { |
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239 | radeon_wb_fini(rdev); |
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240 | return r; |
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241 | } |
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242 | r = radeon_bo_pin(rdev->wb.wb_obj, RADEON_GEM_DOMAIN_GTT, |
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243 | &rdev->wb.gpu_addr); |
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244 | if (r) { |
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245 | radeon_bo_unreserve(rdev->wb.wb_obj); |
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246 | dev_warn(rdev->dev, "(%d) pin WB bo failed\n", r); |
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247 | radeon_wb_fini(rdev); |
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248 | return r; |
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249 | } |
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250 | r = radeon_bo_kmap(rdev->wb.wb_obj, (void **)&rdev->wb.wb); |
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251 | radeon_bo_unreserve(rdev->wb.wb_obj); |
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252 | if (r) { |
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253 | dev_warn(rdev->dev, "(%d) map WB bo failed\n", r); |
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254 | radeon_wb_fini(rdev); |
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255 | return r; |
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256 | } |
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257 | |||
258 | /* clear wb memory */ |
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259 | memset((char *)rdev->wb.wb, 0, RADEON_GPU_PAGE_SIZE); |
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260 | /* disable event_write fences */ |
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261 | rdev->wb.use_event = false; |
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262 | /* disabled via module param */ |
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263 | if (radeon_no_wb == 1) |
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264 | rdev->wb.enabled = false; |
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265 | else { |
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266 | /* often unreliable on AGP */ |
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267 | // if (rdev->flags & RADEON_IS_AGP) { |
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268 | // rdev->wb.enabled = false; |
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269 | // } else { |
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270 | rdev->wb.enabled = true; |
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271 | /* event_write fences are only available on r600+ */ |
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272 | if (rdev->family >= CHIP_R600) |
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273 | rdev->wb.use_event = true; |
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274 | // } |
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275 | } |
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276 | /* always use writeback/events on NI */ |
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277 | if (ASIC_IS_DCE5(rdev)) { |
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278 | rdev->wb.enabled = true; |
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279 | rdev->wb.use_event = true; |
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280 | } |
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281 | |||
282 | dev_info(rdev->dev, "WB %sabled\n", rdev->wb.enabled ? "en" : "dis"); |
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283 | |||
284 | return 0; |
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285 | } |
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286 | |||
1430 | serge | 287 | /** |
288 | * radeon_vram_location - try to find VRAM location |
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289 | * @rdev: radeon device structure holding all necessary informations |
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290 | * @mc: memory controller structure holding memory informations |
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291 | * @base: base address at which to put VRAM |
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292 | * |
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293 | * Function will place try to place VRAM at base address provided |
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294 | * as parameter (which is so far either PCI aperture address or |
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295 | * for IGP TOM base address). |
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296 | * |
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297 | * If there is not enough space to fit the unvisible VRAM in the 32bits |
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298 | * address space then we limit the VRAM size to the aperture. |
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299 | * |
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300 | * If we are using AGP and if the AGP aperture doesn't allow us to have |
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301 | * room for all the VRAM than we restrict the VRAM to the PCI aperture |
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302 | * size and print a warning. |
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303 | * |
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304 | * This function will never fails, worst case are limiting VRAM. |
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305 | * |
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306 | * Note: GTT start, end, size should be initialized before calling this |
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307 | * function on AGP platform. |
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308 | * |
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1963 | serge | 309 | * Note: We don't explicitly enforce VRAM start to be aligned on VRAM size, |
1430 | serge | 310 | * this shouldn't be a problem as we are using the PCI aperture as a reference. |
311 | * Otherwise this would be needed for rv280, all r3xx, and all r4xx, but |
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312 | * not IGP. |
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313 | * |
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314 | * Note: we use mc_vram_size as on some board we need to program the mc to |
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315 | * cover the whole aperture even if VRAM size is inferior to aperture size |
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316 | * Novell bug 204882 + along with lots of ubuntu ones |
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317 | * |
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318 | * Note: when limiting vram it's safe to overwritte real_vram_size because |
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319 | * we are not in case where real_vram_size is inferior to mc_vram_size (ie |
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320 | * note afected by bogus hw of Novell bug 204882 + along with lots of ubuntu |
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321 | * ones) |
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322 | * |
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323 | * Note: IGP TOM addr should be the same as the aperture addr, we don't |
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324 | * explicitly check for that thought. |
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325 | * |
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326 | * FIXME: when reducing VRAM size align new size on power of 2. |
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1117 | serge | 327 | */ |
1430 | serge | 328 | void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base) |
1117 | serge | 329 | { |
1430 | serge | 330 | mc->vram_start = base; |
331 | if (mc->mc_vram_size > (0xFFFFFFFF - base + 1)) { |
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332 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
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333 | mc->real_vram_size = mc->aper_size; |
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334 | mc->mc_vram_size = mc->aper_size; |
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335 | } |
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336 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
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1963 | serge | 337 | if (rdev->flags & RADEON_IS_AGP && mc->vram_end > mc->gtt_start && mc->vram_start <= mc->gtt_end) { |
1430 | serge | 338 | dev_warn(rdev->dev, "limiting VRAM to PCI aperture size\n"); |
339 | mc->real_vram_size = mc->aper_size; |
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340 | mc->mc_vram_size = mc->aper_size; |
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341 | } |
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342 | mc->vram_end = mc->vram_start + mc->mc_vram_size - 1; |
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1963 | serge | 343 | dev_info(rdev->dev, "VRAM: %lluM 0x%016llX - 0x%016llX (%lluM used)\n", |
1430 | serge | 344 | mc->mc_vram_size >> 20, mc->vram_start, |
345 | mc->vram_end, mc->real_vram_size >> 20); |
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346 | } |
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1117 | serge | 347 | |
1430 | serge | 348 | /** |
349 | * radeon_gtt_location - try to find GTT location |
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350 | * @rdev: radeon device structure holding all necessary informations |
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351 | * @mc: memory controller structure holding memory informations |
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352 | * |
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353 | * Function will place try to place GTT before or after VRAM. |
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354 | * |
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355 | * If GTT size is bigger than space left then we ajust GTT size. |
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356 | * Thus function will never fails. |
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357 | * |
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358 | * FIXME: when reducing GTT size align new size on power of 2. |
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359 | */ |
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360 | void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc) |
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361 | { |
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362 | u64 size_af, size_bf; |
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363 | |||
1963 | serge | 364 | size_af = ((0xFFFFFFFF - mc->vram_end) + mc->gtt_base_align) & ~mc->gtt_base_align; |
365 | size_bf = mc->vram_start & ~mc->gtt_base_align; |
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1430 | serge | 366 | if (size_bf > size_af) { |
367 | if (mc->gtt_size > size_bf) { |
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368 | dev_warn(rdev->dev, "limiting GTT\n"); |
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369 | mc->gtt_size = size_bf; |
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1117 | serge | 370 | } |
1963 | serge | 371 | mc->gtt_start = (mc->vram_start & ~mc->gtt_base_align) - mc->gtt_size; |
1430 | serge | 372 | } else { |
373 | if (mc->gtt_size > size_af) { |
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374 | dev_warn(rdev->dev, "limiting GTT\n"); |
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375 | mc->gtt_size = size_af; |
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1117 | serge | 376 | } |
1963 | serge | 377 | mc->gtt_start = (mc->vram_end + 1 + mc->gtt_base_align) & ~mc->gtt_base_align; |
1117 | serge | 378 | } |
1430 | serge | 379 | mc->gtt_end = mc->gtt_start + mc->gtt_size - 1; |
1963 | serge | 380 | dev_info(rdev->dev, "GTT: %lluM 0x%016llX - 0x%016llX\n", |
1430 | serge | 381 | mc->gtt_size >> 20, mc->gtt_start, mc->gtt_end); |
1117 | serge | 382 | } |
383 | |||
384 | /* |
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385 | * GPU helpers function. |
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386 | */ |
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1179 | serge | 387 | bool radeon_card_posted(struct radeon_device *rdev) |
1117 | serge | 388 | { |
389 | uint32_t reg; |
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390 | |||
391 | /* first check CRTCs */ |
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1963 | serge | 392 | if (ASIC_IS_DCE41(rdev)) { |
1430 | serge | 393 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
1963 | serge | 394 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET); |
395 | if (reg & EVERGREEN_CRTC_MASTER_EN) |
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396 | return true; |
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397 | } else if (ASIC_IS_DCE4(rdev)) { |
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398 | reg = RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC0_REGISTER_OFFSET) | |
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1430 | serge | 399 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC1_REGISTER_OFFSET) | |
400 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC2_REGISTER_OFFSET) | |
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401 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC3_REGISTER_OFFSET) | |
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402 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC4_REGISTER_OFFSET) | |
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403 | RREG32(EVERGREEN_CRTC_CONTROL + EVERGREEN_CRTC5_REGISTER_OFFSET); |
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404 | if (reg & EVERGREEN_CRTC_MASTER_EN) |
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405 | return true; |
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406 | } else if (ASIC_IS_AVIVO(rdev)) { |
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1117 | serge | 407 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
408 | RREG32(AVIVO_D2CRTC_CONTROL); |
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409 | if (reg & AVIVO_CRTC_EN) { |
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410 | return true; |
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411 | } |
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412 | } else { |
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413 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | |
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414 | RREG32(RADEON_CRTC2_GEN_CNTL); |
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415 | if (reg & RADEON_CRTC_EN) { |
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416 | return true; |
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417 | } |
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418 | } |
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419 | |||
420 | /* then check MEM_SIZE, in case the crtcs are off */ |
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421 | if (rdev->family >= CHIP_R600) |
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422 | reg = RREG32(R600_CONFIG_MEMSIZE); |
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423 | else |
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424 | reg = RREG32(RADEON_CONFIG_MEMSIZE); |
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425 | |||
426 | if (reg) |
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427 | return true; |
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428 | |||
429 | return false; |
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430 | |||
431 | } |
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432 | |||
1963 | serge | 433 | void radeon_update_bandwidth_info(struct radeon_device *rdev) |
434 | { |
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435 | fixed20_12 a; |
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436 | u32 sclk = rdev->pm.current_sclk; |
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437 | u32 mclk = rdev->pm.current_mclk; |
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438 | |||
439 | /* sclk/mclk in Mhz */ |
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440 | a.full = dfixed_const(100); |
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441 | rdev->pm.sclk.full = dfixed_const(sclk); |
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442 | rdev->pm.sclk.full = dfixed_div(rdev->pm.sclk, a); |
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443 | rdev->pm.mclk.full = dfixed_const(mclk); |
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444 | rdev->pm.mclk.full = dfixed_div(rdev->pm.mclk, a); |
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445 | |||
446 | if (rdev->flags & RADEON_IS_IGP) { |
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447 | a.full = dfixed_const(16); |
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448 | /* core_bandwidth = sclk(Mhz) * 16 */ |
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449 | rdev->pm.core_bandwidth.full = dfixed_div(rdev->pm.sclk, a); |
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450 | } |
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451 | } |
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452 | |||
1321 | serge | 453 | bool radeon_boot_test_post_card(struct radeon_device *rdev) |
454 | { |
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455 | if (radeon_card_posted(rdev)) |
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456 | return true; |
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457 | |||
458 | if (rdev->bios) { |
||
459 | DRM_INFO("GPU not posted. posting now...\n"); |
||
460 | if (rdev->is_atom_bios) |
||
461 | atom_asic_init(rdev->mode_info.atom_context); |
||
462 | else |
||
463 | radeon_combios_asic_init(rdev->ddev); |
||
464 | return true; |
||
465 | } else { |
||
466 | dev_err(rdev->dev, "Card not posted and no BIOS - ignoring\n"); |
||
467 | return false; |
||
468 | } |
||
469 | } |
||
470 | |||
1233 | serge | 471 | int radeon_dummy_page_init(struct radeon_device *rdev) |
472 | { |
||
1430 | serge | 473 | if (rdev->dummy_page.page) |
474 | return 0; |
||
1233 | serge | 475 | rdev->dummy_page.page = AllocPage(); |
476 | if (rdev->dummy_page.page == NULL) |
||
477 | return -ENOMEM; |
||
478 | rdev->dummy_page.addr = MapIoMem(rdev->dummy_page.page, 4096, 5); |
||
479 | if (!rdev->dummy_page.addr) { |
||
480 | // __free_page(rdev->dummy_page.page); |
||
481 | rdev->dummy_page.page = NULL; |
||
482 | return -ENOMEM; |
||
483 | } |
||
484 | return 0; |
||
485 | } |
||
1117 | serge | 486 | |
1233 | serge | 487 | void radeon_dummy_page_fini(struct radeon_device *rdev) |
488 | { |
||
489 | if (rdev->dummy_page.page == NULL) |
||
490 | return; |
||
491 | KernelFree(rdev->dummy_page.addr); |
||
492 | rdev->dummy_page.page = NULL; |
||
493 | } |
||
494 | |||
495 | |||
1117 | serge | 496 | /* ATOM accessor methods */ |
497 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) |
||
498 | { |
||
499 | struct radeon_device *rdev = info->dev->dev_private; |
||
500 | uint32_t r; |
||
501 | |||
502 | r = rdev->pll_rreg(rdev, reg); |
||
503 | return r; |
||
504 | } |
||
505 | |||
506 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) |
||
507 | { |
||
508 | struct radeon_device *rdev = info->dev->dev_private; |
||
509 | |||
510 | rdev->pll_wreg(rdev, reg, val); |
||
511 | } |
||
512 | |||
513 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) |
||
514 | { |
||
515 | struct radeon_device *rdev = info->dev->dev_private; |
||
516 | uint32_t r; |
||
517 | |||
518 | r = rdev->mc_rreg(rdev, reg); |
||
519 | return r; |
||
520 | } |
||
521 | |||
522 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) |
||
523 | { |
||
524 | struct radeon_device *rdev = info->dev->dev_private; |
||
525 | |||
526 | rdev->mc_wreg(rdev, reg, val); |
||
527 | } |
||
528 | |||
529 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) |
||
530 | { |
||
531 | struct radeon_device *rdev = info->dev->dev_private; |
||
532 | |||
533 | WREG32(reg*4, val); |
||
534 | } |
||
535 | |||
536 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) |
||
537 | { |
||
538 | struct radeon_device *rdev = info->dev->dev_private; |
||
539 | uint32_t r; |
||
540 | |||
541 | r = RREG32(reg*4); |
||
542 | return r; |
||
543 | } |
||
544 | |||
1963 | serge | 545 | static void cail_ioreg_write(struct card_info *info, uint32_t reg, uint32_t val) |
546 | { |
||
547 | struct radeon_device *rdev = info->dev->dev_private; |
||
548 | |||
549 | WREG32_IO(reg*4, val); |
||
550 | } |
||
551 | |||
552 | static uint32_t cail_ioreg_read(struct card_info *info, uint32_t reg) |
||
553 | { |
||
554 | struct radeon_device *rdev = info->dev->dev_private; |
||
555 | uint32_t r; |
||
556 | |||
557 | r = RREG32_IO(reg*4); |
||
558 | return r; |
||
559 | } |
||
560 | |||
1117 | serge | 561 | int radeon_atombios_init(struct radeon_device *rdev) |
562 | { |
||
1268 | serge | 563 | struct card_info *atom_card_info = |
564 | kzalloc(sizeof(struct card_info), GFP_KERNEL); |
||
1117 | serge | 565 | |
1268 | serge | 566 | if (!atom_card_info) |
567 | return -ENOMEM; |
||
568 | |||
569 | rdev->mode_info.atom_card_info = atom_card_info; |
||
570 | atom_card_info->dev = rdev->ddev; |
||
571 | atom_card_info->reg_read = cail_reg_read; |
||
572 | atom_card_info->reg_write = cail_reg_write; |
||
1963 | serge | 573 | /* needed for iio ops */ |
574 | if (rdev->rio_mem) { |
||
575 | atom_card_info->ioreg_read = cail_ioreg_read; |
||
576 | atom_card_info->ioreg_write = cail_ioreg_write; |
||
577 | } else { |
||
578 | DRM_ERROR("Unable to find PCI I/O BAR; using MMIO for ATOM IIO\n"); |
||
579 | atom_card_info->ioreg_read = cail_reg_read; |
||
580 | atom_card_info->ioreg_write = cail_reg_write; |
||
581 | } |
||
1268 | serge | 582 | atom_card_info->mc_read = cail_mc_read; |
583 | atom_card_info->mc_write = cail_mc_write; |
||
584 | atom_card_info->pll_read = cail_pll_read; |
||
585 | atom_card_info->pll_write = cail_pll_write; |
||
586 | |||
587 | rdev->mode_info.atom_context = atom_parse(atom_card_info, rdev->bios); |
||
1630 | serge | 588 | mutex_init(&rdev->mode_info.atom_context->mutex); |
1117 | serge | 589 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
1321 | serge | 590 | atom_allocate_fb_scratch(rdev->mode_info.atom_context); |
1117 | serge | 591 | return 0; |
592 | } |
||
593 | |||
594 | void radeon_atombios_fini(struct radeon_device *rdev) |
||
595 | { |
||
1321 | serge | 596 | if (rdev->mode_info.atom_context) { |
597 | kfree(rdev->mode_info.atom_context->scratch); |
||
1119 | serge | 598 | kfree(rdev->mode_info.atom_context); |
1321 | serge | 599 | } |
1268 | serge | 600 | kfree(rdev->mode_info.atom_card_info); |
1117 | serge | 601 | } |
602 | |||
603 | int radeon_combios_init(struct radeon_device *rdev) |
||
604 | { |
||
1128 | serge | 605 | radeon_combios_initialize_bios_scratch_regs(rdev->ddev); |
1117 | serge | 606 | return 0; |
607 | } |
||
608 | |||
609 | void radeon_combios_fini(struct radeon_device *rdev) |
||
610 | { |
||
611 | } |
||
612 | |||
1233 | serge | 613 | /* if we get transitioned to only one device, tak VGA back */ |
614 | static unsigned int radeon_vga_set_decode(void *cookie, bool state) |
||
615 | { |
||
616 | struct radeon_device *rdev = cookie; |
||
617 | radeon_vga_set_state(rdev, state); |
||
618 | if (state) |
||
619 | return VGA_RSRC_LEGACY_IO | VGA_RSRC_LEGACY_MEM | |
||
620 | VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
||
621 | else |
||
622 | return VGA_RSRC_NORMAL_IO | VGA_RSRC_NORMAL_MEM; |
||
623 | } |
||
1117 | serge | 624 | |
1404 | serge | 625 | void radeon_check_arguments(struct radeon_device *rdev) |
626 | { |
||
627 | /* vramlimit must be a power of two */ |
||
628 | switch (radeon_vram_limit) { |
||
629 | case 0: |
||
630 | case 4: |
||
631 | case 8: |
||
632 | case 16: |
||
633 | case 32: |
||
634 | case 64: |
||
635 | case 128: |
||
636 | case 256: |
||
637 | case 512: |
||
638 | case 1024: |
||
639 | case 2048: |
||
640 | case 4096: |
||
641 | break; |
||
642 | default: |
||
643 | dev_warn(rdev->dev, "vram limit (%d) must be a power of 2\n", |
||
644 | radeon_vram_limit); |
||
645 | radeon_vram_limit = 0; |
||
646 | break; |
||
647 | } |
||
648 | radeon_vram_limit = radeon_vram_limit << 20; |
||
649 | /* gtt size must be power of two and greater or equal to 32M */ |
||
650 | switch (radeon_gart_size) { |
||
651 | case 4: |
||
652 | case 8: |
||
653 | case 16: |
||
654 | dev_warn(rdev->dev, "gart size (%d) too small forcing to 512M\n", |
||
655 | radeon_gart_size); |
||
656 | radeon_gart_size = 512; |
||
657 | break; |
||
658 | case 32: |
||
659 | case 64: |
||
660 | case 128: |
||
661 | case 256: |
||
662 | case 512: |
||
663 | case 1024: |
||
664 | case 2048: |
||
665 | case 4096: |
||
666 | break; |
||
667 | default: |
||
668 | dev_warn(rdev->dev, "gart size (%d) must be a power of 2\n", |
||
669 | radeon_gart_size); |
||
670 | radeon_gart_size = 512; |
||
671 | break; |
||
672 | } |
||
673 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
||
674 | /* AGP mode can only be -1, 1, 2, 4, 8 */ |
||
675 | switch (radeon_agpmode) { |
||
676 | case -1: |
||
677 | case 0: |
||
678 | case 1: |
||
679 | case 2: |
||
680 | case 4: |
||
681 | case 8: |
||
682 | break; |
||
683 | default: |
||
684 | dev_warn(rdev->dev, "invalid AGP mode %d (valid mode: " |
||
685 | "-1, 0, 1, 2, 4, 8)\n", radeon_agpmode); |
||
686 | radeon_agpmode = 0; |
||
687 | break; |
||
688 | } |
||
689 | } |
||
690 | |||
1117 | serge | 691 | int radeon_device_init(struct radeon_device *rdev, |
692 | struct drm_device *ddev, |
||
693 | struct pci_dev *pdev, |
||
694 | uint32_t flags) |
||
695 | { |
||
1963 | serge | 696 | int r, i; |
1179 | serge | 697 | int dma_bits; |
1117 | serge | 698 | |
699 | rdev->shutdown = false; |
||
700 | rdev->ddev = ddev; |
||
701 | rdev->pdev = pdev; |
||
702 | rdev->flags = flags; |
||
703 | rdev->family = flags & RADEON_FAMILY_MASK; |
||
704 | rdev->is_atom_bios = false; |
||
705 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; |
||
706 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
||
707 | rdev->gpu_lockup = false; |
||
1221 | serge | 708 | rdev->accel_working = false; |
1963 | serge | 709 | |
710 | DRM_INFO("initializing kernel modesetting (%s 0x%04X:0x%04X).\n", |
||
711 | radeon_family_name[rdev->family], pdev->vendor, pdev->device); |
||
712 | |||
1117 | serge | 713 | /* mutex initialization are all done here so we |
714 | * can recall function without having locking issues */ |
||
1630 | serge | 715 | mutex_init(&rdev->cs_mutex); |
716 | mutex_init(&rdev->ib_pool.mutex); |
||
717 | mutex_init(&rdev->cp.mutex); |
||
718 | mutex_init(&rdev->dc_hw_i2c_mutex); |
||
2005 | serge | 719 | if (rdev->family >= CHIP_R600) |
720 | spin_lock_init(&rdev->ih.lock); |
||
1630 | serge | 721 | mutex_init(&rdev->gem.mutex); |
722 | mutex_init(&rdev->pm.mutex); |
||
1963 | serge | 723 | mutex_init(&rdev->vram_mutex); |
2005 | serge | 724 | rwlock_init(&rdev->fence_drv.lock); |
1963 | serge | 725 | INIT_LIST_HEAD(&rdev->gem.objects); |
1117 | serge | 726 | |
1179 | serge | 727 | /* Set asic functions */ |
728 | r = radeon_asic_init(rdev); |
||
1404 | serge | 729 | if (r) |
1179 | serge | 730 | return r; |
1404 | serge | 731 | radeon_check_arguments(rdev); |
1179 | serge | 732 | |
1963 | serge | 733 | /* all of the newer IGP chips have an internal gart |
734 | * However some rs4xx report as AGP, so remove that here. |
||
735 | */ |
||
736 | if ((rdev->family >= CHIP_RS400) && |
||
737 | (rdev->flags & RADEON_IS_IGP)) { |
||
738 | rdev->flags &= ~RADEON_IS_AGP; |
||
739 | } |
||
740 | |||
1321 | serge | 741 | if (rdev->flags & RADEON_IS_AGP && radeon_agpmode == -1) { |
1221 | serge | 742 | radeon_agp_disable(rdev); |
1117 | serge | 743 | } |
744 | |||
1179 | serge | 745 | /* set DMA mask + need_dma32 flags. |
746 | * PCIE - can handle 40-bits. |
||
747 | * IGP - can handle 40-bits (in theory) |
||
748 | * AGP - generally dma32 is safest |
||
749 | * PCI - only dma32 |
||
750 | */ |
||
751 | rdev->need_dma32 = false; |
||
752 | if (rdev->flags & RADEON_IS_AGP) |
||
753 | rdev->need_dma32 = true; |
||
754 | if (rdev->flags & RADEON_IS_PCI) |
||
755 | rdev->need_dma32 = true; |
||
1117 | serge | 756 | |
1179 | serge | 757 | dma_bits = rdev->need_dma32 ? 32 : 40; |
758 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); |
||
1117 | serge | 759 | if (r) { |
1986 | serge | 760 | rdev->need_dma32 = true; |
1119 | serge | 761 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
762 | } |
||
1117 | serge | 763 | |
764 | /* Registers mapping */ |
||
765 | /* TODO: block userspace mapping of io register */ |
||
766 | rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); |
||
767 | rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); |
||
768 | |||
769 | rdev->rmmio = (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size, |
||
770 | PG_SW+PG_NOCACHE); |
||
771 | |||
772 | if (rdev->rmmio == NULL) { |
||
773 | return -ENOMEM; |
||
774 | } |
||
775 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); |
||
776 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); |
||
777 | |||
1179 | serge | 778 | r = radeon_init(rdev); |
1221 | serge | 779 | if (r) |
1963 | serge | 780 | return r; |
1117 | serge | 781 | |
1221 | serge | 782 | if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { |
783 | /* Acceleration not working on AGP card try again |
||
784 | * with fallback to PCI or PCIE GART |
||
785 | */ |
||
1963 | serge | 786 | radeon_asic_reset(rdev); |
1221 | serge | 787 | radeon_fini(rdev); |
788 | radeon_agp_disable(rdev); |
||
789 | r = radeon_init(rdev); |
||
790 | if (r) |
||
1179 | serge | 791 | return r; |
1126 | serge | 792 | } |
1179 | serge | 793 | // if (radeon_testing) { |
794 | // radeon_test_moves(rdev); |
||
1125 | serge | 795 | // } |
2005 | serge | 796 | if (radeon_benchmarking) { |
797 | radeon_benchmark(rdev); |
||
798 | } |
||
1179 | serge | 799 | return 0; |
1117 | serge | 800 | } |
801 | |||
1179 | serge | 802 | |
1117 | serge | 803 | /* |
804 | * Driver load/unload |
||
805 | */ |
||
806 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
||
807 | { |
||
808 | struct radeon_device *rdev; |
||
809 | int r; |
||
810 | |||
1182 | serge | 811 | ENTER(); |
1117 | serge | 812 | |
1120 | serge | 813 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); |
1117 | serge | 814 | if (rdev == NULL) { |
815 | return -ENOMEM; |
||
816 | }; |
||
817 | |||
818 | dev->dev_private = (void *)rdev; |
||
819 | |||
820 | /* update BUS flag */ |
||
1239 | serge | 821 | if (drm_device_is_agp(dev)) { |
1117 | serge | 822 | flags |= RADEON_IS_AGP; |
1239 | serge | 823 | } else if (drm_device_is_pcie(dev)) { |
824 | flags |= RADEON_IS_PCIE; |
||
825 | } else { |
||
826 | flags |= RADEON_IS_PCI; |
||
827 | } |
||
1117 | serge | 828 | |
1182 | serge | 829 | /* radeon_device_init should report only fatal error |
830 | * like memory allocation failure or iomapping failure, |
||
831 | * or memory manager initialization failure, it must |
||
832 | * properly initialize the GPU MC controller and permit |
||
833 | * VRAM allocation |
||
834 | */ |
||
1117 | serge | 835 | r = radeon_device_init(rdev, dev, dev->pdev, flags); |
836 | if (r) { |
||
1182 | serge | 837 | DRM_ERROR("Fatal error while trying to initialize radeon.\n"); |
1117 | serge | 838 | return r; |
839 | } |
||
1182 | serge | 840 | /* Again modeset_init should fail only on fatal error |
841 | * otherwise it should provide enough functionalities |
||
842 | * for shadowfb to run |
||
843 | */ |
||
1246 | serge | 844 | if( radeon_modeset ) |
845 | { |
||
1268 | serge | 846 | r = radeon_modeset_init(rdev); |
847 | if (r) { |
||
848 | return r; |
||
849 | } |
||
1246 | serge | 850 | }; |
1117 | serge | 851 | return 0; |
852 | } |
||
853 | |||
1404 | serge | 854 | videomode_t usermode; |
1230 | serge | 855 | |
1239 | serge | 856 | |
1117 | serge | 857 | int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent) |
858 | { |
||
1246 | serge | 859 | static struct drm_device *dev; |
1117 | serge | 860 | int ret; |
861 | |||
1221 | serge | 862 | ENTER(); |
1117 | serge | 863 | |
1246 | serge | 864 | dev = kzalloc(sizeof(*dev), 0); |
1117 | serge | 865 | if (!dev) |
866 | return -ENOMEM; |
||
867 | |||
868 | // ret = pci_enable_device(pdev); |
||
869 | // if (ret) |
||
870 | // goto err_g1; |
||
871 | |||
872 | // pci_set_master(pdev); |
||
873 | |||
874 | // if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) { |
||
875 | // printk(KERN_ERR "DRM: Fill_in_dev failed.\n"); |
||
876 | // goto err_g2; |
||
877 | // } |
||
878 | |||
879 | dev->pdev = pdev; |
||
880 | dev->pci_device = pdev->device; |
||
881 | dev->pci_vendor = pdev->vendor; |
||
882 | |||
1630 | serge | 883 | INIT_LIST_HEAD(&dev->filelist); |
884 | INIT_LIST_HEAD(&dev->ctxlist); |
||
885 | INIT_LIST_HEAD(&dev->vmalist); |
||
886 | INIT_LIST_HEAD(&dev->maplist); |
||
887 | |||
888 | spin_lock_init(&dev->count_lock); |
||
889 | mutex_init(&dev->struct_mutex); |
||
890 | mutex_init(&dev->ctxlist_mutex); |
||
891 | |||
892 | |||
1221 | serge | 893 | ret = radeon_driver_load_kms(dev, ent->driver_data ); |
894 | if (ret) |
||
1117 | serge | 895 | goto err_g4; |
896 | |||
1986 | serge | 897 | if( radeon_modeset ) |
898 | init_display_kms(dev->dev_private, &usermode); |
||
899 | else |
||
1268 | serge | 900 | init_display(dev->dev_private, &usermode); |
1126 | serge | 901 | |
1221 | serge | 902 | LEAVE(); |
903 | |||
1117 | serge | 904 | return 0; |
905 | |||
906 | err_g4: |
||
907 | // drm_put_minor(&dev->primary); |
||
908 | //err_g3: |
||
909 | // if (drm_core_check_feature(dev, DRIVER_MODESET)) |
||
910 | // drm_put_minor(&dev->control); |
||
911 | //err_g2: |
||
912 | // pci_disable_device(pdev); |
||
913 | //err_g1: |
||
914 | free(dev); |
||
915 | |||
1221 | serge | 916 | LEAVE(); |
917 | |||
1117 | serge | 918 | return ret; |
919 | } |
||
920 | |||
921 | resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource) |
||
922 | { |
||
923 | return pci_resource_start(dev->pdev, resource); |
||
924 | } |
||
925 | |||
926 | resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource) |
||
927 | { |
||
928 | return pci_resource_len(dev->pdev, resource); |
||
929 | } |
||
930 | |||
1123 | serge | 931 | |
932 | uint32_t __div64_32(uint64_t *n, uint32_t base) |
||
933 | { |
||
934 | uint64_t rem = *n; |
||
935 | uint64_t b = base; |
||
936 | uint64_t res, d = 1; |
||
937 | uint32_t high = rem >> 32; |
||
938 | |||
939 | /* Reduce the thing a bit first */ |
||
940 | res = 0; |
||
941 | if (high >= base) { |
||
942 | high /= base; |
||
943 | res = (uint64_t) high << 32; |
||
944 | rem -= (uint64_t) (high*base) << 32; |
||
945 | } |
||
946 | |||
947 | while ((int64_t)b > 0 && b < rem) { |
||
948 | b = b+b; |
||
949 | d = d+d; |
||
950 | } |
||
951 | |||
952 | do { |
||
953 | if (rem >= b) { |
||
954 | rem -= b; |
||
955 | res += d; |
||
956 | } |
||
957 | b >>= 1; |
||
958 | d >>= 1; |
||
959 | } while (d); |
||
960 | |||
961 | *n = res; |
||
962 | return rem; |
||
963 | } |
||
964 | |||
1239 | serge | 965 | |
966 | static struct pci_device_id pciidlist[] = { |
||
967 | radeon_PCI_IDS |
||
968 | }; |
||
969 | |||
970 | |||
971 | #define API_VERSION 0x01000100 |
||
972 | |||
973 | #define SRV_GETVERSION 0 |
||
974 | #define SRV_ENUM_MODES 1 |
||
975 | #define SRV_SET_MODE 2 |
||
976 | |||
2007 | serge | 977 | #define SRV_CREATE_VIDEO 9 |
978 | #define SRV_BLIT_VIDEO 10 |
||
979 | |||
980 | int r600_video_blit(uint64_t src_offset, int x, int y, |
||
981 | int w, int h, int pitch); |
||
982 | |||
1239 | serge | 983 | int _stdcall display_handler(ioctl_t *io) |
984 | { |
||
985 | int retval = -1; |
||
986 | u32_t *inp; |
||
987 | u32_t *outp; |
||
988 | |||
989 | inp = io->input; |
||
990 | outp = io->output; |
||
991 | |||
992 | switch(io->io_code) |
||
993 | { |
||
994 | case SRV_GETVERSION: |
||
995 | if(io->out_size==4) |
||
996 | { |
||
997 | *outp = API_VERSION; |
||
998 | retval = 0; |
||
999 | } |
||
1000 | break; |
||
1001 | |||
1002 | case SRV_ENUM_MODES: |
||
1003 | dbgprintf("SRV_ENUM_MODES inp %x inp_size %x out_size %x\n", |
||
1004 | inp, io->inp_size, io->out_size ); |
||
1005 | |||
1246 | serge | 1006 | if( radeon_modeset && |
1007 | (outp != NULL) && (io->out_size == 4) && |
||
1404 | serge | 1008 | (io->inp_size == *outp * sizeof(videomode_t)) ) |
1268 | serge | 1009 | { |
1404 | serge | 1010 | retval = get_modes((videomode_t*)inp, outp); |
1239 | serge | 1011 | }; |
1012 | break; |
||
1013 | |||
1014 | case SRV_SET_MODE: |
||
1246 | serge | 1015 | dbgprintf("SRV_SET_MODE inp %x inp_size %x\n", |
1016 | inp, io->inp_size); |
||
1017 | |||
1018 | if( radeon_modeset && |
||
1019 | (inp != NULL) && |
||
1404 | serge | 1020 | (io->inp_size == sizeof(videomode_t)) ) |
1239 | serge | 1021 | { |
1404 | serge | 1022 | retval = set_user_mode((videomode_t*)inp); |
1239 | serge | 1023 | }; |
1024 | break; |
||
2007 | serge | 1025 | |
1026 | case SRV_CREATE_VIDEO: |
||
1027 | retval = r600_create_video(inp[0], inp[1], outp); |
||
1028 | break; |
||
1029 | |||
1030 | case SRV_BLIT_VIDEO: |
||
1031 | r600_video_blit( ((uint64_t*)inp)[0], inp[2], inp[3], |
||
1032 | inp[4], inp[5], inp[6]); |
||
1033 | |||
1034 | retval = 0; |
||
1035 | break; |
||
1036 | |||
1239 | serge | 1037 | }; |
1038 | |||
1039 | return retval; |
||
1040 | } |
||
1041 | |||
1246 | serge | 1042 | static char log[256]; |
1404 | serge | 1043 | static pci_dev_t device; |
1246 | serge | 1044 | |
1963 | serge | 1045 | u32_t drvEntry(int action, char *cmdline) |
1239 | serge | 1046 | { |
1428 | serge | 1047 | struct radeon_device *rdev = NULL; |
1048 | |||
1239 | serge | 1049 | struct pci_device_id *ent; |
1050 | |||
1051 | int err; |
||
1052 | u32_t retval = 0; |
||
1053 | |||
1054 | if(action != 1) |
||
1055 | return 0; |
||
1056 | |||
1057 | if( GetService("DISPLAY") != 0 ) |
||
1058 | return 0; |
||
1059 | |||
1060 | if( cmdline && *cmdline ) |
||
1268 | serge | 1061 | parse_cmdline(cmdline, &usermode, log, &radeon_modeset); |
1239 | serge | 1062 | |
1063 | if(!dbg_open(log)) |
||
1064 | { |
||
1990 | serge | 1065 | strcpy(log, "/RD/1/DRIVERS/atikms.log"); |
1239 | serge | 1066 | |
1067 | if(!dbg_open(log)) |
||
1068 | { |
||
1069 | printf("Can't open %s\nExit\n", log); |
||
1070 | return 0; |
||
1071 | }; |
||
1072 | } |
||
1963 | serge | 1073 | dbgprintf("Radeon RC11 cmdline %s\n", cmdline); |
1239 | serge | 1074 | |
1075 | enum_pci_devices(); |
||
1963 | serge | 1076 | |
1239 | serge | 1077 | ent = find_pci_device(&device, pciidlist); |
1078 | |||
1079 | if( unlikely(ent == NULL) ) |
||
1080 | { |
||
1081 | dbgprintf("device not found\n"); |
||
1082 | return 0; |
||
1083 | }; |
||
1084 | |||
1085 | dbgprintf("device %x:%x\n", device.pci_dev.vendor, |
||
1086 | device.pci_dev.device); |
||
1087 | |||
1088 | err = drm_get_dev(&device.pci_dev, ent); |
||
1089 | |||
1428 | serge | 1090 | rdev = rdisplay->ddev->dev_private; |
1091 | |||
1246 | serge | 1092 | err = RegService("DISPLAY", display_handler); |
1239 | serge | 1093 | |
1246 | serge | 1094 | if( err != 0) |
1095 | dbgprintf("Set DISPLAY handler\n"); |
||
1096 | |||
1097 | return err; |
||
1239 | serge | 1098 | }; |
1430 | serge | 1099 | |
1100 | void drm_vblank_post_modeset(struct drm_device *dev, int crtc) |
||
1101 | {}; |
||
1102 | |||
1103 | void drm_vblank_pre_modeset(struct drm_device *dev, int crtc) |
||
1104 | {};>><>><>><>=>>>>>>> |
||
1105 |