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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | //#include |
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1123 | serge | 29 | |
1179 | serge | 30 | #include |
31 | #include |
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1221 | serge | 32 | #include |
1117 | serge | 33 | #include "radeon_reg.h" |
34 | #include "radeon.h" |
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35 | #include "radeon_asic.h" |
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36 | #include "atom.h" |
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37 | |||
1221 | serge | 38 | #include |
39 | |||
1117 | serge | 40 | #include |
41 | |||
42 | int radeon_dynclks = -1; |
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1123 | serge | 43 | int radeon_r4xx_atom = 0; |
1125 | serge | 44 | int radeon_agpmode = -1; |
1117 | serge | 45 | int radeon_gart_size = 512; /* default gart size */ |
1123 | serge | 46 | int radeon_benchmarking = 0; |
47 | int radeon_connector_table = 0; |
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1222 | serge | 48 | int radeon_tv = 0; |
1117 | serge | 49 | |
1230 | serge | 50 | int pre_init_display(struct radeon_device *rdev); |
51 | int post_init_display(struct radeon_device *rdev); |
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1117 | serge | 52 | |
53 | /* |
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54 | * Clear GPU surface registers. |
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55 | */ |
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1179 | serge | 56 | void radeon_surface_init(struct radeon_device *rdev) |
1117 | serge | 57 | { |
1179 | serge | 58 | ENTER(); |
1117 | serge | 59 | |
60 | /* FIXME: check this out */ |
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61 | if (rdev->family < CHIP_R600) { |
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62 | int i; |
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63 | |||
64 | for (i = 0; i < 8; i++) { |
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65 | WREG32(RADEON_SURFACE0_INFO + |
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66 | i * (RADEON_SURFACE1_INFO - RADEON_SURFACE0_INFO), |
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67 | 0); |
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68 | } |
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1179 | serge | 69 | /* enable surfaces */ |
70 | WREG32(RADEON_SURFACE_CNTL, 0); |
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1117 | serge | 71 | } |
72 | } |
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73 | |||
74 | /* |
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75 | * GPU scratch registers helpers function. |
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76 | */ |
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1179 | serge | 77 | void radeon_scratch_init(struct radeon_device *rdev) |
1117 | serge | 78 | { |
79 | int i; |
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80 | |||
81 | /* FIXME: check this out */ |
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82 | if (rdev->family < CHIP_R300) { |
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83 | rdev->scratch.num_reg = 5; |
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84 | } else { |
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85 | rdev->scratch.num_reg = 7; |
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86 | } |
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87 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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88 | rdev->scratch.free[i] = true; |
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89 | rdev->scratch.reg[i] = RADEON_SCRATCH_REG0 + (i * 4); |
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90 | } |
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91 | } |
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92 | |||
93 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg) |
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94 | { |
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95 | int i; |
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96 | |||
97 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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98 | if (rdev->scratch.free[i]) { |
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99 | rdev->scratch.free[i] = false; |
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100 | *reg = rdev->scratch.reg[i]; |
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101 | return 0; |
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102 | } |
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103 | } |
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104 | return -EINVAL; |
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105 | } |
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106 | |||
107 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg) |
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108 | { |
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109 | int i; |
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110 | |||
111 | for (i = 0; i < rdev->scratch.num_reg; i++) { |
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112 | if (rdev->scratch.reg[i] == reg) { |
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113 | rdev->scratch.free[i] = true; |
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114 | return; |
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115 | } |
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116 | } |
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117 | } |
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118 | |||
119 | /* |
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120 | * MC common functions |
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121 | */ |
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122 | int radeon_mc_setup(struct radeon_device *rdev) |
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123 | { |
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124 | uint32_t tmp; |
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125 | |||
126 | /* Some chips have an "issue" with the memory controller, the |
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127 | * location must be aligned to the size. We just align it down, |
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128 | * too bad if we walk over the top of system memory, we don't |
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129 | * use DMA without a remapped anyway. |
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130 | * Affected chips are rv280, all r3xx, and all r4xx, but not IGP |
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131 | */ |
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132 | /* FGLRX seems to setup like this, VRAM a 0, then GART. |
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133 | */ |
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1126 | serge | 134 | /* |
1117 | serge | 135 | * Note: from R6xx the address space is 40bits but here we only |
136 | * use 32bits (still have to see a card which would exhaust 4G |
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137 | * address space). |
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138 | */ |
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139 | if (rdev->mc.vram_location != 0xFFFFFFFFUL) { |
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140 | /* vram location was already setup try to put gtt after |
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141 | * if it fits */ |
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1179 | serge | 142 | tmp = rdev->mc.vram_location + rdev->mc.mc_vram_size; |
1117 | serge | 143 | tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); |
144 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.gtt_size) { |
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145 | rdev->mc.gtt_location = tmp; |
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146 | } else { |
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147 | if (rdev->mc.gtt_size >= rdev->mc.vram_location) { |
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148 | printk(KERN_ERR "[drm] GTT too big to fit " |
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149 | "before or after vram location.\n"); |
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150 | return -EINVAL; |
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151 | } |
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152 | rdev->mc.gtt_location = 0; |
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153 | } |
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154 | } else if (rdev->mc.gtt_location != 0xFFFFFFFFUL) { |
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155 | /* gtt location was already setup try to put vram before |
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156 | * if it fits */ |
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1179 | serge | 157 | if (rdev->mc.mc_vram_size < rdev->mc.gtt_location) { |
1117 | serge | 158 | rdev->mc.vram_location = 0; |
159 | } else { |
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160 | tmp = rdev->mc.gtt_location + rdev->mc.gtt_size; |
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1179 | serge | 161 | tmp += (rdev->mc.mc_vram_size - 1); |
162 | tmp &= ~(rdev->mc.mc_vram_size - 1); |
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163 | if ((0xFFFFFFFFUL - tmp) >= rdev->mc.mc_vram_size) { |
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1117 | serge | 164 | rdev->mc.vram_location = tmp; |
165 | } else { |
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166 | printk(KERN_ERR "[drm] vram too big to fit " |
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167 | "before or after GTT location.\n"); |
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168 | return -EINVAL; |
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169 | } |
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170 | } |
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171 | } else { |
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172 | rdev->mc.vram_location = 0; |
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1179 | serge | 173 | tmp = rdev->mc.mc_vram_size; |
174 | tmp = (tmp + rdev->mc.gtt_size - 1) & ~(rdev->mc.gtt_size - 1); |
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175 | rdev->mc.gtt_location = tmp; |
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1117 | serge | 176 | } |
1179 | serge | 177 | rdev->mc.vram_start = rdev->mc.vram_location; |
178 | rdev->mc.vram_end = rdev->mc.vram_location + rdev->mc.mc_vram_size - 1; |
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179 | rdev->mc.gtt_start = rdev->mc.gtt_location; |
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180 | rdev->mc.gtt_end = rdev->mc.gtt_location + rdev->mc.gtt_size - 1; |
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181 | DRM_INFO("radeon: VRAM %uM\n", (unsigned)(rdev->mc.mc_vram_size >> 20)); |
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1117 | serge | 182 | DRM_INFO("radeon: VRAM from 0x%08X to 0x%08X\n", |
1179 | serge | 183 | (unsigned)rdev->mc.vram_location, |
184 | (unsigned)(rdev->mc.vram_location + rdev->mc.mc_vram_size - 1)); |
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185 | DRM_INFO("radeon: GTT %uM\n", (unsigned)(rdev->mc.gtt_size >> 20)); |
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1117 | serge | 186 | DRM_INFO("radeon: GTT from 0x%08X to 0x%08X\n", |
1179 | serge | 187 | (unsigned)rdev->mc.gtt_location, |
188 | (unsigned)(rdev->mc.gtt_location + rdev->mc.gtt_size - 1)); |
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1117 | serge | 189 | return 0; |
190 | } |
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191 | |||
192 | |||
193 | /* |
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194 | * GPU helpers function. |
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195 | */ |
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1179 | serge | 196 | bool radeon_card_posted(struct radeon_device *rdev) |
1117 | serge | 197 | { |
198 | uint32_t reg; |
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199 | |||
1179 | serge | 200 | ENTER(); |
1117 | serge | 201 | |
202 | /* first check CRTCs */ |
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203 | if (ASIC_IS_AVIVO(rdev)) { |
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204 | reg = RREG32(AVIVO_D1CRTC_CONTROL) | |
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205 | RREG32(AVIVO_D2CRTC_CONTROL); |
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206 | if (reg & AVIVO_CRTC_EN) { |
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207 | return true; |
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208 | } |
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209 | } else { |
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210 | reg = RREG32(RADEON_CRTC_GEN_CNTL) | |
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211 | RREG32(RADEON_CRTC2_GEN_CNTL); |
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212 | if (reg & RADEON_CRTC_EN) { |
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213 | return true; |
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214 | } |
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215 | } |
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216 | |||
217 | /* then check MEM_SIZE, in case the crtcs are off */ |
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218 | if (rdev->family >= CHIP_R600) |
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219 | reg = RREG32(R600_CONFIG_MEMSIZE); |
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220 | else |
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221 | reg = RREG32(RADEON_CONFIG_MEMSIZE); |
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222 | |||
223 | if (reg) |
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224 | return true; |
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225 | |||
226 | return false; |
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227 | |||
228 | } |
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229 | |||
230 | |||
231 | /* |
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232 | * Registers accessors functions. |
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233 | */ |
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234 | uint32_t radeon_invalid_rreg(struct radeon_device *rdev, uint32_t reg) |
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235 | { |
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236 | DRM_ERROR("Invalid callback to read register 0x%04X\n", reg); |
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237 | BUG_ON(1); |
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238 | return 0; |
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239 | } |
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240 | |||
241 | void radeon_invalid_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
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242 | { |
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243 | DRM_ERROR("Invalid callback to write register 0x%04X with 0x%08X\n", |
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244 | reg, v); |
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245 | BUG_ON(1); |
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246 | } |
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247 | |||
248 | void radeon_register_accessor_init(struct radeon_device *rdev) |
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249 | { |
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250 | rdev->mc_rreg = &radeon_invalid_rreg; |
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251 | rdev->mc_wreg = &radeon_invalid_wreg; |
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252 | rdev->pll_rreg = &radeon_invalid_rreg; |
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253 | rdev->pll_wreg = &radeon_invalid_wreg; |
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254 | rdev->pciep_rreg = &radeon_invalid_rreg; |
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255 | rdev->pciep_wreg = &radeon_invalid_wreg; |
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256 | |||
257 | /* Don't change order as we are overridding accessor. */ |
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258 | if (rdev->family < CHIP_RV515) { |
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1179 | serge | 259 | rdev->pcie_reg_mask = 0xff; |
260 | } else { |
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261 | rdev->pcie_reg_mask = 0x7ff; |
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1117 | serge | 262 | } |
263 | /* FIXME: not sure here */ |
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264 | if (rdev->family <= CHIP_R580) { |
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1119 | serge | 265 | rdev->pll_rreg = &r100_pll_rreg; |
266 | rdev->pll_wreg = &r100_pll_wreg; |
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1117 | serge | 267 | } |
1179 | serge | 268 | if (rdev->family >= CHIP_R420) { |
269 | rdev->mc_rreg = &r420_mc_rreg; |
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270 | rdev->mc_wreg = &r420_mc_wreg; |
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271 | } |
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1117 | serge | 272 | if (rdev->family >= CHIP_RV515) { |
273 | rdev->mc_rreg = &rv515_mc_rreg; |
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274 | rdev->mc_wreg = &rv515_mc_wreg; |
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275 | } |
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276 | if (rdev->family == CHIP_RS400 || rdev->family == CHIP_RS480) { |
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1128 | serge | 277 | rdev->mc_rreg = &rs400_mc_rreg; |
278 | rdev->mc_wreg = &rs400_mc_wreg; |
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1117 | serge | 279 | } |
1221 | serge | 280 | if (rdev->family == CHIP_RS690 || rdev->family == CHIP_RS740) { |
281 | rdev->mc_rreg = &rs690_mc_rreg; |
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282 | rdev->mc_wreg = &rs690_mc_wreg; |
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283 | } |
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284 | if (rdev->family == CHIP_RS600) { |
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285 | rdev->mc_rreg = &rs600_mc_rreg; |
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286 | rdev->mc_wreg = &rs600_mc_wreg; |
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287 | } |
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1179 | serge | 288 | // if (rdev->family >= CHIP_R600) { |
289 | // rdev->pciep_rreg = &r600_pciep_rreg; |
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290 | // rdev->pciep_wreg = &r600_pciep_wreg; |
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291 | // } |
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1117 | serge | 292 | } |
293 | |||
294 | |||
295 | /* |
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296 | * ASIC |
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297 | */ |
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298 | int radeon_asic_init(struct radeon_device *rdev) |
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299 | { |
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300 | radeon_register_accessor_init(rdev); |
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301 | switch (rdev->family) { |
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302 | case CHIP_R100: |
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303 | case CHIP_RV100: |
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304 | case CHIP_RS100: |
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305 | case CHIP_RV200: |
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306 | case CHIP_RS200: |
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307 | case CHIP_R200: |
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308 | case CHIP_RV250: |
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309 | case CHIP_RS300: |
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310 | case CHIP_RV280: |
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1128 | serge | 311 | rdev->asic = &r100_asic; |
1117 | serge | 312 | break; |
313 | case CHIP_R300: |
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314 | case CHIP_R350: |
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315 | case CHIP_RV350: |
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316 | case CHIP_RV380: |
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1128 | serge | 317 | rdev->asic = &r300_asic; |
1179 | serge | 318 | if (rdev->flags & RADEON_IS_PCIE) { |
319 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
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320 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
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321 | } |
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1117 | serge | 322 | break; |
323 | case CHIP_R420: |
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324 | case CHIP_R423: |
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325 | case CHIP_RV410: |
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1128 | serge | 326 | rdev->asic = &r420_asic; |
1117 | serge | 327 | break; |
328 | case CHIP_RS400: |
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329 | case CHIP_RS480: |
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1128 | serge | 330 | rdev->asic = &rs400_asic; |
1117 | serge | 331 | break; |
332 | case CHIP_RS600: |
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1221 | serge | 333 | rdev->asic = &rs600_asic; |
1117 | serge | 334 | break; |
335 | case CHIP_RS690: |
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336 | case CHIP_RS740: |
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1221 | serge | 337 | rdev->asic = &rs690_asic; |
1117 | serge | 338 | break; |
339 | case CHIP_RV515: |
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1128 | serge | 340 | rdev->asic = &rv515_asic; |
1117 | serge | 341 | break; |
342 | case CHIP_R520: |
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343 | case CHIP_RV530: |
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344 | case CHIP_RV560: |
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345 | case CHIP_RV570: |
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346 | case CHIP_R580: |
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347 | rdev->asic = &r520_asic; |
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348 | break; |
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349 | case CHIP_R600: |
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350 | case CHIP_RV610: |
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351 | case CHIP_RV630: |
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352 | case CHIP_RV620: |
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353 | case CHIP_RV635: |
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354 | case CHIP_RV670: |
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355 | case CHIP_RS780: |
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1221 | serge | 356 | case CHIP_RS880: |
357 | // rdev->asic = &r600_asic; |
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358 | break; |
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1117 | serge | 359 | case CHIP_RV770: |
360 | case CHIP_RV730: |
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361 | case CHIP_RV710: |
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1221 | serge | 362 | case CHIP_RV740: |
363 | // rdev->asic = &rv770_asic; |
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364 | break; |
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1117 | serge | 365 | default: |
366 | /* FIXME: not supported yet */ |
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367 | return -EINVAL; |
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368 | } |
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369 | return 0; |
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370 | } |
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371 | |||
372 | |||
373 | /* |
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374 | * Wrapper around modesetting bits. |
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375 | */ |
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376 | int radeon_clocks_init(struct radeon_device *rdev) |
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377 | { |
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378 | int r; |
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379 | |||
1179 | serge | 380 | ENTER(); |
1117 | serge | 381 | |
382 | r = radeon_static_clocks_init(rdev->ddev); |
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383 | if (r) { |
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384 | return r; |
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385 | } |
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386 | DRM_INFO("Clocks initialized !\n"); |
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387 | return 0; |
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388 | } |
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389 | |||
390 | void radeon_clocks_fini(struct radeon_device *rdev) |
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391 | { |
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392 | } |
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393 | |||
394 | /* ATOM accessor methods */ |
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395 | static uint32_t cail_pll_read(struct card_info *info, uint32_t reg) |
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396 | { |
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397 | struct radeon_device *rdev = info->dev->dev_private; |
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398 | uint32_t r; |
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399 | |||
400 | r = rdev->pll_rreg(rdev, reg); |
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401 | return r; |
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402 | } |
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403 | |||
404 | static void cail_pll_write(struct card_info *info, uint32_t reg, uint32_t val) |
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405 | { |
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406 | struct radeon_device *rdev = info->dev->dev_private; |
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407 | |||
408 | rdev->pll_wreg(rdev, reg, val); |
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409 | } |
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410 | |||
411 | static uint32_t cail_mc_read(struct card_info *info, uint32_t reg) |
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412 | { |
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413 | struct radeon_device *rdev = info->dev->dev_private; |
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414 | uint32_t r; |
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415 | |||
416 | r = rdev->mc_rreg(rdev, reg); |
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417 | return r; |
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418 | } |
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419 | |||
420 | static void cail_mc_write(struct card_info *info, uint32_t reg, uint32_t val) |
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421 | { |
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422 | struct radeon_device *rdev = info->dev->dev_private; |
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423 | |||
424 | rdev->mc_wreg(rdev, reg, val); |
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425 | } |
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426 | |||
427 | static void cail_reg_write(struct card_info *info, uint32_t reg, uint32_t val) |
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428 | { |
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429 | struct radeon_device *rdev = info->dev->dev_private; |
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430 | |||
431 | WREG32(reg*4, val); |
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432 | } |
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433 | |||
434 | static uint32_t cail_reg_read(struct card_info *info, uint32_t reg) |
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435 | { |
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436 | struct radeon_device *rdev = info->dev->dev_private; |
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437 | uint32_t r; |
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438 | |||
439 | r = RREG32(reg*4); |
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440 | return r; |
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441 | } |
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442 | |||
443 | static struct card_info atom_card_info = { |
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444 | .dev = NULL, |
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445 | .reg_read = cail_reg_read, |
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446 | .reg_write = cail_reg_write, |
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447 | .mc_read = cail_mc_read, |
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448 | .mc_write = cail_mc_write, |
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449 | .pll_read = cail_pll_read, |
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450 | .pll_write = cail_pll_write, |
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451 | }; |
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452 | |||
453 | int radeon_atombios_init(struct radeon_device *rdev) |
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454 | { |
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1179 | serge | 455 | ENTER(); |
1117 | serge | 456 | |
457 | atom_card_info.dev = rdev->ddev; |
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458 | rdev->mode_info.atom_context = atom_parse(&atom_card_info, rdev->bios); |
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459 | radeon_atom_initialize_bios_scratch_regs(rdev->ddev); |
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460 | return 0; |
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461 | } |
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462 | |||
463 | void radeon_atombios_fini(struct radeon_device *rdev) |
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464 | { |
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1119 | serge | 465 | kfree(rdev->mode_info.atom_context); |
1117 | serge | 466 | } |
467 | |||
468 | int radeon_combios_init(struct radeon_device *rdev) |
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469 | { |
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1128 | serge | 470 | radeon_combios_initialize_bios_scratch_regs(rdev->ddev); |
1117 | serge | 471 | return 0; |
472 | } |
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473 | |||
474 | void radeon_combios_fini(struct radeon_device *rdev) |
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475 | { |
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476 | } |
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477 | |||
478 | int radeon_modeset_init(struct radeon_device *rdev); |
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479 | void radeon_modeset_fini(struct radeon_device *rdev); |
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480 | |||
1221 | serge | 481 | void radeon_agp_disable(struct radeon_device *rdev) |
482 | { |
||
483 | rdev->flags &= ~RADEON_IS_AGP; |
||
484 | if (rdev->family >= CHIP_R600) { |
||
485 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
||
486 | rdev->flags |= RADEON_IS_PCIE; |
||
487 | } else if (rdev->family >= CHIP_RV515 || |
||
488 | rdev->family == CHIP_RV380 || |
||
489 | rdev->family == CHIP_RV410 || |
||
490 | rdev->family == CHIP_R423) { |
||
491 | DRM_INFO("Forcing AGP to PCIE mode\n"); |
||
492 | rdev->flags |= RADEON_IS_PCIE; |
||
493 | rdev->asic->gart_tlb_flush = &rv370_pcie_gart_tlb_flush; |
||
494 | rdev->asic->gart_set_page = &rv370_pcie_gart_set_page; |
||
495 | } else { |
||
496 | DRM_INFO("Forcing AGP to PCI mode\n"); |
||
497 | rdev->flags |= RADEON_IS_PCI; |
||
498 | rdev->asic->gart_tlb_flush = &r100_pci_gart_tlb_flush; |
||
499 | rdev->asic->gart_set_page = &r100_pci_gart_set_page; |
||
500 | } |
||
501 | } |
||
1179 | serge | 502 | |
1117 | serge | 503 | /* |
504 | * Radeon device. |
||
505 | */ |
||
506 | int radeon_device_init(struct radeon_device *rdev, |
||
507 | struct drm_device *ddev, |
||
508 | struct pci_dev *pdev, |
||
509 | uint32_t flags) |
||
510 | { |
||
1221 | serge | 511 | int r; |
1179 | serge | 512 | int dma_bits; |
1117 | serge | 513 | |
1179 | serge | 514 | ENTER(); |
1117 | serge | 515 | |
516 | DRM_INFO("radeon: Initializing kernel modesetting.\n"); |
||
517 | rdev->shutdown = false; |
||
518 | rdev->ddev = ddev; |
||
519 | rdev->pdev = pdev; |
||
520 | rdev->flags = flags; |
||
521 | rdev->family = flags & RADEON_FAMILY_MASK; |
||
522 | rdev->is_atom_bios = false; |
||
523 | rdev->usec_timeout = RADEON_MAX_USEC_TIMEOUT; |
||
524 | rdev->mc.gtt_size = radeon_gart_size * 1024 * 1024; |
||
525 | rdev->gpu_lockup = false; |
||
1221 | serge | 526 | rdev->accel_working = false; |
1117 | serge | 527 | /* mutex initialization are all done here so we |
528 | * can recall function without having locking issues */ |
||
529 | // mutex_init(&rdev->cs_mutex); |
||
530 | // mutex_init(&rdev->ib_pool.mutex); |
||
531 | // mutex_init(&rdev->cp.mutex); |
||
532 | // rwlock_init(&rdev->fence_drv.lock); |
||
533 | |||
1179 | serge | 534 | /* Set asic functions */ |
535 | r = radeon_asic_init(rdev); |
||
536 | if (r) { |
||
537 | return r; |
||
538 | } |
||
539 | |||
1117 | serge | 540 | if (radeon_agpmode == -1) { |
1221 | serge | 541 | radeon_agp_disable(rdev); |
1117 | serge | 542 | } |
543 | |||
1179 | serge | 544 | /* set DMA mask + need_dma32 flags. |
545 | * PCIE - can handle 40-bits. |
||
546 | * IGP - can handle 40-bits (in theory) |
||
547 | * AGP - generally dma32 is safest |
||
548 | * PCI - only dma32 |
||
549 | */ |
||
550 | rdev->need_dma32 = false; |
||
551 | if (rdev->flags & RADEON_IS_AGP) |
||
552 | rdev->need_dma32 = true; |
||
553 | if (rdev->flags & RADEON_IS_PCI) |
||
554 | rdev->need_dma32 = true; |
||
1117 | serge | 555 | |
1179 | serge | 556 | dma_bits = rdev->need_dma32 ? 32 : 40; |
557 | r = pci_set_dma_mask(rdev->pdev, DMA_BIT_MASK(dma_bits)); |
||
1117 | serge | 558 | if (r) { |
1119 | serge | 559 | printk(KERN_WARNING "radeon: No suitable DMA available.\n"); |
560 | } |
||
1117 | serge | 561 | |
562 | /* Registers mapping */ |
||
563 | /* TODO: block userspace mapping of io register */ |
||
564 | rdev->rmmio_base = pci_resource_start(rdev->pdev, 2); |
||
565 | |||
566 | rdev->rmmio_size = pci_resource_len(rdev->pdev, 2); |
||
567 | |||
568 | rdev->rmmio = (void*)MapIoMem(rdev->rmmio_base, rdev->rmmio_size, |
||
569 | PG_SW+PG_NOCACHE); |
||
570 | |||
571 | if (rdev->rmmio == NULL) { |
||
572 | return -ENOMEM; |
||
573 | } |
||
574 | DRM_INFO("register mmio base: 0x%08X\n", (uint32_t)rdev->rmmio_base); |
||
575 | DRM_INFO("register mmio size: %u\n", (unsigned)rdev->rmmio_size); |
||
576 | |||
1221 | serge | 577 | /* if we have > 1 VGA cards, then disable the radeon VGA resources */ |
578 | // r = vga_client_register(rdev->pdev, rdev, NULL, radeon_vga_set_decode); |
||
579 | // if (r) { |
||
580 | // return -EINVAL; |
||
581 | // } |
||
582 | |||
1179 | serge | 583 | r = radeon_init(rdev); |
1221 | serge | 584 | if (r) |
1117 | serge | 585 | return r; |
586 | |||
1221 | serge | 587 | if (rdev->flags & RADEON_IS_AGP && !rdev->accel_working) { |
588 | /* Acceleration not working on AGP card try again |
||
589 | * with fallback to PCI or PCIE GART |
||
590 | */ |
||
591 | radeon_gpu_reset(rdev); |
||
592 | radeon_fini(rdev); |
||
593 | radeon_agp_disable(rdev); |
||
594 | r = radeon_init(rdev); |
||
595 | if (r) |
||
1179 | serge | 596 | return r; |
1126 | serge | 597 | } |
1179 | serge | 598 | // if (radeon_testing) { |
599 | // radeon_test_moves(rdev); |
||
1125 | serge | 600 | // } |
1179 | serge | 601 | // if (radeon_benchmarking) { |
602 | // radeon_benchmark(rdev); |
||
603 | // } |
||
604 | return 0; |
||
1117 | serge | 605 | } |
606 | |||
1179 | serge | 607 | |
1117 | serge | 608 | static struct pci_device_id pciidlist[] = { |
609 | radeon_PCI_IDS |
||
610 | }; |
||
611 | |||
612 | |||
1179 | serge | 613 | u32_t drvEntry(int action, char *cmdline) |
1117 | serge | 614 | { |
615 | struct pci_device_id *ent; |
||
616 | |||
617 | dev_t device; |
||
618 | int err; |
||
619 | u32_t retval = 0; |
||
620 | |||
621 | if(action != 1) |
||
622 | return 0; |
||
623 | |||
1120 | serge | 624 | if(!dbg_open("/hd0/2/atikms.log")) |
1117 | serge | 625 | { |
1120 | serge | 626 | printf("Can't open /hd0/2/atikms.log\nExit\n"); |
1117 | serge | 627 | return 0; |
628 | } |
||
629 | |||
1179 | serge | 630 | if(cmdline) |
631 | dbgprintf("cmdline: %s\n", cmdline); |
||
632 | |||
1117 | serge | 633 | enum_pci_devices(); |
634 | |||
635 | ent = find_pci_device(&device, pciidlist); |
||
636 | |||
637 | if( unlikely(ent == NULL) ) |
||
638 | { |
||
639 | dbgprintf("device not found\n"); |
||
640 | return 0; |
||
641 | }; |
||
642 | |||
643 | dbgprintf("device %x:%x\n", device.pci_dev.vendor, |
||
644 | device.pci_dev.device); |
||
645 | |||
646 | err = drm_get_dev(&device.pci_dev, ent); |
||
647 | |||
648 | return retval; |
||
649 | }; |
||
650 | |||
651 | |||
652 | |||
653 | /* |
||
654 | * Driver load/unload |
||
655 | */ |
||
656 | int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags) |
||
657 | { |
||
658 | struct radeon_device *rdev; |
||
659 | int r; |
||
660 | |||
1182 | serge | 661 | ENTER(); |
1117 | serge | 662 | |
1120 | serge | 663 | rdev = kzalloc(sizeof(struct radeon_device), GFP_KERNEL); |
1117 | serge | 664 | if (rdev == NULL) { |
665 | return -ENOMEM; |
||
666 | }; |
||
667 | |||
668 | dev->dev_private = (void *)rdev; |
||
669 | |||
670 | /* update BUS flag */ |
||
671 | // if (drm_device_is_agp(dev)) { |
||
672 | flags |= RADEON_IS_AGP; |
||
673 | // } else if (drm_device_is_pcie(dev)) { |
||
674 | // flags |= RADEON_IS_PCIE; |
||
675 | // } else { |
||
676 | // flags |= RADEON_IS_PCI; |
||
677 | // } |
||
678 | |||
1182 | serge | 679 | /* radeon_device_init should report only fatal error |
680 | * like memory allocation failure or iomapping failure, |
||
681 | * or memory manager initialization failure, it must |
||
682 | * properly initialize the GPU MC controller and permit |
||
683 | * VRAM allocation |
||
684 | */ |
||
1117 | serge | 685 | r = radeon_device_init(rdev, dev, dev->pdev, flags); |
686 | if (r) { |
||
1182 | serge | 687 | DRM_ERROR("Fatal error while trying to initialize radeon.\n"); |
1117 | serge | 688 | return r; |
689 | } |
||
1182 | serge | 690 | /* Again modeset_init should fail only on fatal error |
691 | * otherwise it should provide enough functionalities |
||
692 | * for shadowfb to run |
||
693 | */ |
||
694 | r = radeon_modeset_init(rdev); |
||
695 | if (r) { |
||
696 | return r; |
||
697 | } |
||
1117 | serge | 698 | return 0; |
699 | } |
||
700 | |||
1230 | serge | 701 | |
1117 | serge | 702 | int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent) |
703 | { |
||
704 | struct drm_device *dev; |
||
705 | int ret; |
||
706 | |||
1221 | serge | 707 | ENTER(); |
1117 | serge | 708 | |
709 | dev = malloc(sizeof(*dev)); |
||
710 | if (!dev) |
||
711 | return -ENOMEM; |
||
712 | |||
713 | // ret = pci_enable_device(pdev); |
||
714 | // if (ret) |
||
715 | // goto err_g1; |
||
716 | |||
717 | // pci_set_master(pdev); |
||
718 | |||
719 | // if ((ret = drm_fill_in_dev(dev, pdev, ent, driver))) { |
||
720 | // printk(KERN_ERR "DRM: Fill_in_dev failed.\n"); |
||
721 | // goto err_g2; |
||
722 | // } |
||
723 | |||
724 | dev->pdev = pdev; |
||
725 | dev->pci_device = pdev->device; |
||
726 | dev->pci_vendor = pdev->vendor; |
||
727 | |||
728 | // if (drm_core_check_feature(dev, DRIVER_MODESET)) { |
||
729 | // pci_set_drvdata(pdev, dev); |
||
730 | // ret = drm_get_minor(dev, &dev->control, DRM_MINOR_CONTROL); |
||
731 | // if (ret) |
||
732 | // goto err_g2; |
||
733 | // } |
||
734 | |||
735 | // if ((ret = drm_get_minor(dev, &dev->primary, DRM_MINOR_LEGACY))) |
||
736 | // goto err_g3; |
||
737 | |||
738 | // if (dev->driver->load) { |
||
739 | // ret = dev->driver->load(dev, ent->driver_data); |
||
740 | // if (ret) |
||
741 | // goto err_g4; |
||
742 | // } |
||
743 | |||
1221 | serge | 744 | ret = radeon_driver_load_kms(dev, ent->driver_data ); |
745 | if (ret) |
||
1117 | serge | 746 | goto err_g4; |
747 | |||
748 | // list_add_tail(&dev->driver_item, &driver->device_list); |
||
749 | |||
750 | // DRM_INFO("Initialized %s %d.%d.%d %s for %s on minor %d\n", |
||
751 | // driver->name, driver->major, driver->minor, driver->patchlevel, |
||
752 | // driver->date, pci_name(pdev), dev->primary->index); |
||
753 | |||
1230 | serge | 754 | pre_init_display(dev->dev_private); |
1221 | serge | 755 | set_mode(dev, 1280, 1024); |
1230 | serge | 756 | post_init_display(dev->dev_private); |
1126 | serge | 757 | |
1221 | serge | 758 | LEAVE(); |
759 | |||
1117 | serge | 760 | return 0; |
761 | |||
762 | err_g4: |
||
763 | // drm_put_minor(&dev->primary); |
||
764 | //err_g3: |
||
765 | // if (drm_core_check_feature(dev, DRIVER_MODESET)) |
||
766 | // drm_put_minor(&dev->control); |
||
767 | //err_g2: |
||
768 | // pci_disable_device(pdev); |
||
769 | //err_g1: |
||
770 | free(dev); |
||
771 | |||
1221 | serge | 772 | LEAVE(); |
773 | |||
1117 | serge | 774 | return ret; |
775 | } |
||
776 | |||
777 | resource_size_t drm_get_resource_start(struct drm_device *dev, unsigned int resource) |
||
778 | { |
||
779 | return pci_resource_start(dev->pdev, resource); |
||
780 | } |
||
781 | |||
782 | resource_size_t drm_get_resource_len(struct drm_device *dev, unsigned int resource) |
||
783 | { |
||
784 | return pci_resource_len(dev->pdev, resource); |
||
785 | } |
||
786 | |||
1123 | serge | 787 | |
788 | uint32_t __div64_32(uint64_t *n, uint32_t base) |
||
789 | { |
||
790 | uint64_t rem = *n; |
||
791 | uint64_t b = base; |
||
792 | uint64_t res, d = 1; |
||
793 | uint32_t high = rem >> 32; |
||
794 | |||
795 | /* Reduce the thing a bit first */ |
||
796 | res = 0; |
||
797 | if (high >= base) { |
||
798 | high /= base; |
||
799 | res = (uint64_t) high << 32; |
||
800 | rem -= (uint64_t) (high*base) << 32; |
||
801 | } |
||
802 | |||
803 | while ((int64_t)b > 0 && b < rem) { |
||
804 | b = b+b; |
||
805 | d = d+d; |
||
806 | } |
||
807 | |||
808 | do { |
||
809 | if (rem >= b) { |
||
810 | rem -= b; |
||
811 | res += d; |
||
812 | } |
||
813 | b >>= 1; |
||
814 | d >>= 1; |
||
815 | } while (d); |
||
816 | |||
817 | *n = res; |
||
818 | return rem; |
||
819 | }>><>><>=>>>>>>>>> |
||
820 |