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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #ifndef __RADEON_H__ |
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29 | #define __RADEON_H__ |
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30 | |||
31 | /* TODO: Here are things that needs to be done : |
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32 | * - surface allocator & initializer : (bit like scratch reg) should |
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33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
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34 | * related to surface |
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35 | * - WB : write back stuff (do it bit like scratch reg things) |
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36 | * - Vblank : look at Jesse's rework and what we should do |
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37 | * - r600/r700: gart & cp |
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38 | * - cs : clean cs ioctl use bitmap & things like that. |
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39 | * - power management stuff |
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40 | * - Barrier in gart code |
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41 | * - Unmappabled vram ? |
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42 | * - TESTING, TESTING, TESTING |
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43 | */ |
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44 | |||
1221 | serge | 45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various |
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47 | * reasons even thought we work hard to make it works on most |
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48 | * configurations. In order to still have a working userspace in such |
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49 | * situation the init path must succeed up to the memory controller |
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50 | * initialization point. Failure before this point are considered as |
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51 | * fatal error. Here is the init callchain : |
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52 | * radeon_device_init perform common structure, mutex initialization |
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53 | * asic_init setup the GPU memory layout and perform all |
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54 | * one time initialization (failure in this |
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55 | * function are considered fatal) |
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56 | * asic_startup setup the GPU acceleration, in order to |
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57 | * follow guideline the first thing this |
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58 | * function should do is setting the GPU |
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59 | * memory controller (only MC setup failure |
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60 | * are considered as fatal) |
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61 | */ |
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62 | |||
1321 | serge | 63 | #include |
2997 | Serge | 64 | #include |
1321 | serge | 65 | #include |
66 | #include |
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2997 | Serge | 67 | #include |
1221 | serge | 68 | |
1321 | serge | 69 | #include |
70 | #include |
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71 | #include |
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72 | #include |
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1221 | serge | 73 | |
2004 | serge | 74 | #include |
1120 | serge | 75 | #include |
1117 | serge | 76 | |
1120 | serge | 77 | #include |
1179 | serge | 78 | |
79 | #include "radeon_family.h" |
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1117 | serge | 80 | #include "radeon_mode.h" |
81 | #include "radeon_reg.h" |
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82 | |||
83 | #include |
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84 | |||
1179 | serge | 85 | /* |
86 | * Modules parameters. |
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87 | */ |
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88 | extern int radeon_no_wb; |
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1123 | serge | 89 | extern int radeon_modeset; |
1117 | serge | 90 | extern int radeon_dynclks; |
1123 | serge | 91 | extern int radeon_r4xx_atom; |
1128 | serge | 92 | extern int radeon_agpmode; |
93 | extern int radeon_vram_limit; |
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1117 | serge | 94 | extern int radeon_gart_size; |
1128 | serge | 95 | extern int radeon_benchmarking; |
1179 | serge | 96 | extern int radeon_testing; |
1123 | serge | 97 | extern int radeon_connector_table; |
1179 | serge | 98 | extern int radeon_tv; |
1403 | serge | 99 | extern int radeon_audio; |
1963 | serge | 100 | extern int radeon_disp_priority; |
101 | extern int radeon_hw_i2c; |
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102 | extern int radeon_pcie_gen2; |
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2997 | Serge | 103 | extern int radeon_msi; |
104 | extern int radeon_lockup_timeout; |
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105 | |||
106 | |||
107 | |||
1430 | serge | 108 | typedef struct pm_message { |
109 | int event; |
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110 | } pm_message_t; |
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111 | |||
1233 | serge | 112 | typedef struct |
113 | { |
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114 | int width; |
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115 | int height; |
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116 | int bpp; |
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117 | int freq; |
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1321 | serge | 118 | }videomode_t; |
1179 | serge | 119 | |
120 | |||
121 | |||
1963 | serge | 122 | static inline u32 ioread32(const volatile void __iomem *addr) |
123 | { |
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124 | return in32((u32)addr); |
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125 | } |
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126 | |||
127 | static inline void iowrite32(uint32_t b, volatile void __iomem *addr) |
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128 | { |
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129 | out32((u32)addr, b); |
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130 | } |
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131 | |||
2997 | Serge | 132 | //struct __wait_queue_head { |
133 | // spinlock_t lock; |
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134 | // struct list_head task_list; |
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135 | //}; |
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136 | //typedef struct __wait_queue_head wait_queue_head_t; |
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1963 | serge | 137 | |
138 | |||
1117 | serge | 139 | /* |
140 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
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141 | * symbol; |
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142 | */ |
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1120 | serge | 143 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
1963 | serge | 144 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
1428 | serge | 145 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
1120 | serge | 146 | #define RADEON_IB_POOL_SIZE 16 |
2997 | Serge | 147 | #define RADEON_DEBUGFS_MAX_COMPONENTS 32 |
1120 | serge | 148 | #define RADEONFB_CONN_LIMIT 4 |
1179 | serge | 149 | #define RADEON_BIOS_NUM_SCRATCH 8 |
1117 | serge | 150 | |
2997 | Serge | 151 | /* max number of rings */ |
152 | #define RADEON_NUM_RINGS 3 |
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153 | |||
154 | /* fence seq are set to this number when signaled */ |
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155 | #define RADEON_FENCE_SIGNALED_SEQ 0LL |
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156 | |||
157 | /* internal ring indices */ |
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158 | /* r1xx+ has gfx CP ring */ |
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159 | #define RADEON_RING_TYPE_GFX_INDEX 0 |
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160 | |||
161 | /* cayman has 2 compute CP rings */ |
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162 | #define CAYMAN_RING_TYPE_CP1_INDEX 1 |
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163 | #define CAYMAN_RING_TYPE_CP2_INDEX 2 |
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164 | |||
165 | /* hardcode those limit for now */ |
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166 | #define RADEON_VA_IB_OFFSET (1 << 20) |
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167 | #define RADEON_VA_RESERVED_SIZE (8 << 20) |
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168 | #define RADEON_IB_VM_MAX_SIZE (64 << 10) |
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169 | |||
1117 | serge | 170 | /* |
171 | * Errata workarounds. |
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172 | */ |
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173 | enum radeon_pll_errata { |
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174 | CHIP_ERRATA_R300_CG = 0x00000001, |
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175 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
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176 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
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177 | }; |
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178 | |||
179 | |||
180 | struct radeon_device; |
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181 | |||
182 | |||
183 | /* |
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184 | * BIOS. |
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185 | */ |
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186 | bool radeon_get_bios(struct radeon_device *rdev); |
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187 | |||
188 | /* |
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1179 | serge | 189 | * Dummy page |
190 | */ |
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191 | struct radeon_dummy_page { |
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192 | struct page *page; |
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193 | dma_addr_t addr; |
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194 | }; |
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195 | int radeon_dummy_page_init(struct radeon_device *rdev); |
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196 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
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197 | |||
198 | |||
199 | /* |
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1117 | serge | 200 | * Clocks |
201 | */ |
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202 | struct radeon_clock { |
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203 | struct radeon_pll p1pll; |
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204 | struct radeon_pll p2pll; |
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1430 | serge | 205 | struct radeon_pll dcpll; |
1117 | serge | 206 | struct radeon_pll spll; |
207 | struct radeon_pll mpll; |
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208 | /* 10 Khz units */ |
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209 | uint32_t default_mclk; |
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210 | uint32_t default_sclk; |
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1430 | serge | 211 | uint32_t default_dispclk; |
212 | uint32_t dp_extclk; |
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1963 | serge | 213 | uint32_t max_pixel_clock; |
1117 | serge | 214 | }; |
215 | |||
1268 | serge | 216 | /* |
217 | * Power management |
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218 | */ |
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219 | int radeon_pm_init(struct radeon_device *rdev); |
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1963 | serge | 220 | void radeon_pm_fini(struct radeon_device *rdev); |
1430 | serge | 221 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
1963 | serge | 222 | void radeon_pm_suspend(struct radeon_device *rdev); |
223 | void radeon_pm_resume(struct radeon_device *rdev); |
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1430 | serge | 224 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
225 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
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1963 | serge | 226 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
227 | void rs690_pm_info(struct radeon_device *rdev); |
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228 | extern int rv6xx_get_temp(struct radeon_device *rdev); |
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229 | extern int rv770_get_temp(struct radeon_device *rdev); |
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230 | extern int evergreen_get_temp(struct radeon_device *rdev); |
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231 | extern int sumo_get_temp(struct radeon_device *rdev); |
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2997 | Serge | 232 | extern int si_get_temp(struct radeon_device *rdev); |
233 | extern void evergreen_tiling_fields(unsigned tiling_flags, unsigned *bankw, |
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234 | unsigned *bankh, unsigned *mtaspect, |
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235 | unsigned *tile_split); |
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1179 | serge | 236 | |
1117 | serge | 237 | /* |
238 | * Fences. |
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239 | */ |
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240 | struct radeon_fence_driver { |
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241 | uint32_t scratch_reg; |
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2997 | Serge | 242 | uint64_t gpu_addr; |
243 | volatile uint32_t *cpu_addr; |
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244 | /* sync_seq is protected by ring emission lock */ |
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245 | uint64_t sync_seq[RADEON_NUM_RINGS]; |
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246 | atomic64_t last_seq; |
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247 | unsigned long last_activity; |
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1403 | serge | 248 | bool initialized; |
1117 | serge | 249 | }; |
250 | |||
251 | struct radeon_fence { |
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2997 | Serge | 252 | struct radeon_device *rdev; |
253 | struct kref kref; |
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1117 | serge | 254 | /* protected by radeon_fence.lock */ |
2997 | Serge | 255 | uint64_t seq; |
256 | /* RB, DMA, etc. */ |
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257 | unsigned ring; |
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1117 | serge | 258 | }; |
259 | |||
2997 | Serge | 260 | int radeon_fence_driver_start_ring(struct radeon_device *rdev, int ring); |
1117 | serge | 261 | int radeon_fence_driver_init(struct radeon_device *rdev); |
262 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
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2997 | Serge | 263 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence **fence, int ring); |
264 | void radeon_fence_process(struct radeon_device *rdev, int ring); |
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1117 | serge | 265 | bool radeon_fence_signaled(struct radeon_fence *fence); |
266 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
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2997 | Serge | 267 | int radeon_fence_wait_next_locked(struct radeon_device *rdev, int ring); |
268 | void radeon_fence_wait_empty_locked(struct radeon_device *rdev, int ring); |
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269 | int radeon_fence_wait_any(struct radeon_device *rdev, |
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270 | struct radeon_fence **fences, |
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271 | bool intr); |
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1117 | serge | 272 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
273 | void radeon_fence_unref(struct radeon_fence **fence); |
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2997 | Serge | 274 | unsigned radeon_fence_count_emitted(struct radeon_device *rdev, int ring); |
275 | bool radeon_fence_need_sync(struct radeon_fence *fence, int ring); |
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276 | void radeon_fence_note_sync(struct radeon_fence *fence, int ring); |
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277 | static inline struct radeon_fence *radeon_fence_later(struct radeon_fence *a, |
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278 | struct radeon_fence *b) |
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279 | { |
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280 | if (!a) { |
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281 | return b; |
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282 | } |
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1117 | serge | 283 | |
2997 | Serge | 284 | if (!b) { |
285 | return a; |
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286 | } |
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287 | |||
288 | BUG_ON(a->ring != b->ring); |
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289 | |||
290 | if (a->seq > b->seq) { |
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291 | return a; |
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292 | } else { |
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293 | return b; |
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294 | } |
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295 | } |
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296 | |||
297 | static inline bool radeon_fence_is_earlier(struct radeon_fence *a, |
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298 | struct radeon_fence *b) |
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299 | { |
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300 | if (!a) { |
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301 | return false; |
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302 | } |
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303 | |||
304 | if (!b) { |
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305 | return true; |
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306 | } |
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307 | |||
308 | BUG_ON(a->ring != b->ring); |
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309 | |||
310 | return a->seq < b->seq; |
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311 | } |
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312 | |||
1179 | serge | 313 | /* |
314 | * Tiling registers |
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315 | */ |
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316 | struct radeon_surface_reg { |
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1321 | serge | 317 | struct radeon_bo *bo; |
1179 | serge | 318 | }; |
1117 | serge | 319 | |
1179 | serge | 320 | #define RADEON_GEM_MAX_SURFACES 8 |
321 | |||
1117 | serge | 322 | /* |
1321 | serge | 323 | * TTM. |
1117 | serge | 324 | */ |
1321 | serge | 325 | struct radeon_mman { |
326 | struct ttm_bo_global_ref bo_global_ref; |
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1963 | serge | 327 | // struct drm_global_reference mem_global_ref; |
1403 | serge | 328 | struct ttm_bo_device bdev; |
1321 | serge | 329 | bool mem_global_referenced; |
1403 | serge | 330 | bool initialized; |
1321 | serge | 331 | }; |
1117 | serge | 332 | |
2997 | Serge | 333 | /* bo virtual address in a specific vm */ |
334 | struct radeon_bo_va { |
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335 | /* protected by bo being reserved */ |
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336 | struct list_head bo_list; |
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337 | uint64_t soffset; |
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338 | uint64_t eoffset; |
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339 | uint32_t flags; |
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340 | bool valid; |
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341 | unsigned ref_count; |
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342 | |||
343 | /* protected by vm mutex */ |
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344 | struct list_head vm_list; |
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345 | |||
346 | /* constant after initialization */ |
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347 | struct radeon_vm *vm; |
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348 | struct radeon_bo *bo; |
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349 | }; |
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350 | |||
1321 | serge | 351 | struct radeon_bo { |
352 | /* Protected by gem.mutex */ |
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353 | struct list_head list; |
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354 | /* Protected by tbo.reserved */ |
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355 | u32 placements[3]; |
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356 | struct ttm_placement placement; |
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357 | struct ttm_buffer_object tbo; |
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358 | struct ttm_bo_kmap_obj kmap; |
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1404 | serge | 359 | unsigned pin_count; |
360 | void *kptr; |
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2007 | serge | 361 | void *uptr; |
1404 | serge | 362 | u32 cpu_addr; |
363 | u32 tiling_flags; |
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364 | u32 pitch; |
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365 | int surface_reg; |
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2997 | Serge | 366 | /* list of all virtual address to which this bo |
367 | * is associated to |
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368 | */ |
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369 | struct list_head va; |
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1321 | serge | 370 | /* Constant after initialization */ |
371 | struct radeon_device *rdev; |
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1963 | serge | 372 | struct drm_gem_object gem_base; |
1404 | serge | 373 | u32 domain; |
2997 | Serge | 374 | int vmapping_count; |
1321 | serge | 375 | }; |
1963 | serge | 376 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
1321 | serge | 377 | |
378 | struct radeon_bo_list { |
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379 | struct radeon_bo *bo; |
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1117 | serge | 380 | uint64_t gpu_offset; |
381 | unsigned rdomain; |
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382 | unsigned wdomain; |
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1321 | serge | 383 | u32 tiling_flags; |
1117 | serge | 384 | }; |
385 | |||
2997 | Serge | 386 | /* sub-allocation manager, it has to be protected by another lock. |
387 | * By conception this is an helper for other part of the driver |
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388 | * like the indirect buffer or semaphore, which both have their |
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389 | * locking. |
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390 | * |
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391 | * Principe is simple, we keep a list of sub allocation in offset |
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392 | * order (first entry has offset == 0, last entry has the highest |
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393 | * offset). |
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394 | * |
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395 | * When allocating new object we first check if there is room at |
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396 | * the end total_size - (last_object_offset + last_object_size) >= |
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397 | * alloc_size. If so we allocate new object there. |
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398 | * |
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399 | * When there is not enough room at the end, we start waiting for |
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400 | * each sub object until we reach object_offset+object_size >= |
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401 | * alloc_size, this object then become the sub object we return. |
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402 | * |
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403 | * Alignment can't be bigger than page size. |
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404 | * |
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405 | * Hole are not considered for allocation to keep things simple. |
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406 | * Assumption is that there won't be hole (all object on same |
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407 | * alignment). |
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408 | */ |
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409 | struct radeon_sa_manager { |
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410 | wait_queue_head_t wq; |
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411 | struct radeon_bo *bo; |
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412 | struct list_head *hole; |
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413 | struct list_head flist[RADEON_NUM_RINGS]; |
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414 | struct list_head olist; |
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415 | unsigned size; |
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416 | uint64_t gpu_addr; |
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417 | void *cpu_ptr; |
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418 | uint32_t domain; |
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419 | }; |
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420 | |||
421 | struct radeon_sa_bo; |
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422 | |||
423 | /* sub-allocation buffer */ |
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424 | struct radeon_sa_bo { |
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425 | struct list_head olist; |
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426 | struct list_head flist; |
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427 | struct radeon_sa_manager *manager; |
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428 | unsigned soffset; |
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429 | unsigned eoffset; |
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430 | struct radeon_fence *fence; |
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431 | }; |
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432 | |||
1123 | serge | 433 | /* |
434 | * GEM objects. |
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435 | */ |
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436 | struct radeon_gem { |
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1630 | serge | 437 | struct mutex mutex; |
1123 | serge | 438 | struct list_head objects; |
439 | }; |
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1117 | serge | 440 | |
1126 | serge | 441 | int radeon_gem_init(struct radeon_device *rdev); |
442 | void radeon_gem_fini(struct radeon_device *rdev); |
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443 | int radeon_gem_object_create(struct radeon_device *rdev, int size, |
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444 | int alignment, int initial_domain, |
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445 | bool discardable, bool kernel, |
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446 | struct drm_gem_object **obj); |
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1117 | serge | 447 | |
2004 | serge | 448 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
449 | struct drm_device *dev, |
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450 | struct drm_mode_create_dumb *args); |
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451 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
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452 | struct drm_device *dev, |
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453 | uint32_t handle, uint64_t *offset_p); |
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454 | int radeon_mode_dumb_destroy(struct drm_file *file_priv, |
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455 | struct drm_device *dev, |
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456 | uint32_t handle); |
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1117 | serge | 457 | |
458 | /* |
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2997 | Serge | 459 | * Semaphores. |
1117 | serge | 460 | */ |
2997 | Serge | 461 | /* everything here is constant */ |
462 | struct radeon_semaphore { |
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463 | struct radeon_sa_bo *sa_bo; |
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464 | signed waiters; |
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465 | uint64_t gpu_addr; |
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1117 | serge | 466 | }; |
467 | |||
2997 | Serge | 468 | int radeon_semaphore_create(struct radeon_device *rdev, |
469 | struct radeon_semaphore **semaphore); |
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470 | void radeon_semaphore_emit_signal(struct radeon_device *rdev, int ring, |
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471 | struct radeon_semaphore *semaphore); |
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472 | void radeon_semaphore_emit_wait(struct radeon_device *rdev, int ring, |
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473 | struct radeon_semaphore *semaphore); |
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474 | int radeon_semaphore_sync_rings(struct radeon_device *rdev, |
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475 | struct radeon_semaphore *semaphore, |
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476 | int signaler, int waiter); |
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477 | void radeon_semaphore_free(struct radeon_device *rdev, |
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478 | struct radeon_semaphore **semaphore, |
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479 | struct radeon_fence *fence); |
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1117 | serge | 480 | |
2997 | Serge | 481 | /* |
482 | * GART structures, functions & helpers |
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483 | */ |
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484 | struct radeon_mc; |
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1117 | serge | 485 | |
1268 | serge | 486 | #define RADEON_GPU_PAGE_SIZE 4096 |
1430 | serge | 487 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
2997 | Serge | 488 | #define RADEON_GPU_PAGE_SHIFT 12 |
489 | #define RADEON_GPU_PAGE_ALIGN(a) (((a) + RADEON_GPU_PAGE_MASK) & ~RADEON_GPU_PAGE_MASK) |
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1268 | serge | 490 | |
1117 | serge | 491 | struct radeon_gart { |
492 | dma_addr_t table_addr; |
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2997 | Serge | 493 | struct radeon_bo *robj; |
494 | void *ptr; |
||
1117 | serge | 495 | unsigned num_gpu_pages; |
496 | unsigned num_cpu_pages; |
||
497 | unsigned table_size; |
||
498 | struct page **pages; |
||
499 | dma_addr_t *pages_addr; |
||
500 | bool ready; |
||
501 | }; |
||
502 | |||
503 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
||
504 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
||
505 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
||
506 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
||
2997 | Serge | 507 | int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
508 | void radeon_gart_table_vram_unpin(struct radeon_device *rdev); |
||
1117 | serge | 509 | int radeon_gart_init(struct radeon_device *rdev); |
510 | void radeon_gart_fini(struct radeon_device *rdev); |
||
511 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
||
512 | int pages); |
||
1120 | serge | 513 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
2997 | Serge | 514 | int pages, u32 *pagelist, |
515 | dma_addr_t *dma_addr); |
||
516 | void radeon_gart_restore(struct radeon_device *rdev); |
||
1117 | serge | 517 | |
518 | |||
519 | /* |
||
520 | * GPU MC structures, functions & helpers |
||
521 | */ |
||
522 | struct radeon_mc { |
||
523 | resource_size_t aper_size; |
||
524 | resource_size_t aper_base; |
||
525 | resource_size_t agp_base; |
||
1179 | serge | 526 | /* for some chips with <= 32MB we need to lie |
527 | * about vram size near mc fb location */ |
||
528 | u64 mc_vram_size; |
||
1430 | serge | 529 | u64 visible_vram_size; |
1179 | serge | 530 | u64 gtt_size; |
531 | u64 gtt_start; |
||
532 | u64 gtt_end; |
||
533 | u64 vram_start; |
||
534 | u64 vram_end; |
||
1117 | serge | 535 | unsigned vram_width; |
1179 | serge | 536 | u64 real_vram_size; |
1117 | serge | 537 | int vram_mtrr; |
538 | bool vram_is_ddr; |
||
1403 | serge | 539 | bool igp_sideport_enabled; |
1963 | serge | 540 | u64 gtt_base_align; |
1117 | serge | 541 | }; |
542 | |||
1403 | serge | 543 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
544 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
||
1117 | serge | 545 | |
546 | /* |
||
547 | * GPU scratch registers structures, functions & helpers |
||
548 | */ |
||
549 | struct radeon_scratch { |
||
550 | unsigned num_reg; |
||
1963 | serge | 551 | uint32_t reg_base; |
1117 | serge | 552 | bool free[32]; |
553 | uint32_t reg[32]; |
||
554 | }; |
||
555 | |||
556 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
||
557 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
||
558 | |||
559 | |||
560 | /* |
||
561 | * IRQS. |
||
562 | */ |
||
1963 | serge | 563 | struct r500_irq_stat_regs { |
564 | u32 disp_int; |
||
2997 | Serge | 565 | u32 hdmi0_status; |
1963 | serge | 566 | }; |
567 | |||
568 | struct r600_irq_stat_regs { |
||
569 | u32 disp_int; |
||
570 | u32 disp_int_cont; |
||
571 | u32 disp_int_cont2; |
||
572 | u32 d1grph_int; |
||
573 | u32 d2grph_int; |
||
2997 | Serge | 574 | u32 hdmi0_status; |
575 | u32 hdmi1_status; |
||
1963 | serge | 576 | }; |
577 | |||
578 | struct evergreen_irq_stat_regs { |
||
579 | u32 disp_int; |
||
580 | u32 disp_int_cont; |
||
581 | u32 disp_int_cont2; |
||
582 | u32 disp_int_cont3; |
||
583 | u32 disp_int_cont4; |
||
584 | u32 disp_int_cont5; |
||
585 | u32 d1grph_int; |
||
586 | u32 d2grph_int; |
||
587 | u32 d3grph_int; |
||
588 | u32 d4grph_int; |
||
589 | u32 d5grph_int; |
||
590 | u32 d6grph_int; |
||
2997 | Serge | 591 | u32 afmt_status1; |
592 | u32 afmt_status2; |
||
593 | u32 afmt_status3; |
||
594 | u32 afmt_status4; |
||
595 | u32 afmt_status5; |
||
596 | u32 afmt_status6; |
||
1963 | serge | 597 | }; |
598 | |||
599 | union radeon_irq_stat_regs { |
||
600 | struct r500_irq_stat_regs r500; |
||
601 | struct r600_irq_stat_regs r600; |
||
602 | struct evergreen_irq_stat_regs evergreen; |
||
603 | }; |
||
604 | |||
2997 | Serge | 605 | #define RADEON_MAX_HPD_PINS 6 |
606 | #define RADEON_MAX_CRTCS 6 |
||
607 | #define RADEON_MAX_AFMT_BLOCKS 6 |
||
608 | |||
1117 | serge | 609 | struct radeon_irq { |
610 | bool installed; |
||
2997 | Serge | 611 | spinlock_t lock; |
612 | atomic_t ring_int[RADEON_NUM_RINGS]; |
||
613 | bool crtc_vblank_int[RADEON_MAX_CRTCS]; |
||
614 | atomic_t pflip[RADEON_MAX_CRTCS]; |
||
1963 | serge | 615 | wait_queue_head_t vblank_queue; |
2997 | Serge | 616 | bool hpd[RADEON_MAX_HPD_PINS]; |
617 | bool afmt[RADEON_MAX_AFMT_BLOCKS]; |
||
1963 | serge | 618 | union radeon_irq_stat_regs stat_regs; |
1117 | serge | 619 | }; |
620 | |||
621 | int radeon_irq_kms_init(struct radeon_device *rdev); |
||
622 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
||
2997 | Serge | 623 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev, int ring); |
624 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev, int ring); |
||
2004 | serge | 625 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
626 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); |
||
2997 | Serge | 627 | void radeon_irq_kms_enable_afmt(struct radeon_device *rdev, int block); |
628 | void radeon_irq_kms_disable_afmt(struct radeon_device *rdev, int block); |
||
629 | void radeon_irq_kms_enable_hpd(struct radeon_device *rdev, unsigned hpd_mask); |
||
630 | void radeon_irq_kms_disable_hpd(struct radeon_device *rdev, unsigned hpd_mask); |
||
1117 | serge | 631 | |
632 | /* |
||
2997 | Serge | 633 | * CP & rings. |
1117 | serge | 634 | */ |
2997 | Serge | 635 | |
1117 | serge | 636 | struct radeon_ib { |
2997 | Serge | 637 | struct radeon_sa_bo *sa_bo; |
638 | uint32_t length_dw; |
||
1403 | serge | 639 | uint64_t gpu_addr; |
2997 | Serge | 640 | uint32_t *ptr; |
641 | int ring; |
||
1117 | serge | 642 | struct radeon_fence *fence; |
2997 | Serge | 643 | struct radeon_vm *vm; |
644 | bool is_const_ib; |
||
645 | struct radeon_fence *sync_to[RADEON_NUM_RINGS]; |
||
646 | struct radeon_semaphore *semaphore; |
||
1117 | serge | 647 | }; |
648 | |||
2997 | Serge | 649 | struct radeon_ring { |
1321 | serge | 650 | struct radeon_bo *ring_obj; |
1117 | serge | 651 | volatile uint32_t *ring; |
1403 | serge | 652 | unsigned rptr; |
2997 | Serge | 653 | unsigned rptr_offs; |
654 | unsigned rptr_reg; |
||
655 | unsigned rptr_save_reg; |
||
656 | u64 next_rptr_gpu_addr; |
||
657 | volatile u32 *next_rptr_cpu_addr; |
||
1403 | serge | 658 | unsigned wptr; |
659 | unsigned wptr_old; |
||
2997 | Serge | 660 | unsigned wptr_reg; |
1403 | serge | 661 | unsigned ring_size; |
662 | unsigned ring_free_dw; |
||
663 | int count_dw; |
||
2997 | Serge | 664 | unsigned long last_activity; |
665 | unsigned last_rptr; |
||
1403 | serge | 666 | uint64_t gpu_addr; |
667 | uint32_t align_mask; |
||
668 | uint32_t ptr_mask; |
||
669 | bool ready; |
||
2997 | Serge | 670 | u32 ptr_reg_shift; |
671 | u32 ptr_reg_mask; |
||
672 | u32 nop; |
||
673 | u32 idx; |
||
1117 | serge | 674 | }; |
675 | |||
1321 | serge | 676 | /* |
2997 | Serge | 677 | * VM |
678 | */ |
||
679 | |||
680 | /* maximum number of VMIDs */ |
||
681 | #define RADEON_NUM_VM 16 |
||
682 | |||
683 | /* defines number of bits in page table versus page directory, |
||
684 | * a page is 4KB so we have 12 bits offset, 9 bits in the page |
||
685 | * table and the remaining 19 bits are in the page directory */ |
||
686 | #define RADEON_VM_BLOCK_SIZE 9 |
||
687 | |||
688 | /* number of entries in page table */ |
||
689 | #define RADEON_VM_PTE_COUNT (1 << RADEON_VM_BLOCK_SIZE) |
||
690 | |||
691 | struct radeon_vm { |
||
692 | struct list_head list; |
||
693 | struct list_head va; |
||
694 | unsigned id; |
||
695 | |||
696 | /* contains the page directory */ |
||
697 | struct radeon_sa_bo *page_directory; |
||
698 | uint64_t pd_gpu_addr; |
||
699 | |||
700 | /* array of page tables, one for each page directory entry */ |
||
701 | struct radeon_sa_bo **page_tables; |
||
702 | |||
703 | struct mutex mutex; |
||
704 | /* last fence for cs using this vm */ |
||
705 | struct radeon_fence *fence; |
||
706 | /* last flush or NULL if we still need to flush */ |
||
707 | struct radeon_fence *last_flush; |
||
708 | }; |
||
709 | |||
710 | struct radeon_vm_manager { |
||
711 | struct mutex lock; |
||
712 | struct list_head lru_vm; |
||
713 | struct radeon_fence *active[RADEON_NUM_VM]; |
||
714 | struct radeon_sa_manager sa_manager; |
||
715 | uint32_t max_pfn; |
||
716 | /* number of VMIDs */ |
||
717 | unsigned nvm; |
||
718 | /* vram base address for page table entry */ |
||
719 | u64 vram_base_offset; |
||
720 | /* is vm enabled? */ |
||
721 | bool enabled; |
||
722 | }; |
||
723 | |||
724 | /* |
||
725 | * file private structure |
||
726 | */ |
||
727 | struct radeon_fpriv { |
||
728 | struct radeon_vm vm; |
||
729 | }; |
||
730 | |||
731 | /* |
||
1321 | serge | 732 | * R6xx+ IH ring |
733 | */ |
||
734 | struct r600_ih { |
||
735 | struct radeon_bo *ring_obj; |
||
736 | volatile uint32_t *ring; |
||
737 | unsigned rptr; |
||
738 | unsigned ring_size; |
||
739 | uint64_t gpu_addr; |
||
740 | uint32_t ptr_mask; |
||
2997 | Serge | 741 | atomic_t lock; |
1321 | serge | 742 | bool enabled; |
743 | }; |
||
744 | |||
2997 | Serge | 745 | struct r600_blit_cp_primitives { |
746 | void (*set_render_target)(struct radeon_device *rdev, int format, |
||
747 | int w, int h, u64 gpu_addr); |
||
748 | void (*cp_set_surface_sync)(struct radeon_device *rdev, |
||
749 | u32 sync_type, u32 size, |
||
750 | u64 mc_addr); |
||
751 | void (*set_shaders)(struct radeon_device *rdev); |
||
752 | void (*set_vtx_resource)(struct radeon_device *rdev, u64 gpu_addr); |
||
753 | void (*set_tex_resource)(struct radeon_device *rdev, |
||
754 | int format, int w, int h, int pitch, |
||
755 | u64 gpu_addr, u32 size); |
||
756 | void (*set_scissors)(struct radeon_device *rdev, int x1, int y1, |
||
757 | int x2, int y2); |
||
758 | void (*draw_auto)(struct radeon_device *rdev); |
||
759 | void (*set_default_state)(struct radeon_device *rdev); |
||
760 | }; |
||
761 | |||
1179 | serge | 762 | struct r600_blit { |
1321 | serge | 763 | struct radeon_bo *shader_obj; |
2997 | Serge | 764 | struct r600_blit_cp_primitives primitives; |
765 | int max_dim; |
||
766 | int ring_size_common; |
||
767 | int ring_size_per_loop; |
||
1179 | serge | 768 | u64 shader_gpu_addr; |
769 | u32 vs_offset, ps_offset; |
||
770 | u32 state_offset; |
||
771 | u32 state_len; |
||
772 | }; |
||
773 | |||
2997 | Serge | 774 | /* |
775 | * SI RLC stuff |
||
776 | */ |
||
777 | struct si_rlc { |
||
778 | /* for power gating */ |
||
779 | struct radeon_bo *save_restore_obj; |
||
780 | uint64_t save_restore_gpu_addr; |
||
781 | /* for clear state */ |
||
782 | struct radeon_bo *clear_state_obj; |
||
783 | uint64_t clear_state_gpu_addr; |
||
784 | }; |
||
785 | |||
786 | int radeon_ib_get(struct radeon_device *rdev, int ring, |
||
787 | struct radeon_ib *ib, struct radeon_vm *vm, |
||
788 | unsigned size); |
||
789 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib *ib); |
||
790 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib, |
||
791 | struct radeon_ib *const_ib); |
||
1117 | serge | 792 | int radeon_ib_pool_init(struct radeon_device *rdev); |
793 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
||
2997 | Serge | 794 | int radeon_ib_ring_tests(struct radeon_device *rdev); |
1117 | serge | 795 | /* Ring access between begin & end cannot sleep */ |
2997 | Serge | 796 | bool radeon_ring_supports_scratch_reg(struct radeon_device *rdev, |
797 | struct radeon_ring *ring); |
||
798 | void radeon_ring_free_size(struct radeon_device *rdev, struct radeon_ring *cp); |
||
799 | int radeon_ring_alloc(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
||
800 | int radeon_ring_lock(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ndw); |
||
801 | void radeon_ring_commit(struct radeon_device *rdev, struct radeon_ring *cp); |
||
802 | void radeon_ring_unlock_commit(struct radeon_device *rdev, struct radeon_ring *cp); |
||
803 | void radeon_ring_undo(struct radeon_ring *ring); |
||
804 | void radeon_ring_unlock_undo(struct radeon_device *rdev, struct radeon_ring *cp); |
||
805 | int radeon_ring_test(struct radeon_device *rdev, struct radeon_ring *cp); |
||
806 | void radeon_ring_force_activity(struct radeon_device *rdev, struct radeon_ring *ring); |
||
807 | void radeon_ring_lockup_update(struct radeon_ring *ring); |
||
808 | bool radeon_ring_test_lockup(struct radeon_device *rdev, struct radeon_ring *ring); |
||
809 | unsigned radeon_ring_backup(struct radeon_device *rdev, struct radeon_ring *ring, |
||
810 | uint32_t **data); |
||
811 | int radeon_ring_restore(struct radeon_device *rdev, struct radeon_ring *ring, |
||
812 | unsigned size, uint32_t *data); |
||
813 | int radeon_ring_init(struct radeon_device *rdev, struct radeon_ring *cp, unsigned ring_size, |
||
814 | unsigned rptr_offs, unsigned rptr_reg, unsigned wptr_reg, |
||
815 | u32 ptr_reg_shift, u32 ptr_reg_mask, u32 nop); |
||
816 | void radeon_ring_fini(struct radeon_device *rdev, struct radeon_ring *cp); |
||
1117 | serge | 817 | |
818 | |||
819 | /* |
||
820 | * CS. |
||
821 | */ |
||
822 | struct radeon_cs_reloc { |
||
823 | // struct drm_gem_object *gobj; |
||
1321 | serge | 824 | struct radeon_bo *robj; |
1630 | serge | 825 | struct radeon_bo_list lobj; |
1403 | serge | 826 | uint32_t handle; |
827 | uint32_t flags; |
||
1117 | serge | 828 | }; |
829 | |||
830 | struct radeon_cs_chunk { |
||
831 | uint32_t chunk_id; |
||
832 | uint32_t length_dw; |
||
1221 | serge | 833 | int kpage_idx[2]; |
834 | uint32_t *kpage[2]; |
||
1117 | serge | 835 | uint32_t *kdata; |
1221 | serge | 836 | void __user *user_ptr; |
837 | int last_copied_page; |
||
838 | int last_page_index; |
||
1117 | serge | 839 | }; |
840 | |||
841 | struct radeon_cs_parser { |
||
1430 | serge | 842 | struct device *dev; |
1117 | serge | 843 | struct radeon_device *rdev; |
2004 | serge | 844 | struct drm_file *filp; |
1117 | serge | 845 | /* chunks */ |
846 | unsigned nchunks; |
||
847 | struct radeon_cs_chunk *chunks; |
||
848 | uint64_t *chunks_array; |
||
849 | /* IB */ |
||
850 | unsigned idx; |
||
851 | /* relocations */ |
||
852 | unsigned nrelocs; |
||
853 | struct radeon_cs_reloc *relocs; |
||
854 | struct radeon_cs_reloc **relocs_ptr; |
||
1120 | serge | 855 | struct list_head validated; |
1117 | serge | 856 | /* indices of various chunks */ |
857 | int chunk_ib_idx; |
||
858 | int chunk_relocs_idx; |
||
2997 | Serge | 859 | int chunk_flags_idx; |
860 | int chunk_const_ib_idx; |
||
861 | struct radeon_ib ib; |
||
862 | struct radeon_ib const_ib; |
||
1117 | serge | 863 | void *track; |
1179 | serge | 864 | unsigned family; |
1221 | serge | 865 | int parser_error; |
2997 | Serge | 866 | u32 cs_flags; |
867 | u32 ring; |
||
868 | s32 priority; |
||
1117 | serge | 869 | }; |
870 | |||
1221 | serge | 871 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
2997 | Serge | 872 | extern u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx); |
1221 | serge | 873 | |
1117 | serge | 874 | struct radeon_cs_packet { |
875 | unsigned idx; |
||
876 | unsigned type; |
||
877 | unsigned reg; |
||
878 | unsigned opcode; |
||
879 | int count; |
||
880 | unsigned one_reg_wr; |
||
881 | }; |
||
882 | |||
883 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
||
884 | struct radeon_cs_packet *pkt, |
||
885 | unsigned idx, unsigned reg); |
||
886 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
||
887 | struct radeon_cs_packet *pkt); |
||
888 | |||
889 | |||
890 | /* |
||
891 | * AGP |
||
892 | */ |
||
893 | int radeon_agp_init(struct radeon_device *rdev); |
||
1321 | serge | 894 | void radeon_agp_resume(struct radeon_device *rdev); |
1963 | serge | 895 | void radeon_agp_suspend(struct radeon_device *rdev); |
1117 | serge | 896 | void radeon_agp_fini(struct radeon_device *rdev); |
897 | |||
898 | |||
899 | /* |
||
900 | * Writeback |
||
901 | */ |
||
902 | struct radeon_wb { |
||
1321 | serge | 903 | struct radeon_bo *wb_obj; |
1117 | serge | 904 | volatile uint32_t *wb; |
905 | uint64_t gpu_addr; |
||
1963 | serge | 906 | bool enabled; |
907 | bool use_event; |
||
1117 | serge | 908 | }; |
909 | |||
1963 | serge | 910 | #define RADEON_WB_SCRATCH_OFFSET 0 |
2997 | Serge | 911 | #define RADEON_WB_RING0_NEXT_RPTR 256 |
1963 | serge | 912 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
913 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
||
914 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 |
||
915 | #define R600_WB_IH_WPTR_OFFSET 2048 |
||
916 | #define R600_WB_EVENT_OFFSET 3072 |
||
917 | |||
1179 | serge | 918 | /** |
919 | * struct radeon_pm - power management datas |
||
920 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
||
921 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
||
922 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
||
923 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
||
924 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
||
925 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
||
926 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
||
927 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
||
928 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
||
1963 | serge | 929 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
1179 | serge | 930 | * @needed_bandwidth: current bandwidth needs |
931 | * |
||
932 | * It keeps track of various data needed to take powermanagement decision. |
||
1963 | serge | 933 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
1179 | serge | 934 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
935 | * (type of memory, bus size, efficiency, ...) |
||
936 | */ |
||
1963 | serge | 937 | |
938 | enum radeon_pm_method { |
||
939 | PM_METHOD_PROFILE, |
||
940 | PM_METHOD_DYNPM, |
||
1430 | serge | 941 | }; |
1963 | serge | 942 | |
943 | enum radeon_dynpm_state { |
||
944 | DYNPM_STATE_DISABLED, |
||
945 | DYNPM_STATE_MINIMUM, |
||
946 | DYNPM_STATE_PAUSED, |
||
947 | DYNPM_STATE_ACTIVE, |
||
948 | DYNPM_STATE_SUSPENDED, |
||
1430 | serge | 949 | }; |
1963 | serge | 950 | enum radeon_dynpm_action { |
951 | DYNPM_ACTION_NONE, |
||
952 | DYNPM_ACTION_MINIMUM, |
||
953 | DYNPM_ACTION_DOWNCLOCK, |
||
954 | DYNPM_ACTION_UPCLOCK, |
||
955 | DYNPM_ACTION_DEFAULT |
||
956 | }; |
||
1430 | serge | 957 | |
958 | enum radeon_voltage_type { |
||
959 | VOLTAGE_NONE = 0, |
||
960 | VOLTAGE_GPIO, |
||
961 | VOLTAGE_VDDC, |
||
962 | VOLTAGE_SW |
||
963 | }; |
||
964 | |||
965 | enum radeon_pm_state_type { |
||
966 | POWER_STATE_TYPE_DEFAULT, |
||
967 | POWER_STATE_TYPE_POWERSAVE, |
||
968 | POWER_STATE_TYPE_BATTERY, |
||
969 | POWER_STATE_TYPE_BALANCED, |
||
970 | POWER_STATE_TYPE_PERFORMANCE, |
||
971 | }; |
||
972 | |||
1963 | serge | 973 | enum radeon_pm_profile_type { |
974 | PM_PROFILE_DEFAULT, |
||
975 | PM_PROFILE_AUTO, |
||
976 | PM_PROFILE_LOW, |
||
977 | PM_PROFILE_MID, |
||
978 | PM_PROFILE_HIGH, |
||
1430 | serge | 979 | }; |
980 | |||
1963 | serge | 981 | #define PM_PROFILE_DEFAULT_IDX 0 |
982 | #define PM_PROFILE_LOW_SH_IDX 1 |
||
983 | #define PM_PROFILE_MID_SH_IDX 2 |
||
984 | #define PM_PROFILE_HIGH_SH_IDX 3 |
||
985 | #define PM_PROFILE_LOW_MH_IDX 4 |
||
986 | #define PM_PROFILE_MID_MH_IDX 5 |
||
987 | #define PM_PROFILE_HIGH_MH_IDX 6 |
||
988 | #define PM_PROFILE_MAX 7 |
||
989 | |||
990 | struct radeon_pm_profile { |
||
991 | int dpms_off_ps_idx; |
||
992 | int dpms_on_ps_idx; |
||
993 | int dpms_off_cm_idx; |
||
994 | int dpms_on_cm_idx; |
||
995 | }; |
||
996 | |||
997 | enum radeon_int_thermal_type { |
||
998 | THERMAL_TYPE_NONE, |
||
999 | THERMAL_TYPE_RV6XX, |
||
1000 | THERMAL_TYPE_RV770, |
||
1001 | THERMAL_TYPE_EVERGREEN, |
||
1002 | THERMAL_TYPE_SUMO, |
||
1003 | THERMAL_TYPE_NI, |
||
2997 | Serge | 1004 | THERMAL_TYPE_SI, |
1963 | serge | 1005 | }; |
1006 | |||
1430 | serge | 1007 | struct radeon_voltage { |
1008 | enum radeon_voltage_type type; |
||
1009 | /* gpio voltage */ |
||
1010 | struct radeon_gpio_rec gpio; |
||
1011 | u32 delay; /* delay in usec from voltage drop to sclk change */ |
||
1012 | bool active_high; /* voltage drop is active when bit is high */ |
||
1013 | /* VDDC voltage */ |
||
1014 | u8 vddc_id; /* index into vddc voltage table */ |
||
1015 | u8 vddci_id; /* index into vddci voltage table */ |
||
1016 | bool vddci_enabled; |
||
1017 | /* r6xx+ sw */ |
||
1963 | serge | 1018 | u16 voltage; |
1019 | /* evergreen+ vddci */ |
||
1020 | u16 vddci; |
||
1430 | serge | 1021 | }; |
1022 | |||
1963 | serge | 1023 | /* clock mode flags */ |
1024 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) |
||
1430 | serge | 1025 | |
1026 | struct radeon_pm_clock_info { |
||
1027 | /* memory clock */ |
||
1028 | u32 mclk; |
||
1029 | /* engine clock */ |
||
1030 | u32 sclk; |
||
1031 | /* voltage info */ |
||
1032 | struct radeon_voltage voltage; |
||
1963 | serge | 1033 | /* standardized clock flags */ |
1430 | serge | 1034 | u32 flags; |
1035 | }; |
||
1036 | |||
1963 | serge | 1037 | /* state flags */ |
1038 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
||
1039 | |||
1430 | serge | 1040 | struct radeon_power_state { |
1041 | enum radeon_pm_state_type type; |
||
2997 | Serge | 1042 | struct radeon_pm_clock_info *clock_info; |
1430 | serge | 1043 | /* number of valid clock modes in this power state */ |
1044 | int num_clock_modes; |
||
1045 | struct radeon_pm_clock_info *default_clock_mode; |
||
1963 | serge | 1046 | /* standardized state flags */ |
1047 | u32 flags; |
||
1048 | u32 misc; /* vbios specific flags */ |
||
1049 | u32 misc2; /* vbios specific flags */ |
||
1050 | int pcie_lanes; /* pcie lanes */ |
||
1430 | serge | 1051 | }; |
1052 | |||
1053 | /* |
||
1054 | * Some modes are overclocked by very low value, accept them |
||
1055 | */ |
||
1056 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ |
||
1057 | |||
1179 | serge | 1058 | struct radeon_pm { |
1630 | serge | 1059 | struct mutex mutex; |
2997 | Serge | 1060 | /* write locked while reprogramming mclk */ |
1061 | struct rw_semaphore mclk_lock; |
||
1963 | serge | 1062 | u32 active_crtcs; |
1063 | int active_crtc_count; |
||
1430 | serge | 1064 | int req_vblank; |
1963 | serge | 1065 | bool vblank_sync; |
1179 | serge | 1066 | fixed20_12 max_bandwidth; |
1067 | fixed20_12 igp_sideport_mclk; |
||
1068 | fixed20_12 igp_system_mclk; |
||
1069 | fixed20_12 igp_ht_link_clk; |
||
1070 | fixed20_12 igp_ht_link_width; |
||
1071 | fixed20_12 k8_bandwidth; |
||
1072 | fixed20_12 sideport_bandwidth; |
||
1073 | fixed20_12 ht_bandwidth; |
||
1074 | fixed20_12 core_bandwidth; |
||
1075 | fixed20_12 sclk; |
||
1963 | serge | 1076 | fixed20_12 mclk; |
1179 | serge | 1077 | fixed20_12 needed_bandwidth; |
1963 | serge | 1078 | struct radeon_power_state *power_state; |
1430 | serge | 1079 | /* number of valid power states */ |
1080 | int num_power_states; |
||
1963 | serge | 1081 | int current_power_state_index; |
1082 | int current_clock_mode_index; |
||
1083 | int requested_power_state_index; |
||
1084 | int requested_clock_mode_index; |
||
1085 | int default_power_state_index; |
||
1086 | u32 current_sclk; |
||
1087 | u32 current_mclk; |
||
1088 | u16 current_vddc; |
||
1089 | u16 current_vddci; |
||
1090 | u32 default_sclk; |
||
1091 | u32 default_mclk; |
||
1092 | u16 default_vddc; |
||
1093 | u16 default_vddci; |
||
1094 | struct radeon_i2c_chan *i2c_bus; |
||
1095 | /* selected pm method */ |
||
1096 | enum radeon_pm_method pm_method; |
||
1097 | /* dynpm power management */ |
||
1098 | // struct delayed_work dynpm_idle_work; |
||
1099 | enum radeon_dynpm_state dynpm_state; |
||
1100 | enum radeon_dynpm_action dynpm_planned_action; |
||
1101 | unsigned long dynpm_action_timeout; |
||
1102 | bool dynpm_can_upclock; |
||
1103 | bool dynpm_can_downclock; |
||
1104 | /* profile-based power management */ |
||
1105 | enum radeon_pm_profile_type profile; |
||
1106 | int profile_index; |
||
1107 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; |
||
1108 | /* internal thermal controller on rv6xx+ */ |
||
1109 | enum radeon_int_thermal_type int_thermal_type; |
||
1110 | struct device *int_hwmon_dev; |
||
1179 | serge | 1111 | }; |
1117 | serge | 1112 | |
2997 | Serge | 1113 | int radeon_pm_get_type_index(struct radeon_device *rdev, |
1114 | enum radeon_pm_state_type ps_type, |
||
1115 | int instance); |
||
1116 | |||
1117 | struct r600_audio { |
||
1118 | int channels; |
||
1119 | int rate; |
||
1120 | int bits_per_sample; |
||
1121 | u8 status_bits; |
||
1122 | u8 category_code; |
||
1123 | }; |
||
1117 | serge | 1124 | /* |
1125 | * ASIC specific functions. |
||
1126 | */ |
||
1127 | struct radeon_asic { |
||
1128 | int (*init)(struct radeon_device *rdev); |
||
1179 | serge | 1129 | void (*fini)(struct radeon_device *rdev); |
1130 | int (*resume)(struct radeon_device *rdev); |
||
1131 | int (*suspend)(struct radeon_device *rdev); |
||
1132 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
||
1963 | serge | 1133 | int (*asic_reset)(struct radeon_device *rdev); |
2997 | Serge | 1134 | /* ioctl hw specific callback. Some hw might want to perform special |
1135 | * operation on specific ioctl. For instance on wait idle some hw |
||
1136 | * might want to perform and HDP flush through MMIO as it seems that |
||
1137 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed |
||
1138 | * through ring. |
||
1139 | */ |
||
1140 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); |
||
1141 | /* check if 3D engine is idle */ |
||
1142 | bool (*gui_idle)(struct radeon_device *rdev); |
||
1143 | /* wait for mc_idle */ |
||
1144 | int (*mc_wait_for_idle)(struct radeon_device *rdev); |
||
1145 | /* gart */ |
||
1146 | struct { |
||
1147 | void (*tlb_flush)(struct radeon_device *rdev); |
||
1148 | int (*set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
||
1149 | } gart; |
||
1150 | struct { |
||
1151 | int (*init)(struct radeon_device *rdev); |
||
1152 | void (*fini)(struct radeon_device *rdev); |
||
1153 | |||
1154 | u32 pt_ring_index; |
||
1155 | void (*set_page)(struct radeon_device *rdev, uint64_t pe, |
||
1156 | uint64_t addr, unsigned count, |
||
1157 | uint32_t incr, uint32_t flags); |
||
1158 | } vm; |
||
1159 | /* ring specific callbacks */ |
||
1160 | struct { |
||
1161 | void (*ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
||
1162 | int (*ib_parse)(struct radeon_device *rdev, struct radeon_ib *ib); |
||
1163 | void (*emit_fence)(struct radeon_device *rdev, struct radeon_fence *fence); |
||
1164 | void (*emit_semaphore)(struct radeon_device *rdev, struct radeon_ring *cp, |
||
1165 | struct radeon_semaphore *semaphore, bool emit_wait); |
||
1166 | int (*cs_parse)(struct radeon_cs_parser *p); |
||
1167 | void (*ring_start)(struct radeon_device *rdev, struct radeon_ring *cp); |
||
1168 | int (*ring_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
||
1169 | int (*ib_test)(struct radeon_device *rdev, struct radeon_ring *cp); |
||
1170 | bool (*is_lockup)(struct radeon_device *rdev, struct radeon_ring *cp); |
||
1171 | void (*vm_flush)(struct radeon_device *rdev, int ridx, struct radeon_vm *vm); |
||
1172 | } ring[RADEON_NUM_RINGS]; |
||
1173 | /* irqs */ |
||
1174 | struct { |
||
1175 | int (*set)(struct radeon_device *rdev); |
||
1176 | int (*process)(struct radeon_device *rdev); |
||
1177 | } irq; |
||
1178 | /* displays */ |
||
1179 | struct { |
||
1180 | /* display watermarks */ |
||
1181 | void (*bandwidth_update)(struct radeon_device *rdev); |
||
1182 | /* get frame count */ |
||
1179 | serge | 1183 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
2997 | Serge | 1184 | /* wait for vblank */ |
1185 | void (*wait_for_vblank)(struct radeon_device *rdev, int crtc); |
||
1186 | /* set backlight level */ |
||
1187 | void (*set_backlight_level)(struct radeon_encoder *radeon_encoder, u8 level); |
||
1188 | /* get backlight level */ |
||
1189 | u8 (*get_backlight_level)(struct radeon_encoder *radeon_encoder); |
||
1190 | } display; |
||
1191 | /* copy functions for bo handling */ |
||
1192 | struct { |
||
1193 | int (*blit)(struct radeon_device *rdev, |
||
1117 | serge | 1194 | uint64_t src_offset, |
1195 | uint64_t dst_offset, |
||
2997 | Serge | 1196 | unsigned num_gpu_pages, |
1197 | struct radeon_fence **fence); |
||
1198 | u32 blit_ring_index; |
||
1199 | int (*dma)(struct radeon_device *rdev, |
||
1117 | serge | 1200 | uint64_t src_offset, |
1201 | uint64_t dst_offset, |
||
2997 | Serge | 1202 | unsigned num_gpu_pages, |
1203 | struct radeon_fence **fence); |
||
1204 | u32 dma_ring_index; |
||
1205 | /* method used for bo copy */ |
||
1117 | serge | 1206 | int (*copy)(struct radeon_device *rdev, |
1207 | uint64_t src_offset, |
||
1208 | uint64_t dst_offset, |
||
2997 | Serge | 1209 | unsigned num_gpu_pages, |
1210 | struct radeon_fence **fence); |
||
1211 | /* ring used for bo copies */ |
||
1212 | u32 copy_ring_index; |
||
1213 | } copy; |
||
1214 | /* surfaces */ |
||
1215 | struct { |
||
1216 | int (*set_reg)(struct radeon_device *rdev, int reg, |
||
1217 | uint32_t tiling_flags, uint32_t pitch, |
||
1218 | uint32_t offset, uint32_t obj_size); |
||
1219 | void (*clear_reg)(struct radeon_device *rdev, int reg); |
||
1220 | } surface; |
||
1221 | /* hotplug detect */ |
||
1222 | struct { |
||
1223 | void (*init)(struct radeon_device *rdev); |
||
1224 | void (*fini)(struct radeon_device *rdev); |
||
1225 | bool (*sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
||
1226 | void (*set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
||
1227 | } hpd; |
||
1228 | /* power management */ |
||
1229 | struct { |
||
1230 | void (*misc)(struct radeon_device *rdev); |
||
1231 | void (*prepare)(struct radeon_device *rdev); |
||
1232 | void (*finish)(struct radeon_device *rdev); |
||
1233 | void (*init_profile)(struct radeon_device *rdev); |
||
1234 | void (*get_dynpm_state)(struct radeon_device *rdev); |
||
1268 | serge | 1235 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
1117 | serge | 1236 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
1268 | serge | 1237 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
1117 | serge | 1238 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
1430 | serge | 1239 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
1117 | serge | 1240 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
1241 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
||
2997 | Serge | 1242 | } pm; |
1963 | serge | 1243 | /* pageflipping */ |
2997 | Serge | 1244 | struct { |
1963 | serge | 1245 | void (*pre_page_flip)(struct radeon_device *rdev, int crtc); |
1246 | u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); |
||
1247 | void (*post_page_flip)(struct radeon_device *rdev, int crtc); |
||
2997 | Serge | 1248 | } pflip; |
1117 | serge | 1249 | }; |
1250 | |||
1179 | serge | 1251 | /* |
1252 | * Asic structures |
||
1253 | */ |
||
1254 | struct r100_asic { |
||
1255 | const unsigned *reg_safe_bm; |
||
1256 | unsigned reg_safe_bm_size; |
||
1403 | serge | 1257 | u32 hdp_cntl; |
1179 | serge | 1258 | }; |
1259 | |||
1260 | struct r300_asic { |
||
1261 | const unsigned *reg_safe_bm; |
||
1262 | unsigned reg_safe_bm_size; |
||
1403 | serge | 1263 | u32 resync_scratch; |
1264 | u32 hdp_cntl; |
||
1179 | serge | 1265 | }; |
1266 | |||
1267 | struct r600_asic { |
||
1268 | unsigned max_pipes; |
||
1269 | unsigned max_tile_pipes; |
||
1270 | unsigned max_simds; |
||
1271 | unsigned max_backends; |
||
1272 | unsigned max_gprs; |
||
1273 | unsigned max_threads; |
||
1274 | unsigned max_stack_entries; |
||
1275 | unsigned max_hw_contexts; |
||
1276 | unsigned max_gs_threads; |
||
1277 | unsigned sx_max_export_size; |
||
1278 | unsigned sx_max_export_pos_size; |
||
1279 | unsigned sx_max_export_smx_size; |
||
1280 | unsigned sq_num_cf_insts; |
||
1430 | serge | 1281 | unsigned tiling_nbanks; |
1282 | unsigned tiling_npipes; |
||
1283 | unsigned tiling_group_size; |
||
1963 | serge | 1284 | unsigned tile_config; |
2160 | serge | 1285 | unsigned backend_map; |
1179 | serge | 1286 | }; |
1287 | |||
1288 | struct rv770_asic { |
||
1289 | unsigned max_pipes; |
||
1290 | unsigned max_tile_pipes; |
||
1291 | unsigned max_simds; |
||
1292 | unsigned max_backends; |
||
1293 | unsigned max_gprs; |
||
1294 | unsigned max_threads; |
||
1295 | unsigned max_stack_entries; |
||
1296 | unsigned max_hw_contexts; |
||
1297 | unsigned max_gs_threads; |
||
1298 | unsigned sx_max_export_size; |
||
1299 | unsigned sx_max_export_pos_size; |
||
1300 | unsigned sx_max_export_smx_size; |
||
1301 | unsigned sq_num_cf_insts; |
||
1302 | unsigned sx_num_of_sets; |
||
1303 | unsigned sc_prim_fifo_size; |
||
1304 | unsigned sc_hiz_tile_fifo_size; |
||
1305 | unsigned sc_earlyz_tile_fifo_fize; |
||
1430 | serge | 1306 | unsigned tiling_nbanks; |
1307 | unsigned tiling_npipes; |
||
1308 | unsigned tiling_group_size; |
||
1963 | serge | 1309 | unsigned tile_config; |
2160 | serge | 1310 | unsigned backend_map; |
1179 | serge | 1311 | }; |
1312 | |||
1963 | serge | 1313 | struct evergreen_asic { |
1314 | unsigned num_ses; |
||
1315 | unsigned max_pipes; |
||
1316 | unsigned max_tile_pipes; |
||
1317 | unsigned max_simds; |
||
1318 | unsigned max_backends; |
||
1319 | unsigned max_gprs; |
||
1320 | unsigned max_threads; |
||
1321 | unsigned max_stack_entries; |
||
1322 | unsigned max_hw_contexts; |
||
1323 | unsigned max_gs_threads; |
||
1324 | unsigned sx_max_export_size; |
||
1325 | unsigned sx_max_export_pos_size; |
||
1326 | unsigned sx_max_export_smx_size; |
||
1327 | unsigned sq_num_cf_insts; |
||
1328 | unsigned sx_num_of_sets; |
||
1329 | unsigned sc_prim_fifo_size; |
||
1330 | unsigned sc_hiz_tile_fifo_size; |
||
1331 | unsigned sc_earlyz_tile_fifo_size; |
||
1332 | unsigned tiling_nbanks; |
||
1333 | unsigned tiling_npipes; |
||
1334 | unsigned tiling_group_size; |
||
1335 | unsigned tile_config; |
||
2160 | serge | 1336 | unsigned backend_map; |
1963 | serge | 1337 | }; |
1338 | |||
1339 | struct cayman_asic { |
||
1340 | unsigned max_shader_engines; |
||
1341 | unsigned max_pipes_per_simd; |
||
1342 | unsigned max_tile_pipes; |
||
1343 | unsigned max_simds_per_se; |
||
1344 | unsigned max_backends_per_se; |
||
1345 | unsigned max_texture_channel_caches; |
||
1346 | unsigned max_gprs; |
||
1347 | unsigned max_threads; |
||
1348 | unsigned max_gs_threads; |
||
1349 | unsigned max_stack_entries; |
||
1350 | unsigned sx_num_of_sets; |
||
1351 | unsigned sx_max_export_size; |
||
1352 | unsigned sx_max_export_pos_size; |
||
1353 | unsigned sx_max_export_smx_size; |
||
1354 | unsigned max_hw_contexts; |
||
1355 | unsigned sq_num_cf_insts; |
||
1356 | unsigned sc_prim_fifo_size; |
||
1357 | unsigned sc_hiz_tile_fifo_size; |
||
1358 | unsigned sc_earlyz_tile_fifo_size; |
||
1359 | |||
1360 | unsigned num_shader_engines; |
||
1361 | unsigned num_shader_pipes_per_simd; |
||
1362 | unsigned num_tile_pipes; |
||
1363 | unsigned num_simds_per_se; |
||
1364 | unsigned num_backends_per_se; |
||
1365 | unsigned backend_disable_mask_per_asic; |
||
1366 | unsigned backend_map; |
||
1367 | unsigned num_texture_channel_caches; |
||
1368 | unsigned mem_max_burst_length_bytes; |
||
1369 | unsigned mem_row_size_in_kb; |
||
1370 | unsigned shader_engine_tile_size; |
||
1371 | unsigned num_gpus; |
||
1372 | unsigned multi_gpu_tile_size; |
||
1373 | |||
1374 | unsigned tile_config; |
||
1375 | }; |
||
1376 | |||
2997 | Serge | 1377 | struct si_asic { |
1378 | unsigned max_shader_engines; |
||
1379 | unsigned max_tile_pipes; |
||
1380 | unsigned max_cu_per_sh; |
||
1381 | unsigned max_sh_per_se; |
||
1382 | unsigned max_backends_per_se; |
||
1383 | unsigned max_texture_channel_caches; |
||
1384 | unsigned max_gprs; |
||
1385 | unsigned max_gs_threads; |
||
1386 | unsigned max_hw_contexts; |
||
1387 | unsigned sc_prim_fifo_size_frontend; |
||
1388 | unsigned sc_prim_fifo_size_backend; |
||
1389 | unsigned sc_hiz_tile_fifo_size; |
||
1390 | unsigned sc_earlyz_tile_fifo_size; |
||
1391 | |||
1392 | unsigned num_tile_pipes; |
||
1393 | unsigned num_backends_per_se; |
||
1394 | unsigned backend_disable_mask_per_asic; |
||
1395 | unsigned backend_map; |
||
1396 | unsigned num_texture_channel_caches; |
||
1397 | unsigned mem_max_burst_length_bytes; |
||
1398 | unsigned mem_row_size_in_kb; |
||
1399 | unsigned shader_engine_tile_size; |
||
1400 | unsigned num_gpus; |
||
1401 | unsigned multi_gpu_tile_size; |
||
1402 | |||
1403 | unsigned tile_config; |
||
1404 | }; |
||
1405 | |||
1117 | serge | 1406 | union radeon_asic_config { |
1407 | struct r300_asic r300; |
||
1179 | serge | 1408 | struct r100_asic r100; |
1409 | struct r600_asic r600; |
||
1410 | struct rv770_asic rv770; |
||
1963 | serge | 1411 | struct evergreen_asic evergreen; |
1412 | struct cayman_asic cayman; |
||
2997 | Serge | 1413 | struct si_asic si; |
1117 | serge | 1414 | }; |
1415 | |||
1416 | /* |
||
1963 | serge | 1417 | * asic initizalization from radeon_asic.c |
1418 | */ |
||
1419 | void radeon_agp_disable(struct radeon_device *rdev); |
||
1420 | int radeon_asic_init(struct radeon_device *rdev); |
||
1179 | serge | 1421 | |
1422 | |||
1423 | |||
2997 | Serge | 1424 | /* VRAM scratch page for HDP bug, default vram page */ |
1425 | struct r600_vram_scratch { |
||
1963 | serge | 1426 | struct radeon_bo *robj; |
1427 | volatile uint32_t *ptr; |
||
2997 | Serge | 1428 | u64 gpu_addr; |
1963 | serge | 1429 | }; |
1179 | serge | 1430 | |
2997 | Serge | 1431 | |
1117 | serge | 1432 | /* |
1433 | * Core structure, functions and helpers. |
||
1434 | */ |
||
1435 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
||
1436 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
||
1437 | |||
1438 | struct radeon_device { |
||
2997 | Serge | 1439 | struct device *dev; |
1117 | serge | 1440 | struct drm_device *ddev; |
1441 | struct pci_dev *pdev; |
||
2997 | Serge | 1442 | struct rw_semaphore exclusive_lock; |
1117 | serge | 1443 | /* ASIC */ |
1444 | union radeon_asic_config config; |
||
1445 | enum radeon_family family; |
||
1446 | unsigned long flags; |
||
1447 | int usec_timeout; |
||
1448 | enum radeon_pll_errata pll_errata; |
||
1449 | int num_gb_pipes; |
||
1413 | serge | 1450 | int num_z_pipes; |
1117 | serge | 1451 | int disp_priority; |
1452 | /* BIOS */ |
||
1453 | uint8_t *bios; |
||
1454 | bool is_atom_bios; |
||
1455 | uint16_t bios_header_start; |
||
1413 | serge | 1456 | struct radeon_bo *stollen_vga_memory; |
1117 | serge | 1457 | /* Register mmio */ |
1963 | serge | 1458 | resource_size_t rmmio_base; |
1459 | resource_size_t rmmio_size; |
||
2997 | Serge | 1460 | void __iomem *rmmio; |
1120 | serge | 1461 | radeon_rreg_t mc_rreg; |
1462 | radeon_wreg_t mc_wreg; |
||
1463 | radeon_rreg_t pll_rreg; |
||
1464 | radeon_wreg_t pll_wreg; |
||
1179 | serge | 1465 | uint32_t pcie_reg_mask; |
1120 | serge | 1466 | radeon_rreg_t pciep_rreg; |
1467 | radeon_wreg_t pciep_wreg; |
||
1963 | serge | 1468 | /* io port */ |
1469 | void __iomem *rio_mem; |
||
1470 | resource_size_t rio_mem_size; |
||
1120 | serge | 1471 | struct radeon_clock clock; |
1117 | serge | 1472 | struct radeon_mc mc; |
1473 | struct radeon_gart gart; |
||
1474 | struct radeon_mode_info mode_info; |
||
1475 | struct radeon_scratch scratch; |
||
1321 | serge | 1476 | struct radeon_mman mman; |
2997 | Serge | 1477 | struct radeon_fence_driver fence_drv[RADEON_NUM_RINGS]; |
1478 | wait_queue_head_t fence_queue; |
||
1479 | struct mutex ring_lock; |
||
1480 | struct radeon_ring ring[RADEON_NUM_RINGS]; |
||
1481 | bool ib_pool_ready; |
||
1482 | struct radeon_sa_manager ring_tmp_bo; |
||
1963 | serge | 1483 | struct radeon_irq irq; |
1117 | serge | 1484 | struct radeon_asic *asic; |
1126 | serge | 1485 | struct radeon_gem gem; |
1179 | serge | 1486 | struct radeon_pm pm; |
1487 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
||
1117 | serge | 1488 | struct radeon_wb wb; |
1179 | serge | 1489 | struct radeon_dummy_page dummy_page; |
1117 | serge | 1490 | bool shutdown; |
1491 | bool suspend; |
||
1179 | serge | 1492 | bool need_dma32; |
1493 | bool accel_working; |
||
1494 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
||
1495 | const struct firmware *me_fw; /* all family ME firmware */ |
||
1496 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
||
1403 | serge | 1497 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
1963 | serge | 1498 | const struct firmware *mc_fw; /* NI MC firmware */ |
2997 | Serge | 1499 | const struct firmware *ce_fw; /* SI CE firmware */ |
1179 | serge | 1500 | struct r600_blit r600_blit; |
2997 | Serge | 1501 | struct r600_vram_scratch vram_scratch; |
1268 | serge | 1502 | int msi_enabled; /* msi enabled */ |
2004 | serge | 1503 | struct r600_ih ih; /* r6/700 interrupt ring */ |
2997 | Serge | 1504 | struct si_rlc rlc; |
1963 | serge | 1505 | // struct work_struct hotplug_work; |
2997 | Serge | 1506 | // struct work_struct audio_work; |
1430 | serge | 1507 | int num_crtc; /* number of crtcs */ |
1630 | serge | 1508 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
1963 | serge | 1509 | bool audio_enabled; |
2997 | Serge | 1510 | // struct r600_audio audio_status; /* audio stuff */ |
1511 | // struct notifier_block acpi_nb; |
||
1512 | /* only one userspace can use Hyperz features or CMASK at a time */ |
||
1513 | // struct drm_file *hyperz_filp; |
||
1514 | // struct drm_file *cmask_filp; |
||
1963 | serge | 1515 | /* i2c buses */ |
1516 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; |
||
2997 | Serge | 1517 | /* debugfs */ |
1518 | // struct radeon_debugfs debugfs[RADEON_DEBUGFS_MAX_COMPONENTS]; |
||
1519 | unsigned debugfs_count; |
||
1520 | /* virtual memory */ |
||
1521 | struct radeon_vm_manager vm_manager; |
||
1522 | struct mutex gpu_clock_mutex; |
||
1523 | /* ACPI interface */ |
||
1524 | // struct radeon_atif atif; |
||
1525 | // struct radeon_atcs atcs; |
||
1117 | serge | 1526 | }; |
1527 | |||
1528 | int radeon_device_init(struct radeon_device *rdev, |
||
1529 | struct drm_device *ddev, |
||
1530 | struct pci_dev *pdev, |
||
1531 | uint32_t flags); |
||
1532 | void radeon_device_fini(struct radeon_device *rdev); |
||
1533 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
||
1534 | |||
2997 | Serge | 1535 | uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg); |
1536 | void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v); |
||
1537 | u32 r100_io_rreg(struct radeon_device *rdev, u32 reg); |
||
1538 | void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v); |
||
1117 | serge | 1539 | |
1321 | serge | 1540 | /* |
1541 | * Cast helper |
||
1542 | */ |
||
1543 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) |
||
1117 | serge | 1544 | |
1545 | /* |
||
1546 | * Registers read & write functions. |
||
1547 | */ |
||
2997 | Serge | 1548 | #define RREG8(reg) readb((rdev->rmmio) + (reg)) |
1549 | #define WREG8(reg, v) writeb(v, (rdev->rmmio) + (reg)) |
||
1550 | #define RREG16(reg) readw((rdev->rmmio) + (reg)) |
||
1551 | #define WREG16(reg, v) writew(v, (rdev->rmmio) + (reg)) |
||
1179 | serge | 1552 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
2004 | serge | 1553 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) |
1179 | serge | 1554 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
1117 | serge | 1555 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1556 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
||
1557 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
||
1558 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
||
1559 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
||
1560 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
||
1179 | serge | 1561 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
1562 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
||
1430 | serge | 1563 | #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) |
1564 | #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) |
||
1117 | serge | 1565 | #define WREG32_P(reg, val, mask) \ |
1566 | do { \ |
||
1567 | uint32_t tmp_ = RREG32(reg); \ |
||
1568 | tmp_ &= (mask); \ |
||
1569 | tmp_ |= ((val) & ~(mask)); \ |
||
1570 | WREG32(reg, tmp_); \ |
||
1571 | } while (0) |
||
1572 | #define WREG32_PLL_P(reg, val, mask) \ |
||
1573 | do { \ |
||
1574 | uint32_t tmp_ = RREG32_PLL(reg); \ |
||
1575 | tmp_ &= (mask); \ |
||
1576 | tmp_ |= ((val) & ~(mask)); \ |
||
1577 | WREG32_PLL(reg, tmp_); \ |
||
1578 | } while (0) |
||
1963 | serge | 1579 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
1580 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) |
||
1117 | serge | 1581 | |
1179 | serge | 1582 | /* |
1583 | * Indirect registers accessor |
||
1584 | */ |
||
1585 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
||
1586 | { |
||
1587 | uint32_t r; |
||
1117 | serge | 1588 | |
1179 | serge | 1589 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
1590 | r = RREG32(RADEON_PCIE_DATA); |
||
1591 | return r; |
||
1592 | } |
||
1593 | |||
1594 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
||
1595 | { |
||
1596 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
||
1597 | WREG32(RADEON_PCIE_DATA, (v)); |
||
1598 | } |
||
1599 | |||
1600 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
||
1601 | |||
1602 | |||
1117 | serge | 1603 | /* |
1604 | * ASICs helpers. |
||
1605 | */ |
||
1179 | serge | 1606 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
1607 | (rdev->pdev->device == 0x5969)) |
||
1117 | serge | 1608 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
1609 | (rdev->family == CHIP_RV200) || \ |
||
1610 | (rdev->family == CHIP_RS100) || \ |
||
1611 | (rdev->family == CHIP_RS200) || \ |
||
1612 | (rdev->family == CHIP_RV250) || \ |
||
1613 | (rdev->family == CHIP_RV280) || \ |
||
1614 | (rdev->family == CHIP_RS300)) |
||
1615 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
||
1616 | (rdev->family == CHIP_RV350) || \ |
||
1617 | (rdev->family == CHIP_R350) || \ |
||
1618 | (rdev->family == CHIP_RV380) || \ |
||
1619 | (rdev->family == CHIP_R420) || \ |
||
1620 | (rdev->family == CHIP_R423) || \ |
||
1621 | (rdev->family == CHIP_RV410) || \ |
||
1622 | (rdev->family == CHIP_RS400) || \ |
||
1623 | (rdev->family == CHIP_RS480)) |
||
1963 | serge | 1624 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
1625 | (rdev->ddev->pdev->device == 0x9443) || \ |
||
1626 | (rdev->ddev->pdev->device == 0x944B) || \ |
||
1627 | (rdev->ddev->pdev->device == 0x9506) || \ |
||
1628 | (rdev->ddev->pdev->device == 0x9509) || \ |
||
1629 | (rdev->ddev->pdev->device == 0x950F) || \ |
||
1630 | (rdev->ddev->pdev->device == 0x689C) || \ |
||
1631 | (rdev->ddev->pdev->device == 0x689D)) |
||
1117 | serge | 1632 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
1963 | serge | 1633 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
1634 | (rdev->family == CHIP_RS690) || \ |
||
1635 | (rdev->family == CHIP_RS740) || \ |
||
1636 | (rdev->family >= CHIP_R600)) |
||
1117 | serge | 1637 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
1638 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
||
1430 | serge | 1639 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
1963 | serge | 1640 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
1641 | (rdev->flags & RADEON_IS_IGP)) |
||
1642 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
||
2997 | Serge | 1643 | #define ASIC_IS_DCE6(rdev) ((rdev->family >= CHIP_ARUBA)) |
1644 | #define ASIC_IS_DCE61(rdev) ((rdev->family >= CHIP_ARUBA) && \ |
||
1645 | (rdev->flags & RADEON_IS_IGP)) |
||
1117 | serge | 1646 | |
1647 | /* |
||
1648 | * BIOS helpers. |
||
1649 | */ |
||
1650 | #define RBIOS8(i) (rdev->bios[i]) |
||
1651 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
||
1652 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
||
1653 | |||
1654 | int radeon_combios_init(struct radeon_device *rdev); |
||
1655 | void radeon_combios_fini(struct radeon_device *rdev); |
||
1656 | int radeon_atombios_init(struct radeon_device *rdev); |
||
1657 | void radeon_atombios_fini(struct radeon_device *rdev); |
||
1658 | |||
1659 | |||
1660 | /* |
||
1661 | * RING helpers. |
||
1662 | */ |
||
2997 | Serge | 1663 | #if DRM_DEBUG_CODE == 0 |
1664 | static inline void radeon_ring_write(struct radeon_ring *ring, uint32_t v) |
||
1117 | serge | 1665 | { |
2997 | Serge | 1666 | ring->ring[ring->wptr++] = v; |
1667 | ring->wptr &= ring->ptr_mask; |
||
1668 | ring->count_dw--; |
||
1669 | ring->ring_free_dw--; |
||
1670 | } |
||
1671 | #else |
||
1672 | /* With debugging this is just too big to inline */ |
||
1673 | void radeon_ring_write(struct radeon_ring *ring, uint32_t v); |
||
1117 | serge | 1674 | #endif |
1675 | |||
1676 | /* |
||
1677 | * ASICs macro. |
||
1678 | */ |
||
1679 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
||
1179 | serge | 1680 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
1681 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
||
1682 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
||
2997 | Serge | 1683 | #define radeon_cs_parse(rdev, r, p) (rdev)->asic->ring[(r)].cs_parse((p)) |
1179 | serge | 1684 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
1963 | serge | 1685 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
2997 | Serge | 1686 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart.tlb_flush((rdev)) |
1687 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart.set_page((rdev), (i), (p)) |
||
1688 | #define radeon_asic_vm_init(rdev) (rdev)->asic->vm.init((rdev)) |
||
1689 | #define radeon_asic_vm_fini(rdev) (rdev)->asic->vm.fini((rdev)) |
||
1690 | #define radeon_asic_vm_set_page(rdev, pe, addr, count, incr, flags) ((rdev)->asic->vm.set_page((rdev), (pe), (addr), (count), (incr), (flags))) |
||
1691 | #define radeon_ring_start(rdev, r, cp) (rdev)->asic->ring[(r)].ring_start((rdev), (cp)) |
||
1692 | #define radeon_ring_test(rdev, r, cp) (rdev)->asic->ring[(r)].ring_test((rdev), (cp)) |
||
1693 | #define radeon_ib_test(rdev, r, cp) (rdev)->asic->ring[(r)].ib_test((rdev), (cp)) |
||
1694 | #define radeon_ring_ib_execute(rdev, r, ib) (rdev)->asic->ring[(r)].ib_execute((rdev), (ib)) |
||
1695 | #define radeon_ring_ib_parse(rdev, r, ib) (rdev)->asic->ring[(r)].ib_parse((rdev), (ib)) |
||
1696 | #define radeon_ring_is_lockup(rdev, r, cp) (rdev)->asic->ring[(r)].is_lockup((rdev), (cp)) |
||
1697 | #define radeon_ring_vm_flush(rdev, r, vm) (rdev)->asic->ring[(r)].vm_flush((rdev), (r), (vm)) |
||
1698 | #define radeon_irq_set(rdev) (rdev)->asic->irq.set((rdev)) |
||
1699 | #define radeon_irq_process(rdev) (rdev)->asic->irq.process((rdev)) |
||
1700 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->display.get_vblank_counter((rdev), (crtc)) |
||
1701 | #define radeon_set_backlight_level(rdev, e, l) (rdev)->asic->display.set_backlight_level((e), (l)) |
||
1702 | #define radeon_get_backlight_level(rdev, e) (rdev)->asic->display.get_backlight_level((e)) |
||
1703 | #define radeon_fence_ring_emit(rdev, r, fence) (rdev)->asic->ring[(r)].emit_fence((rdev), (fence)) |
||
1704 | #define radeon_semaphore_ring_emit(rdev, r, cp, semaphore, emit_wait) (rdev)->asic->ring[(r)].emit_semaphore((rdev), (cp), (semaphore), (emit_wait)) |
||
1705 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy.blit((rdev), (s), (d), (np), (f)) |
||
1706 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy.dma((rdev), (s), (d), (np), (f)) |
||
1707 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy.copy((rdev), (s), (d), (np), (f)) |
||
1708 | #define radeon_copy_blit_ring_index(rdev) (rdev)->asic->copy.blit_ring_index |
||
1709 | #define radeon_copy_dma_ring_index(rdev) (rdev)->asic->copy.dma_ring_index |
||
1710 | #define radeon_copy_ring_index(rdev) (rdev)->asic->copy.copy_ring_index |
||
1711 | #define radeon_get_engine_clock(rdev) (rdev)->asic->pm.get_engine_clock((rdev)) |
||
1712 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->pm.set_engine_clock((rdev), (e)) |
||
1713 | #define radeon_get_memory_clock(rdev) (rdev)->asic->pm.get_memory_clock((rdev)) |
||
1714 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->pm.set_memory_clock((rdev), (e)) |
||
1715 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->pm.get_pcie_lanes((rdev)) |
||
1716 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->pm.set_pcie_lanes((rdev), (l)) |
||
1717 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->pm.set_clock_gating((rdev), (e)) |
||
1718 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f), (p), (o), (s))) |
||
1719 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->surface.clear_reg((rdev), (r))) |
||
1720 | #define radeon_bandwidth_update(rdev) (rdev)->asic->display.bandwidth_update((rdev)) |
||
1721 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd.init((rdev)) |
||
1722 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd.fini((rdev)) |
||
1723 | #define radeon_hpd_sense(rdev, h) (rdev)->asic->hpd.sense((rdev), (h)) |
||
1724 | #define radeon_hpd_set_polarity(rdev, h) (rdev)->asic->hpd.set_polarity((rdev), (h)) |
||
1963 | serge | 1725 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
2997 | Serge | 1726 | #define radeon_pm_misc(rdev) (rdev)->asic->pm.misc((rdev)) |
1727 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm.prepare((rdev)) |
||
1728 | #define radeon_pm_finish(rdev) (rdev)->asic->pm.finish((rdev)) |
||
1729 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm.init_profile((rdev)) |
||
1730 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm.get_dynpm_state((rdev)) |
||
1731 | #define radeon_pre_page_flip(rdev, crtc) (rdev)->asic->pflip.pre_page_flip((rdev), (crtc)) |
||
1732 | #define radeon_page_flip(rdev, crtc, base) (rdev)->asic->pflip.page_flip((rdev), (crtc), (base)) |
||
1733 | #define radeon_post_page_flip(rdev, crtc) (rdev)->asic->pflip.post_page_flip((rdev), (crtc)) |
||
1734 | #define radeon_wait_for_vblank(rdev, crtc) (rdev)->asic->display.wait_for_vblank((rdev), (crtc)) |
||
1735 | #define radeon_mc_wait_for_idle(rdev) (rdev)->asic->mc_wait_for_idle((rdev)) |
||
1117 | serge | 1736 | |
1179 | serge | 1737 | /* Common functions */ |
1403 | serge | 1738 | /* AGP */ |
1963 | serge | 1739 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
1403 | serge | 1740 | extern void radeon_agp_disable(struct radeon_device *rdev); |
1179 | serge | 1741 | extern int radeon_modeset_init(struct radeon_device *rdev); |
1742 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
||
1743 | extern bool radeon_card_posted(struct radeon_device *rdev); |
||
1963 | serge | 1744 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
1745 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
||
1321 | serge | 1746 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
1179 | serge | 1747 | extern void radeon_scratch_init(struct radeon_device *rdev); |
1963 | serge | 1748 | extern void radeon_wb_fini(struct radeon_device *rdev); |
1749 | extern int radeon_wb_init(struct radeon_device *rdev); |
||
1750 | extern void radeon_wb_disable(struct radeon_device *rdev); |
||
1179 | serge | 1751 | extern void radeon_surface_init(struct radeon_device *rdev); |
1752 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
||
1221 | serge | 1753 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
1754 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
||
1321 | serge | 1755 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
1403 | serge | 1756 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
1430 | serge | 1757 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
1758 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
||
1759 | extern int radeon_resume_kms(struct drm_device *dev); |
||
1760 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); |
||
1963 | serge | 1761 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
1117 | serge | 1762 | |
1963 | serge | 1763 | /* |
2997 | Serge | 1764 | * vm |
1765 | */ |
||
1766 | int radeon_vm_manager_init(struct radeon_device *rdev); |
||
1767 | void radeon_vm_manager_fini(struct radeon_device *rdev); |
||
1768 | void radeon_vm_init(struct radeon_device *rdev, struct radeon_vm *vm); |
||
1769 | void radeon_vm_fini(struct radeon_device *rdev, struct radeon_vm *vm); |
||
1770 | int radeon_vm_alloc_pt(struct radeon_device *rdev, struct radeon_vm *vm); |
||
1771 | void radeon_vm_add_to_lru(struct radeon_device *rdev, struct radeon_vm *vm); |
||
1772 | struct radeon_fence *radeon_vm_grab_id(struct radeon_device *rdev, |
||
1773 | struct radeon_vm *vm, int ring); |
||
1774 | void radeon_vm_fence(struct radeon_device *rdev, |
||
1775 | struct radeon_vm *vm, |
||
1776 | struct radeon_fence *fence); |
||
1777 | uint64_t radeon_vm_map_gart(struct radeon_device *rdev, uint64_t addr); |
||
1778 | int radeon_vm_bo_update_pte(struct radeon_device *rdev, |
||
1779 | struct radeon_vm *vm, |
||
1780 | struct radeon_bo *bo, |
||
1781 | struct ttm_mem_reg *mem); |
||
1782 | void radeon_vm_bo_invalidate(struct radeon_device *rdev, |
||
1783 | struct radeon_bo *bo); |
||
1784 | struct radeon_bo_va *radeon_vm_bo_find(struct radeon_vm *vm, |
||
1785 | struct radeon_bo *bo); |
||
1786 | struct radeon_bo_va *radeon_vm_bo_add(struct radeon_device *rdev, |
||
1787 | struct radeon_vm *vm, |
||
1788 | struct radeon_bo *bo); |
||
1789 | int radeon_vm_bo_set_addr(struct radeon_device *rdev, |
||
1790 | struct radeon_bo_va *bo_va, |
||
1791 | uint64_t offset, |
||
1792 | uint32_t flags); |
||
1793 | int radeon_vm_bo_rmv(struct radeon_device *rdev, |
||
1794 | struct radeon_bo_va *bo_va); |
||
1795 | |||
1796 | /* audio */ |
||
1797 | void r600_audio_update_hdmi(struct work_struct *work); |
||
1798 | |||
1799 | /* |
||
1800 | * R600 vram scratch functions |
||
1801 | */ |
||
1802 | int r600_vram_scratch_init(struct radeon_device *rdev); |
||
1803 | void r600_vram_scratch_fini(struct radeon_device *rdev); |
||
1804 | |||
1805 | /* |
||
1806 | * r600 cs checking helper |
||
1807 | */ |
||
1808 | unsigned r600_mip_minify(unsigned size, unsigned level); |
||
1809 | bool r600_fmt_is_valid_color(u32 format); |
||
1810 | bool r600_fmt_is_valid_texture(u32 format, enum radeon_family family); |
||
1811 | int r600_fmt_get_blocksize(u32 format); |
||
1812 | int r600_fmt_get_nblocksx(u32 format, u32 w); |
||
1813 | int r600_fmt_get_nblocksy(u32 format, u32 h); |
||
1814 | |||
1815 | /* |
||
1963 | serge | 1816 | * r600 functions used by radeon_encoder.c |
1817 | */ |
||
2997 | Serge | 1818 | struct radeon_hdmi_acr { |
1819 | u32 clock; |
||
1820 | |||
1821 | int n_32khz; |
||
1822 | int cts_32khz; |
||
1823 | |||
1824 | int n_44_1khz; |
||
1825 | int cts_44_1khz; |
||
1826 | |||
1827 | int n_48khz; |
||
1828 | int cts_48khz; |
||
1829 | |||
1830 | }; |
||
1831 | |||
1832 | extern struct radeon_hdmi_acr r600_hdmi_acr(uint32_t clock); |
||
1833 | |||
1963 | serge | 1834 | extern void r600_hdmi_enable(struct drm_encoder *encoder); |
1835 | extern void r600_hdmi_disable(struct drm_encoder *encoder); |
||
1836 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
||
2997 | Serge | 1837 | extern u32 r6xx_remap_render_backend(struct radeon_device *rdev, |
1838 | u32 tiling_pipe_num, |
||
1839 | u32 max_rb_num, |
||
1840 | u32 total_max_rb_num, |
||
1841 | u32 enabled_rb_mask); |
||
1179 | serge | 1842 | |
2997 | Serge | 1843 | /* |
1844 | * evergreen functions used by radeon_encoder.c |
||
1845 | */ |
||
1846 | |||
1847 | extern void evergreen_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
||
1848 | |||
1963 | serge | 1849 | extern int ni_init_microcode(struct radeon_device *rdev); |
1850 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
||
1221 | serge | 1851 | |
1963 | serge | 1852 | /* radeon_acpi.c */ |
1853 | #if defined(CONFIG_ACPI) |
||
1854 | extern int radeon_acpi_init(struct radeon_device *rdev); |
||
2997 | Serge | 1855 | extern void radeon_acpi_fini(struct radeon_device *rdev); |
1963 | serge | 1856 | #else |
1857 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } |
||
2997 | Serge | 1858 | static inline void radeon_acpi_fini(struct radeon_device *rdev) { } |
1963 | serge | 1859 | #endif |
1179 | serge | 1860 | |
1321 | serge | 1861 | #include "radeon_object.h" |
1179 | serge | 1862 | |
1117 | serge | 1863 | #define DRM_UDELAY(d) udelay(d) |
1864 | |||
1865 | resource_size_t |
||
1866 | drm_get_resource_start(struct drm_device *dev, unsigned int resource); |
||
1867 | resource_size_t |
||
1868 | drm_get_resource_len(struct drm_device *dev, unsigned int resource); |
||
1869 | |||
1239 | serge | 1870 | bool set_mode(struct drm_device *dev, struct drm_connector *connector, |
1403 | serge | 1871 | videomode_t *mode, bool strict); |
1117 | serge | 1872 | |
1179 | serge | 1873 | |
1963 | serge | 1874 | |
1117 | serge | 1875 | #endif><>><>><>><>><>><>><>=>>><>><>><> |