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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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28 | #ifndef __RADEON_H__ |
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29 | #define __RADEON_H__ |
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30 | |||
31 | /* TODO: Here are things that needs to be done : |
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32 | * - surface allocator & initializer : (bit like scratch reg) should |
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33 | * initialize HDP_ stuff on RS600, R600, R700 hw, well anythings |
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34 | * related to surface |
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35 | * - WB : write back stuff (do it bit like scratch reg things) |
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36 | * - Vblank : look at Jesse's rework and what we should do |
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37 | * - r600/r700: gart & cp |
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38 | * - cs : clean cs ioctl use bitmap & things like that. |
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39 | * - power management stuff |
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40 | * - Barrier in gart code |
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41 | * - Unmappabled vram ? |
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42 | * - TESTING, TESTING, TESTING |
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43 | */ |
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44 | |||
1221 | serge | 45 | /* Initialization path: |
46 | * We expect that acceleration initialization might fail for various |
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47 | * reasons even thought we work hard to make it works on most |
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48 | * configurations. In order to still have a working userspace in such |
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49 | * situation the init path must succeed up to the memory controller |
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50 | * initialization point. Failure before this point are considered as |
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51 | * fatal error. Here is the init callchain : |
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52 | * radeon_device_init perform common structure, mutex initialization |
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53 | * asic_init setup the GPU memory layout and perform all |
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54 | * one time initialization (failure in this |
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55 | * function are considered fatal) |
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56 | * asic_startup setup the GPU acceleration, in order to |
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57 | * follow guideline the first thing this |
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58 | * function should do is setting the GPU |
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59 | * memory controller (only MC setup failure |
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60 | * are considered as fatal) |
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61 | */ |
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62 | |||
1321 | serge | 63 | #include |
1221 | serge | 64 | |
1321 | serge | 65 | #include |
66 | #include |
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1221 | serge | 67 | |
1321 | serge | 68 | #include |
69 | #include |
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70 | #include |
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71 | #include |
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1221 | serge | 72 | |
2004 | serge | 73 | #include |
1120 | serge | 74 | #include |
1117 | serge | 75 | |
1120 | serge | 76 | #include |
1123 | serge | 77 | #include "drm_edid.h" |
1179 | serge | 78 | |
79 | #include "radeon_family.h" |
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1117 | serge | 80 | #include "radeon_mode.h" |
81 | #include "radeon_reg.h" |
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82 | |||
83 | #include |
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84 | |||
1963 | serge | 85 | extern unsigned long volatile jiffies; |
86 | |||
1179 | serge | 87 | /* |
88 | * Modules parameters. |
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89 | */ |
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90 | extern int radeon_no_wb; |
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1123 | serge | 91 | extern int radeon_modeset; |
1117 | serge | 92 | extern int radeon_dynclks; |
1123 | serge | 93 | extern int radeon_r4xx_atom; |
1128 | serge | 94 | extern int radeon_agpmode; |
95 | extern int radeon_vram_limit; |
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1117 | serge | 96 | extern int radeon_gart_size; |
1128 | serge | 97 | extern int radeon_benchmarking; |
1179 | serge | 98 | extern int radeon_testing; |
1123 | serge | 99 | extern int radeon_connector_table; |
1179 | serge | 100 | extern int radeon_tv; |
1403 | serge | 101 | extern int radeon_audio; |
1963 | serge | 102 | extern int radeon_disp_priority; |
103 | extern int radeon_hw_i2c; |
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104 | extern int radeon_pcie_gen2; |
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1430 | serge | 105 | typedef struct pm_message { |
106 | int event; |
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107 | } pm_message_t; |
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108 | |||
1233 | serge | 109 | typedef struct |
110 | { |
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111 | int width; |
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112 | int height; |
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113 | int bpp; |
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114 | int freq; |
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1321 | serge | 115 | }videomode_t; |
1179 | serge | 116 | |
117 | static inline uint8_t __raw_readb(const volatile void __iomem *addr) |
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118 | { |
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119 | return *(const volatile uint8_t __force *) addr; |
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120 | } |
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121 | |||
122 | static inline uint16_t __raw_readw(const volatile void __iomem *addr) |
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123 | { |
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124 | return *(const volatile uint16_t __force *) addr; |
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125 | } |
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126 | |||
127 | static inline uint32_t __raw_readl(const volatile void __iomem *addr) |
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128 | { |
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129 | return *(const volatile uint32_t __force *) addr; |
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130 | } |
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131 | |||
132 | #define readb __raw_readb |
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133 | #define readw __raw_readw |
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134 | #define readl __raw_readl |
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135 | |||
136 | |||
137 | |||
138 | static inline void __raw_writeb(uint8_t b, volatile void __iomem *addr) |
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139 | { |
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140 | *(volatile uint8_t __force *) addr = b; |
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141 | } |
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142 | |||
143 | static inline void __raw_writew(uint16_t b, volatile void __iomem *addr) |
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144 | { |
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145 | *(volatile uint16_t __force *) addr = b; |
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146 | } |
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147 | |||
148 | static inline void __raw_writel(uint32_t b, volatile void __iomem *addr) |
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149 | { |
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150 | *(volatile uint32_t __force *) addr = b; |
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151 | } |
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152 | |||
153 | static inline void __raw_writeq(__u64 b, volatile void __iomem *addr) |
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154 | { |
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155 | *(volatile __u64 *)addr = b; |
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156 | } |
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157 | |||
158 | #define writeb __raw_writeb |
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159 | #define writew __raw_writew |
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160 | #define writel __raw_writel |
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161 | #define writeq __raw_writeq |
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162 | |||
163 | |||
1963 | serge | 164 | static inline u32 ioread32(const volatile void __iomem *addr) |
165 | { |
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166 | return in32((u32)addr); |
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167 | } |
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168 | |||
169 | static inline void iowrite32(uint32_t b, volatile void __iomem *addr) |
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170 | { |
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171 | out32((u32)addr, b); |
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172 | } |
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173 | |||
174 | struct __wait_queue_head { |
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175 | spinlock_t lock; |
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176 | struct list_head task_list; |
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177 | }; |
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178 | typedef struct __wait_queue_head wait_queue_head_t; |
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179 | |||
180 | |||
1117 | serge | 181 | /* |
182 | * Copy from radeon_drv.h so we don't have to include both and have conflicting |
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183 | * symbol; |
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184 | */ |
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1120 | serge | 185 | #define RADEON_MAX_USEC_TIMEOUT 100000 /* 100 ms */ |
1963 | serge | 186 | #define RADEON_FENCE_JIFFIES_TIMEOUT (HZ / 2) |
1428 | serge | 187 | /* RADEON_IB_POOL_SIZE must be a power of 2 */ |
1120 | serge | 188 | #define RADEON_IB_POOL_SIZE 16 |
1117 | serge | 189 | #define RADEON_DEBUGFS_MAX_NUM_FILES 32 |
1120 | serge | 190 | #define RADEONFB_CONN_LIMIT 4 |
1179 | serge | 191 | #define RADEON_BIOS_NUM_SCRATCH 8 |
1117 | serge | 192 | |
193 | /* |
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194 | * Errata workarounds. |
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195 | */ |
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196 | enum radeon_pll_errata { |
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197 | CHIP_ERRATA_R300_CG = 0x00000001, |
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198 | CHIP_ERRATA_PLL_DUMMYREADS = 0x00000002, |
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199 | CHIP_ERRATA_PLL_DELAY = 0x00000004 |
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200 | }; |
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201 | |||
202 | |||
203 | struct radeon_device; |
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204 | |||
205 | |||
206 | /* |
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207 | * BIOS. |
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208 | */ |
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1430 | serge | 209 | #define ATRM_BIOS_PAGE 4096 |
210 | |||
211 | #if defined(CONFIG_VGA_SWITCHEROO) |
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212 | bool radeon_atrm_supported(struct pci_dev *pdev); |
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213 | int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len); |
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214 | #else |
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215 | static inline bool radeon_atrm_supported(struct pci_dev *pdev) |
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216 | { |
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217 | return false; |
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218 | } |
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219 | |||
220 | static inline int radeon_atrm_get_bios_chunk(uint8_t *bios, int offset, int len){ |
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221 | return -EINVAL; |
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222 | } |
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223 | #endif |
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1117 | serge | 224 | bool radeon_get_bios(struct radeon_device *rdev); |
225 | |||
1179 | serge | 226 | |
1117 | serge | 227 | /* |
1179 | serge | 228 | * Dummy page |
229 | */ |
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230 | struct radeon_dummy_page { |
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231 | struct page *page; |
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232 | dma_addr_t addr; |
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233 | }; |
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234 | int radeon_dummy_page_init(struct radeon_device *rdev); |
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235 | void radeon_dummy_page_fini(struct radeon_device *rdev); |
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236 | |||
237 | |||
238 | /* |
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1117 | serge | 239 | * Clocks |
240 | */ |
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241 | struct radeon_clock { |
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242 | struct radeon_pll p1pll; |
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243 | struct radeon_pll p2pll; |
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1430 | serge | 244 | struct radeon_pll dcpll; |
1117 | serge | 245 | struct radeon_pll spll; |
246 | struct radeon_pll mpll; |
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247 | /* 10 Khz units */ |
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248 | uint32_t default_mclk; |
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249 | uint32_t default_sclk; |
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1430 | serge | 250 | uint32_t default_dispclk; |
251 | uint32_t dp_extclk; |
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1963 | serge | 252 | uint32_t max_pixel_clock; |
1117 | serge | 253 | }; |
254 | |||
1268 | serge | 255 | /* |
256 | * Power management |
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257 | */ |
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258 | int radeon_pm_init(struct radeon_device *rdev); |
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1963 | serge | 259 | void radeon_pm_fini(struct radeon_device *rdev); |
1430 | serge | 260 | void radeon_pm_compute_clocks(struct radeon_device *rdev); |
1963 | serge | 261 | void radeon_pm_suspend(struct radeon_device *rdev); |
262 | void radeon_pm_resume(struct radeon_device *rdev); |
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1430 | serge | 263 | void radeon_combios_get_power_modes(struct radeon_device *rdev); |
264 | void radeon_atombios_get_power_modes(struct radeon_device *rdev); |
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1963 | serge | 265 | void radeon_atom_set_voltage(struct radeon_device *rdev, u16 voltage_level, u8 voltage_type); |
2004 | serge | 266 | int radeon_atom_get_max_vddc(struct radeon_device *rdev, u16 *voltage); |
1963 | serge | 267 | void rs690_pm_info(struct radeon_device *rdev); |
268 | extern int rv6xx_get_temp(struct radeon_device *rdev); |
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269 | extern int rv770_get_temp(struct radeon_device *rdev); |
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270 | extern int evergreen_get_temp(struct radeon_device *rdev); |
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271 | extern int sumo_get_temp(struct radeon_device *rdev); |
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1179 | serge | 272 | |
1117 | serge | 273 | /* |
274 | * Fences. |
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275 | */ |
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276 | struct radeon_fence_driver { |
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277 | uint32_t scratch_reg; |
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1321 | serge | 278 | atomic_t seq; |
1117 | serge | 279 | uint32_t last_seq; |
1963 | serge | 280 | unsigned long last_jiffies; |
281 | unsigned long last_timeout; |
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282 | wait_queue_head_t queue; |
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1321 | serge | 283 | rwlock_t lock; |
1120 | serge | 284 | struct list_head created; |
285 | struct list_head emited; |
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286 | struct list_head signaled; |
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1403 | serge | 287 | bool initialized; |
1117 | serge | 288 | }; |
289 | |||
290 | struct radeon_fence { |
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291 | struct radeon_device *rdev; |
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1321 | serge | 292 | struct kref kref; |
1120 | serge | 293 | struct list_head list; |
1117 | serge | 294 | /* protected by radeon_fence.lock */ |
295 | uint32_t seq; |
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296 | bool emited; |
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297 | bool signaled; |
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2005 | serge | 298 | evhandle_t evnt; |
1117 | serge | 299 | }; |
300 | |||
301 | int radeon_fence_driver_init(struct radeon_device *rdev); |
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302 | void radeon_fence_driver_fini(struct radeon_device *rdev); |
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303 | int radeon_fence_create(struct radeon_device *rdev, struct radeon_fence **fence); |
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304 | int radeon_fence_emit(struct radeon_device *rdev, struct radeon_fence *fence); |
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305 | void radeon_fence_process(struct radeon_device *rdev); |
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306 | bool radeon_fence_signaled(struct radeon_fence *fence); |
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307 | int radeon_fence_wait(struct radeon_fence *fence, bool interruptible); |
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308 | int radeon_fence_wait_next(struct radeon_device *rdev); |
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309 | int radeon_fence_wait_last(struct radeon_device *rdev); |
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310 | struct radeon_fence *radeon_fence_ref(struct radeon_fence *fence); |
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311 | void radeon_fence_unref(struct radeon_fence **fence); |
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312 | |||
1179 | serge | 313 | /* |
314 | * Tiling registers |
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315 | */ |
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316 | struct radeon_surface_reg { |
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1321 | serge | 317 | struct radeon_bo *bo; |
1179 | serge | 318 | }; |
1117 | serge | 319 | |
1179 | serge | 320 | #define RADEON_GEM_MAX_SURFACES 8 |
321 | |||
1117 | serge | 322 | /* |
1321 | serge | 323 | * TTM. |
1117 | serge | 324 | */ |
1321 | serge | 325 | struct radeon_mman { |
326 | struct ttm_bo_global_ref bo_global_ref; |
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1963 | serge | 327 | // struct drm_global_reference mem_global_ref; |
1403 | serge | 328 | struct ttm_bo_device bdev; |
1321 | serge | 329 | bool mem_global_referenced; |
1403 | serge | 330 | bool initialized; |
1321 | serge | 331 | }; |
1117 | serge | 332 | |
1321 | serge | 333 | struct radeon_bo { |
334 | /* Protected by gem.mutex */ |
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335 | struct list_head list; |
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336 | /* Protected by tbo.reserved */ |
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337 | u32 placements[3]; |
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338 | struct ttm_placement placement; |
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339 | struct ttm_buffer_object tbo; |
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340 | struct ttm_bo_kmap_obj kmap; |
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1404 | serge | 341 | unsigned pin_count; |
342 | void *kptr; |
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2007 | serge | 343 | void *uptr; |
1404 | serge | 344 | u32 cpu_addr; |
345 | u32 tiling_flags; |
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346 | u32 pitch; |
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347 | int surface_reg; |
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1321 | serge | 348 | /* Constant after initialization */ |
349 | struct radeon_device *rdev; |
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1963 | serge | 350 | struct drm_gem_object gem_base; |
1404 | serge | 351 | u32 domain; |
1321 | serge | 352 | }; |
1963 | serge | 353 | #define gem_to_radeon_bo(gobj) container_of((gobj), struct radeon_bo, gem_base) |
1321 | serge | 354 | |
355 | struct radeon_bo_list { |
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356 | struct radeon_bo *bo; |
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1117 | serge | 357 | uint64_t gpu_offset; |
358 | unsigned rdomain; |
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359 | unsigned wdomain; |
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1321 | serge | 360 | u32 tiling_flags; |
1117 | serge | 361 | }; |
362 | |||
1123 | serge | 363 | /* |
364 | * GEM objects. |
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365 | */ |
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366 | struct radeon_gem { |
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1630 | serge | 367 | struct mutex mutex; |
1123 | serge | 368 | struct list_head objects; |
369 | }; |
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1117 | serge | 370 | |
1126 | serge | 371 | int radeon_gem_init(struct radeon_device *rdev); |
372 | void radeon_gem_fini(struct radeon_device *rdev); |
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373 | int radeon_gem_object_create(struct radeon_device *rdev, int size, |
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374 | int alignment, int initial_domain, |
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375 | bool discardable, bool kernel, |
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376 | struct drm_gem_object **obj); |
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377 | int radeon_gem_object_pin(struct drm_gem_object *obj, uint32_t pin_domain, |
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378 | uint64_t *gpu_addr); |
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379 | void radeon_gem_object_unpin(struct drm_gem_object *obj); |
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1117 | serge | 380 | |
2004 | serge | 381 | int radeon_mode_dumb_create(struct drm_file *file_priv, |
382 | struct drm_device *dev, |
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383 | struct drm_mode_create_dumb *args); |
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384 | int radeon_mode_dumb_mmap(struct drm_file *filp, |
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385 | struct drm_device *dev, |
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386 | uint32_t handle, uint64_t *offset_p); |
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387 | int radeon_mode_dumb_destroy(struct drm_file *file_priv, |
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388 | struct drm_device *dev, |
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389 | uint32_t handle); |
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1117 | serge | 390 | |
391 | /* |
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392 | * GART structures, functions & helpers |
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393 | */ |
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394 | struct radeon_mc; |
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395 | |||
396 | struct radeon_gart_table_ram { |
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397 | volatile uint32_t *ptr; |
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398 | }; |
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399 | |||
400 | struct radeon_gart_table_vram { |
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1321 | serge | 401 | struct radeon_bo *robj; |
1117 | serge | 402 | volatile uint32_t *ptr; |
403 | }; |
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404 | |||
405 | union radeon_gart_table { |
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406 | struct radeon_gart_table_ram ram; |
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407 | struct radeon_gart_table_vram vram; |
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408 | }; |
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409 | |||
1268 | serge | 410 | #define RADEON_GPU_PAGE_SIZE 4096 |
1430 | serge | 411 | #define RADEON_GPU_PAGE_MASK (RADEON_GPU_PAGE_SIZE - 1) |
1268 | serge | 412 | |
1117 | serge | 413 | struct radeon_gart { |
414 | dma_addr_t table_addr; |
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415 | unsigned num_gpu_pages; |
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416 | unsigned num_cpu_pages; |
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417 | unsigned table_size; |
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418 | union radeon_gart_table table; |
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419 | struct page **pages; |
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420 | dma_addr_t *pages_addr; |
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1963 | serge | 421 | bool *ttm_alloced; |
1117 | serge | 422 | bool ready; |
423 | }; |
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424 | |||
425 | int radeon_gart_table_ram_alloc(struct radeon_device *rdev); |
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426 | void radeon_gart_table_ram_free(struct radeon_device *rdev); |
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427 | int radeon_gart_table_vram_alloc(struct radeon_device *rdev); |
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428 | void radeon_gart_table_vram_free(struct radeon_device *rdev); |
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429 | int radeon_gart_init(struct radeon_device *rdev); |
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430 | void radeon_gart_fini(struct radeon_device *rdev); |
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431 | void radeon_gart_unbind(struct radeon_device *rdev, unsigned offset, |
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432 | int pages); |
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1120 | serge | 433 | int radeon_gart_bind(struct radeon_device *rdev, unsigned offset, |
434 | int pages, u32_t *pagelist); |
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1117 | serge | 435 | |
436 | |||
437 | /* |
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438 | * GPU MC structures, functions & helpers |
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439 | */ |
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440 | struct radeon_mc { |
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441 | resource_size_t aper_size; |
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442 | resource_size_t aper_base; |
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443 | resource_size_t agp_base; |
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1179 | serge | 444 | /* for some chips with <= 32MB we need to lie |
445 | * about vram size near mc fb location */ |
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446 | u64 mc_vram_size; |
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1430 | serge | 447 | u64 visible_vram_size; |
1179 | serge | 448 | u64 gtt_size; |
449 | u64 gtt_start; |
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450 | u64 gtt_end; |
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451 | u64 vram_start; |
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452 | u64 vram_end; |
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1117 | serge | 453 | unsigned vram_width; |
1179 | serge | 454 | u64 real_vram_size; |
1117 | serge | 455 | int vram_mtrr; |
456 | bool vram_is_ddr; |
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1403 | serge | 457 | bool igp_sideport_enabled; |
1963 | serge | 458 | u64 gtt_base_align; |
1117 | serge | 459 | }; |
460 | |||
1403 | serge | 461 | bool radeon_combios_sideport_present(struct radeon_device *rdev); |
462 | bool radeon_atombios_sideport_present(struct radeon_device *rdev); |
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1117 | serge | 463 | |
464 | /* |
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465 | * GPU scratch registers structures, functions & helpers |
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466 | */ |
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467 | struct radeon_scratch { |
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468 | unsigned num_reg; |
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1963 | serge | 469 | uint32_t reg_base; |
1117 | serge | 470 | bool free[32]; |
471 | uint32_t reg[32]; |
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472 | }; |
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473 | |||
474 | int radeon_scratch_get(struct radeon_device *rdev, uint32_t *reg); |
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475 | void radeon_scratch_free(struct radeon_device *rdev, uint32_t reg); |
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476 | |||
477 | |||
478 | /* |
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479 | * IRQS. |
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480 | */ |
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1963 | serge | 481 | struct r500_irq_stat_regs { |
482 | u32 disp_int; |
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483 | }; |
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484 | |||
485 | struct r600_irq_stat_regs { |
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486 | u32 disp_int; |
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487 | u32 disp_int_cont; |
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488 | u32 disp_int_cont2; |
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489 | u32 d1grph_int; |
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490 | u32 d2grph_int; |
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491 | }; |
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492 | |||
493 | struct evergreen_irq_stat_regs { |
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494 | u32 disp_int; |
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495 | u32 disp_int_cont; |
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496 | u32 disp_int_cont2; |
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497 | u32 disp_int_cont3; |
||
498 | u32 disp_int_cont4; |
||
499 | u32 disp_int_cont5; |
||
500 | u32 d1grph_int; |
||
501 | u32 d2grph_int; |
||
502 | u32 d3grph_int; |
||
503 | u32 d4grph_int; |
||
504 | u32 d5grph_int; |
||
505 | u32 d6grph_int; |
||
506 | }; |
||
507 | |||
508 | union radeon_irq_stat_regs { |
||
509 | struct r500_irq_stat_regs r500; |
||
510 | struct r600_irq_stat_regs r600; |
||
511 | struct evergreen_irq_stat_regs evergreen; |
||
512 | }; |
||
513 | |||
1117 | serge | 514 | struct radeon_irq { |
515 | bool installed; |
||
516 | bool sw_int; |
||
517 | /* FIXME: use a define max crtc rather than hardcode it */ |
||
1963 | serge | 518 | bool crtc_vblank_int[6]; |
519 | bool pflip[6]; |
||
520 | wait_queue_head_t vblank_queue; |
||
1321 | serge | 521 | /* FIXME: use defines for max hpd/dacs */ |
522 | bool hpd[6]; |
||
1963 | serge | 523 | bool gui_idle; |
524 | bool gui_idle_acked; |
||
525 | wait_queue_head_t idle_queue; |
||
526 | /* FIXME: use defines for max HDMI blocks */ |
||
527 | bool hdmi[2]; |
||
1321 | serge | 528 | spinlock_t sw_lock; |
529 | int sw_refcount; |
||
1963 | serge | 530 | union radeon_irq_stat_regs stat_regs; |
531 | spinlock_t pflip_lock[6]; |
||
532 | int pflip_refcount[6]; |
||
1117 | serge | 533 | }; |
534 | |||
535 | int radeon_irq_kms_init(struct radeon_device *rdev); |
||
536 | void radeon_irq_kms_fini(struct radeon_device *rdev); |
||
1321 | serge | 537 | void radeon_irq_kms_sw_irq_get(struct radeon_device *rdev); |
538 | void radeon_irq_kms_sw_irq_put(struct radeon_device *rdev); |
||
2004 | serge | 539 | void radeon_irq_kms_pflip_irq_get(struct radeon_device *rdev, int crtc); |
540 | void radeon_irq_kms_pflip_irq_put(struct radeon_device *rdev, int crtc); |
||
1117 | serge | 541 | |
542 | /* |
||
543 | * CP & ring. |
||
544 | */ |
||
545 | struct radeon_ib { |
||
1403 | serge | 546 | struct list_head list; |
1428 | serge | 547 | unsigned idx; |
1403 | serge | 548 | uint64_t gpu_addr; |
1117 | serge | 549 | struct radeon_fence *fence; |
1403 | serge | 550 | uint32_t *ptr; |
551 | uint32_t length_dw; |
||
1428 | serge | 552 | bool free; |
1117 | serge | 553 | }; |
554 | |||
1179 | serge | 555 | /* |
556 | * locking - |
||
557 | * mutex protects scheduled_ibs, ready, alloc_bm |
||
558 | */ |
||
1117 | serge | 559 | struct radeon_ib_pool { |
1630 | serge | 560 | struct mutex mutex; |
1321 | serge | 561 | struct radeon_bo *robj; |
1430 | serge | 562 | struct list_head bogus_ib; |
1117 | serge | 563 | struct radeon_ib ibs[RADEON_IB_POOL_SIZE]; |
1403 | serge | 564 | bool ready; |
1428 | serge | 565 | unsigned head_id; |
1117 | serge | 566 | }; |
567 | |||
568 | struct radeon_cp { |
||
1321 | serge | 569 | struct radeon_bo *ring_obj; |
1117 | serge | 570 | volatile uint32_t *ring; |
1403 | serge | 571 | unsigned rptr; |
572 | unsigned wptr; |
||
573 | unsigned wptr_old; |
||
574 | unsigned ring_size; |
||
575 | unsigned ring_free_dw; |
||
576 | int count_dw; |
||
577 | uint64_t gpu_addr; |
||
578 | uint32_t align_mask; |
||
579 | uint32_t ptr_mask; |
||
1630 | serge | 580 | struct mutex mutex; |
1403 | serge | 581 | bool ready; |
1117 | serge | 582 | }; |
583 | |||
1321 | serge | 584 | /* |
585 | * R6xx+ IH ring |
||
586 | */ |
||
587 | struct r600_ih { |
||
588 | struct radeon_bo *ring_obj; |
||
589 | volatile uint32_t *ring; |
||
590 | unsigned rptr; |
||
591 | unsigned wptr; |
||
592 | unsigned wptr_old; |
||
593 | unsigned ring_size; |
||
594 | uint64_t gpu_addr; |
||
595 | uint32_t ptr_mask; |
||
596 | spinlock_t lock; |
||
597 | bool enabled; |
||
598 | }; |
||
599 | |||
1179 | serge | 600 | struct r600_blit { |
1630 | serge | 601 | struct mutex mutex; |
1321 | serge | 602 | struct radeon_bo *shader_obj; |
1179 | serge | 603 | u64 shader_gpu_addr; |
604 | u32 vs_offset, ps_offset; |
||
605 | u32 state_offset; |
||
606 | u32 state_len; |
||
607 | u32 vb_used, vb_total; |
||
608 | struct radeon_ib *vb_ib; |
||
609 | }; |
||
610 | |||
1117 | serge | 611 | int radeon_ib_get(struct radeon_device *rdev, struct radeon_ib **ib); |
612 | void radeon_ib_free(struct radeon_device *rdev, struct radeon_ib **ib); |
||
613 | int radeon_ib_schedule(struct radeon_device *rdev, struct radeon_ib *ib); |
||
614 | int radeon_ib_pool_init(struct radeon_device *rdev); |
||
615 | void radeon_ib_pool_fini(struct radeon_device *rdev); |
||
616 | int radeon_ib_test(struct radeon_device *rdev); |
||
1430 | serge | 617 | extern void radeon_ib_bogus_add(struct radeon_device *rdev, struct radeon_ib *ib); |
1117 | serge | 618 | /* Ring access between begin & end cannot sleep */ |
619 | void radeon_ring_free_size(struct radeon_device *rdev); |
||
1963 | serge | 620 | int radeon_ring_alloc(struct radeon_device *rdev, unsigned ndw); |
1117 | serge | 621 | int radeon_ring_lock(struct radeon_device *rdev, unsigned ndw); |
1963 | serge | 622 | void radeon_ring_commit(struct radeon_device *rdev); |
1117 | serge | 623 | void radeon_ring_unlock_commit(struct radeon_device *rdev); |
624 | void radeon_ring_unlock_undo(struct radeon_device *rdev); |
||
625 | int radeon_ring_test(struct radeon_device *rdev); |
||
626 | int radeon_ring_init(struct radeon_device *rdev, unsigned ring_size); |
||
627 | void radeon_ring_fini(struct radeon_device *rdev); |
||
628 | |||
629 | |||
630 | /* |
||
631 | * CS. |
||
632 | */ |
||
633 | struct radeon_cs_reloc { |
||
634 | // struct drm_gem_object *gobj; |
||
1321 | serge | 635 | struct radeon_bo *robj; |
1630 | serge | 636 | struct radeon_bo_list lobj; |
1403 | serge | 637 | uint32_t handle; |
638 | uint32_t flags; |
||
1117 | serge | 639 | }; |
640 | |||
641 | struct radeon_cs_chunk { |
||
642 | uint32_t chunk_id; |
||
643 | uint32_t length_dw; |
||
1221 | serge | 644 | int kpage_idx[2]; |
645 | uint32_t *kpage[2]; |
||
1117 | serge | 646 | uint32_t *kdata; |
1221 | serge | 647 | void __user *user_ptr; |
648 | int last_copied_page; |
||
649 | int last_page_index; |
||
1117 | serge | 650 | }; |
651 | |||
652 | struct radeon_cs_parser { |
||
1430 | serge | 653 | struct device *dev; |
1117 | serge | 654 | struct radeon_device *rdev; |
2004 | serge | 655 | struct drm_file *filp; |
1117 | serge | 656 | /* chunks */ |
657 | unsigned nchunks; |
||
658 | struct radeon_cs_chunk *chunks; |
||
659 | uint64_t *chunks_array; |
||
660 | /* IB */ |
||
661 | unsigned idx; |
||
662 | /* relocations */ |
||
663 | unsigned nrelocs; |
||
664 | struct radeon_cs_reloc *relocs; |
||
665 | struct radeon_cs_reloc **relocs_ptr; |
||
1120 | serge | 666 | struct list_head validated; |
1117 | serge | 667 | /* indices of various chunks */ |
668 | int chunk_ib_idx; |
||
669 | int chunk_relocs_idx; |
||
670 | struct radeon_ib *ib; |
||
671 | void *track; |
||
1179 | serge | 672 | unsigned family; |
1221 | serge | 673 | int parser_error; |
1117 | serge | 674 | }; |
675 | |||
1221 | serge | 676 | extern int radeon_cs_update_pages(struct radeon_cs_parser *p, int pg_idx); |
677 | extern int radeon_cs_finish_pages(struct radeon_cs_parser *p); |
||
678 | |||
679 | |||
680 | static inline u32 radeon_get_ib_value(struct radeon_cs_parser *p, int idx) |
||
681 | { |
||
682 | struct radeon_cs_chunk *ibc = &p->chunks[p->chunk_ib_idx]; |
||
683 | u32 pg_idx, pg_offset; |
||
684 | u32 idx_value = 0; |
||
685 | int new_page; |
||
686 | |||
687 | pg_idx = (idx * 4) / PAGE_SIZE; |
||
688 | pg_offset = (idx * 4) % PAGE_SIZE; |
||
689 | |||
690 | if (ibc->kpage_idx[0] == pg_idx) |
||
691 | return ibc->kpage[0][pg_offset/4]; |
||
692 | if (ibc->kpage_idx[1] == pg_idx) |
||
693 | return ibc->kpage[1][pg_offset/4]; |
||
694 | |||
695 | new_page = radeon_cs_update_pages(p, pg_idx); |
||
696 | if (new_page < 0) { |
||
697 | p->parser_error = new_page; |
||
698 | return 0; |
||
699 | } |
||
700 | |||
701 | idx_value = ibc->kpage[new_page][pg_offset/4]; |
||
702 | return idx_value; |
||
703 | } |
||
704 | |||
1117 | serge | 705 | struct radeon_cs_packet { |
706 | unsigned idx; |
||
707 | unsigned type; |
||
708 | unsigned reg; |
||
709 | unsigned opcode; |
||
710 | int count; |
||
711 | unsigned one_reg_wr; |
||
712 | }; |
||
713 | |||
714 | typedef int (*radeon_packet0_check_t)(struct radeon_cs_parser *p, |
||
715 | struct radeon_cs_packet *pkt, |
||
716 | unsigned idx, unsigned reg); |
||
717 | typedef int (*radeon_packet3_check_t)(struct radeon_cs_parser *p, |
||
718 | struct radeon_cs_packet *pkt); |
||
719 | |||
720 | |||
721 | /* |
||
722 | * AGP |
||
723 | */ |
||
724 | int radeon_agp_init(struct radeon_device *rdev); |
||
1321 | serge | 725 | void radeon_agp_resume(struct radeon_device *rdev); |
1963 | serge | 726 | void radeon_agp_suspend(struct radeon_device *rdev); |
1117 | serge | 727 | void radeon_agp_fini(struct radeon_device *rdev); |
728 | |||
729 | |||
730 | /* |
||
731 | * Writeback |
||
732 | */ |
||
733 | struct radeon_wb { |
||
1321 | serge | 734 | struct radeon_bo *wb_obj; |
1117 | serge | 735 | volatile uint32_t *wb; |
736 | uint64_t gpu_addr; |
||
1963 | serge | 737 | bool enabled; |
738 | bool use_event; |
||
1117 | serge | 739 | }; |
740 | |||
1963 | serge | 741 | #define RADEON_WB_SCRATCH_OFFSET 0 |
742 | #define RADEON_WB_CP_RPTR_OFFSET 1024 |
||
743 | #define RADEON_WB_CP1_RPTR_OFFSET 1280 |
||
744 | #define RADEON_WB_CP2_RPTR_OFFSET 1536 |
||
745 | #define R600_WB_IH_WPTR_OFFSET 2048 |
||
746 | #define R600_WB_EVENT_OFFSET 3072 |
||
747 | |||
1179 | serge | 748 | /** |
749 | * struct radeon_pm - power management datas |
||
750 | * @max_bandwidth: maximum bandwidth the gpu has (MByte/s) |
||
751 | * @igp_sideport_mclk: sideport memory clock Mhz (rs690,rs740,rs780,rs880) |
||
752 | * @igp_system_mclk: system clock Mhz (rs690,rs740,rs780,rs880) |
||
753 | * @igp_ht_link_clk: ht link clock Mhz (rs690,rs740,rs780,rs880) |
||
754 | * @igp_ht_link_width: ht link width in bits (rs690,rs740,rs780,rs880) |
||
755 | * @k8_bandwidth: k8 bandwidth the gpu has (MByte/s) (IGP) |
||
756 | * @sideport_bandwidth: sideport bandwidth the gpu has (MByte/s) (IGP) |
||
757 | * @ht_bandwidth: ht bandwidth the gpu has (MByte/s) (IGP) |
||
758 | * @core_bandwidth: core GPU bandwidth the gpu has (MByte/s) (IGP) |
||
1963 | serge | 759 | * @sclk: GPU clock Mhz (core bandwidth depends of this clock) |
1179 | serge | 760 | * @needed_bandwidth: current bandwidth needs |
761 | * |
||
762 | * It keeps track of various data needed to take powermanagement decision. |
||
1963 | serge | 763 | * Bandwidth need is used to determine minimun clock of the GPU and memory. |
1179 | serge | 764 | * Equation between gpu/memory clock and available bandwidth is hw dependent |
765 | * (type of memory, bus size, efficiency, ...) |
||
766 | */ |
||
1963 | serge | 767 | |
768 | enum radeon_pm_method { |
||
769 | PM_METHOD_PROFILE, |
||
770 | PM_METHOD_DYNPM, |
||
1430 | serge | 771 | }; |
1963 | serge | 772 | |
773 | enum radeon_dynpm_state { |
||
774 | DYNPM_STATE_DISABLED, |
||
775 | DYNPM_STATE_MINIMUM, |
||
776 | DYNPM_STATE_PAUSED, |
||
777 | DYNPM_STATE_ACTIVE, |
||
778 | DYNPM_STATE_SUSPENDED, |
||
1430 | serge | 779 | }; |
1963 | serge | 780 | enum radeon_dynpm_action { |
781 | DYNPM_ACTION_NONE, |
||
782 | DYNPM_ACTION_MINIMUM, |
||
783 | DYNPM_ACTION_DOWNCLOCK, |
||
784 | DYNPM_ACTION_UPCLOCK, |
||
785 | DYNPM_ACTION_DEFAULT |
||
786 | }; |
||
1430 | serge | 787 | |
788 | enum radeon_voltage_type { |
||
789 | VOLTAGE_NONE = 0, |
||
790 | VOLTAGE_GPIO, |
||
791 | VOLTAGE_VDDC, |
||
792 | VOLTAGE_SW |
||
793 | }; |
||
794 | |||
795 | enum radeon_pm_state_type { |
||
796 | POWER_STATE_TYPE_DEFAULT, |
||
797 | POWER_STATE_TYPE_POWERSAVE, |
||
798 | POWER_STATE_TYPE_BATTERY, |
||
799 | POWER_STATE_TYPE_BALANCED, |
||
800 | POWER_STATE_TYPE_PERFORMANCE, |
||
801 | }; |
||
802 | |||
1963 | serge | 803 | enum radeon_pm_profile_type { |
804 | PM_PROFILE_DEFAULT, |
||
805 | PM_PROFILE_AUTO, |
||
806 | PM_PROFILE_LOW, |
||
807 | PM_PROFILE_MID, |
||
808 | PM_PROFILE_HIGH, |
||
1430 | serge | 809 | }; |
810 | |||
1963 | serge | 811 | #define PM_PROFILE_DEFAULT_IDX 0 |
812 | #define PM_PROFILE_LOW_SH_IDX 1 |
||
813 | #define PM_PROFILE_MID_SH_IDX 2 |
||
814 | #define PM_PROFILE_HIGH_SH_IDX 3 |
||
815 | #define PM_PROFILE_LOW_MH_IDX 4 |
||
816 | #define PM_PROFILE_MID_MH_IDX 5 |
||
817 | #define PM_PROFILE_HIGH_MH_IDX 6 |
||
818 | #define PM_PROFILE_MAX 7 |
||
819 | |||
820 | struct radeon_pm_profile { |
||
821 | int dpms_off_ps_idx; |
||
822 | int dpms_on_ps_idx; |
||
823 | int dpms_off_cm_idx; |
||
824 | int dpms_on_cm_idx; |
||
825 | }; |
||
826 | |||
827 | enum radeon_int_thermal_type { |
||
828 | THERMAL_TYPE_NONE, |
||
829 | THERMAL_TYPE_RV6XX, |
||
830 | THERMAL_TYPE_RV770, |
||
831 | THERMAL_TYPE_EVERGREEN, |
||
832 | THERMAL_TYPE_SUMO, |
||
833 | THERMAL_TYPE_NI, |
||
834 | }; |
||
835 | |||
1430 | serge | 836 | struct radeon_voltage { |
837 | enum radeon_voltage_type type; |
||
838 | /* gpio voltage */ |
||
839 | struct radeon_gpio_rec gpio; |
||
840 | u32 delay; /* delay in usec from voltage drop to sclk change */ |
||
841 | bool active_high; /* voltage drop is active when bit is high */ |
||
842 | /* VDDC voltage */ |
||
843 | u8 vddc_id; /* index into vddc voltage table */ |
||
844 | u8 vddci_id; /* index into vddci voltage table */ |
||
845 | bool vddci_enabled; |
||
846 | /* r6xx+ sw */ |
||
1963 | serge | 847 | u16 voltage; |
848 | /* evergreen+ vddci */ |
||
849 | u16 vddci; |
||
1430 | serge | 850 | }; |
851 | |||
1963 | serge | 852 | /* clock mode flags */ |
853 | #define RADEON_PM_MODE_NO_DISPLAY (1 << 0) |
||
1430 | serge | 854 | |
855 | struct radeon_pm_clock_info { |
||
856 | /* memory clock */ |
||
857 | u32 mclk; |
||
858 | /* engine clock */ |
||
859 | u32 sclk; |
||
860 | /* voltage info */ |
||
861 | struct radeon_voltage voltage; |
||
1963 | serge | 862 | /* standardized clock flags */ |
1430 | serge | 863 | u32 flags; |
864 | }; |
||
865 | |||
1963 | serge | 866 | /* state flags */ |
867 | #define RADEON_PM_STATE_SINGLE_DISPLAY_ONLY (1 << 0) |
||
868 | |||
1430 | serge | 869 | struct radeon_power_state { |
870 | enum radeon_pm_state_type type; |
||
871 | /* XXX: use a define for num clock modes */ |
||
872 | struct radeon_pm_clock_info clock_info[8]; |
||
873 | /* number of valid clock modes in this power state */ |
||
874 | int num_clock_modes; |
||
875 | struct radeon_pm_clock_info *default_clock_mode; |
||
1963 | serge | 876 | /* standardized state flags */ |
877 | u32 flags; |
||
878 | u32 misc; /* vbios specific flags */ |
||
879 | u32 misc2; /* vbios specific flags */ |
||
880 | int pcie_lanes; /* pcie lanes */ |
||
1430 | serge | 881 | }; |
882 | |||
883 | /* |
||
884 | * Some modes are overclocked by very low value, accept them |
||
885 | */ |
||
886 | #define RADEON_MODE_OVERCLOCK_MARGIN 500 /* 5 MHz */ |
||
887 | |||
1179 | serge | 888 | struct radeon_pm { |
1630 | serge | 889 | struct mutex mutex; |
1963 | serge | 890 | u32 active_crtcs; |
891 | int active_crtc_count; |
||
1430 | serge | 892 | int req_vblank; |
1963 | serge | 893 | bool vblank_sync; |
894 | bool gui_idle; |
||
1179 | serge | 895 | fixed20_12 max_bandwidth; |
896 | fixed20_12 igp_sideport_mclk; |
||
897 | fixed20_12 igp_system_mclk; |
||
898 | fixed20_12 igp_ht_link_clk; |
||
899 | fixed20_12 igp_ht_link_width; |
||
900 | fixed20_12 k8_bandwidth; |
||
901 | fixed20_12 sideport_bandwidth; |
||
902 | fixed20_12 ht_bandwidth; |
||
903 | fixed20_12 core_bandwidth; |
||
904 | fixed20_12 sclk; |
||
1963 | serge | 905 | fixed20_12 mclk; |
1179 | serge | 906 | fixed20_12 needed_bandwidth; |
1963 | serge | 907 | struct radeon_power_state *power_state; |
1430 | serge | 908 | /* number of valid power states */ |
909 | int num_power_states; |
||
1963 | serge | 910 | int current_power_state_index; |
911 | int current_clock_mode_index; |
||
912 | int requested_power_state_index; |
||
913 | int requested_clock_mode_index; |
||
914 | int default_power_state_index; |
||
915 | u32 current_sclk; |
||
916 | u32 current_mclk; |
||
917 | u16 current_vddc; |
||
918 | u16 current_vddci; |
||
919 | u32 default_sclk; |
||
920 | u32 default_mclk; |
||
921 | u16 default_vddc; |
||
922 | u16 default_vddci; |
||
923 | struct radeon_i2c_chan *i2c_bus; |
||
924 | /* selected pm method */ |
||
925 | enum radeon_pm_method pm_method; |
||
926 | /* dynpm power management */ |
||
927 | // struct delayed_work dynpm_idle_work; |
||
928 | enum radeon_dynpm_state dynpm_state; |
||
929 | enum radeon_dynpm_action dynpm_planned_action; |
||
930 | unsigned long dynpm_action_timeout; |
||
931 | bool dynpm_can_upclock; |
||
932 | bool dynpm_can_downclock; |
||
933 | /* profile-based power management */ |
||
934 | enum radeon_pm_profile_type profile; |
||
935 | int profile_index; |
||
936 | struct radeon_pm_profile profiles[PM_PROFILE_MAX]; |
||
937 | /* internal thermal controller on rv6xx+ */ |
||
938 | enum radeon_int_thermal_type int_thermal_type; |
||
939 | struct device *int_hwmon_dev; |
||
1179 | serge | 940 | }; |
1117 | serge | 941 | |
942 | /* |
||
943 | * ASIC specific functions. |
||
944 | */ |
||
945 | struct radeon_asic { |
||
946 | int (*init)(struct radeon_device *rdev); |
||
1179 | serge | 947 | void (*fini)(struct radeon_device *rdev); |
948 | int (*resume)(struct radeon_device *rdev); |
||
949 | int (*suspend)(struct radeon_device *rdev); |
||
950 | void (*vga_set_state)(struct radeon_device *rdev, bool state); |
||
1963 | serge | 951 | bool (*gpu_is_lockup)(struct radeon_device *rdev); |
952 | int (*asic_reset)(struct radeon_device *rdev); |
||
1117 | serge | 953 | void (*gart_tlb_flush)(struct radeon_device *rdev); |
954 | int (*gart_set_page)(struct radeon_device *rdev, int i, uint64_t addr); |
||
955 | int (*cp_init)(struct radeon_device *rdev, unsigned ring_size); |
||
956 | void (*cp_fini)(struct radeon_device *rdev); |
||
957 | void (*cp_disable)(struct radeon_device *rdev); |
||
1179 | serge | 958 | void (*cp_commit)(struct radeon_device *rdev); |
1117 | serge | 959 | void (*ring_start)(struct radeon_device *rdev); |
1179 | serge | 960 | int (*ring_test)(struct radeon_device *rdev); |
961 | void (*ring_ib_execute)(struct radeon_device *rdev, struct radeon_ib *ib); |
||
1117 | serge | 962 | int (*irq_set)(struct radeon_device *rdev); |
963 | int (*irq_process)(struct radeon_device *rdev); |
||
1179 | serge | 964 | u32 (*get_vblank_counter)(struct radeon_device *rdev, int crtc); |
1117 | serge | 965 | void (*fence_ring_emit)(struct radeon_device *rdev, struct radeon_fence *fence); |
966 | int (*cs_parse)(struct radeon_cs_parser *p); |
||
967 | int (*copy_blit)(struct radeon_device *rdev, |
||
968 | uint64_t src_offset, |
||
969 | uint64_t dst_offset, |
||
970 | unsigned num_pages, |
||
971 | struct radeon_fence *fence); |
||
972 | int (*copy_dma)(struct radeon_device *rdev, |
||
973 | uint64_t src_offset, |
||
974 | uint64_t dst_offset, |
||
975 | unsigned num_pages, |
||
976 | struct radeon_fence *fence); |
||
977 | int (*copy)(struct radeon_device *rdev, |
||
978 | uint64_t src_offset, |
||
979 | uint64_t dst_offset, |
||
980 | unsigned num_pages, |
||
981 | struct radeon_fence *fence); |
||
1268 | serge | 982 | uint32_t (*get_engine_clock)(struct radeon_device *rdev); |
1117 | serge | 983 | void (*set_engine_clock)(struct radeon_device *rdev, uint32_t eng_clock); |
1268 | serge | 984 | uint32_t (*get_memory_clock)(struct radeon_device *rdev); |
1117 | serge | 985 | void (*set_memory_clock)(struct radeon_device *rdev, uint32_t mem_clock); |
1430 | serge | 986 | int (*get_pcie_lanes)(struct radeon_device *rdev); |
1117 | serge | 987 | void (*set_pcie_lanes)(struct radeon_device *rdev, int lanes); |
988 | void (*set_clock_gating)(struct radeon_device *rdev, int enable); |
||
1179 | serge | 989 | int (*set_surface_reg)(struct radeon_device *rdev, int reg, |
990 | uint32_t tiling_flags, uint32_t pitch, |
||
991 | uint32_t offset, uint32_t obj_size); |
||
1963 | serge | 992 | void (*clear_surface_reg)(struct radeon_device *rdev, int reg); |
1179 | serge | 993 | void (*bandwidth_update)(struct radeon_device *rdev); |
1321 | serge | 994 | void (*hpd_init)(struct radeon_device *rdev); |
995 | void (*hpd_fini)(struct radeon_device *rdev); |
||
996 | bool (*hpd_sense)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
||
997 | void (*hpd_set_polarity)(struct radeon_device *rdev, enum radeon_hpd_id hpd); |
||
1404 | serge | 998 | /* ioctl hw specific callback. Some hw might want to perform special |
999 | * operation on specific ioctl. For instance on wait idle some hw |
||
1000 | * might want to perform and HDP flush through MMIO as it seems that |
||
1001 | * some R6XX/R7XX hw doesn't take HDP flush into account if programmed |
||
1002 | * through ring. |
||
1003 | */ |
||
1004 | void (*ioctl_wait_idle)(struct radeon_device *rdev, struct radeon_bo *bo); |
||
1963 | serge | 1005 | bool (*gui_idle)(struct radeon_device *rdev); |
1006 | /* power management */ |
||
1007 | void (*pm_misc)(struct radeon_device *rdev); |
||
1008 | void (*pm_prepare)(struct radeon_device *rdev); |
||
1009 | void (*pm_finish)(struct radeon_device *rdev); |
||
1010 | void (*pm_init_profile)(struct radeon_device *rdev); |
||
1011 | void (*pm_get_dynpm_state)(struct radeon_device *rdev); |
||
1012 | /* pageflipping */ |
||
1013 | void (*pre_page_flip)(struct radeon_device *rdev, int crtc); |
||
1014 | u32 (*page_flip)(struct radeon_device *rdev, int crtc, u64 crtc_base); |
||
1015 | void (*post_page_flip)(struct radeon_device *rdev, int crtc); |
||
1117 | serge | 1016 | }; |
1017 | |||
1179 | serge | 1018 | /* |
1019 | * Asic structures |
||
1020 | */ |
||
1963 | serge | 1021 | struct r100_gpu_lockup { |
1022 | unsigned long last_jiffies; |
||
1023 | u32 last_cp_rptr; |
||
1024 | }; |
||
1025 | |||
1179 | serge | 1026 | struct r100_asic { |
1027 | const unsigned *reg_safe_bm; |
||
1028 | unsigned reg_safe_bm_size; |
||
1403 | serge | 1029 | u32 hdp_cntl; |
1963 | serge | 1030 | struct r100_gpu_lockup lockup; |
1179 | serge | 1031 | }; |
1032 | |||
1033 | struct r300_asic { |
||
1034 | const unsigned *reg_safe_bm; |
||
1035 | unsigned reg_safe_bm_size; |
||
1403 | serge | 1036 | u32 resync_scratch; |
1037 | u32 hdp_cntl; |
||
1963 | serge | 1038 | struct r100_gpu_lockup lockup; |
1179 | serge | 1039 | }; |
1040 | |||
1041 | struct r600_asic { |
||
1042 | unsigned max_pipes; |
||
1043 | unsigned max_tile_pipes; |
||
1044 | unsigned max_simds; |
||
1045 | unsigned max_backends; |
||
1046 | unsigned max_gprs; |
||
1047 | unsigned max_threads; |
||
1048 | unsigned max_stack_entries; |
||
1049 | unsigned max_hw_contexts; |
||
1050 | unsigned max_gs_threads; |
||
1051 | unsigned sx_max_export_size; |
||
1052 | unsigned sx_max_export_pos_size; |
||
1053 | unsigned sx_max_export_smx_size; |
||
1054 | unsigned sq_num_cf_insts; |
||
1430 | serge | 1055 | unsigned tiling_nbanks; |
1056 | unsigned tiling_npipes; |
||
1057 | unsigned tiling_group_size; |
||
1963 | serge | 1058 | unsigned tile_config; |
1059 | struct r100_gpu_lockup lockup; |
||
1179 | serge | 1060 | }; |
1061 | |||
1062 | struct rv770_asic { |
||
1063 | unsigned max_pipes; |
||
1064 | unsigned max_tile_pipes; |
||
1065 | unsigned max_simds; |
||
1066 | unsigned max_backends; |
||
1067 | unsigned max_gprs; |
||
1068 | unsigned max_threads; |
||
1069 | unsigned max_stack_entries; |
||
1070 | unsigned max_hw_contexts; |
||
1071 | unsigned max_gs_threads; |
||
1072 | unsigned sx_max_export_size; |
||
1073 | unsigned sx_max_export_pos_size; |
||
1074 | unsigned sx_max_export_smx_size; |
||
1075 | unsigned sq_num_cf_insts; |
||
1076 | unsigned sx_num_of_sets; |
||
1077 | unsigned sc_prim_fifo_size; |
||
1078 | unsigned sc_hiz_tile_fifo_size; |
||
1079 | unsigned sc_earlyz_tile_fifo_fize; |
||
1430 | serge | 1080 | unsigned tiling_nbanks; |
1081 | unsigned tiling_npipes; |
||
1082 | unsigned tiling_group_size; |
||
1963 | serge | 1083 | unsigned tile_config; |
1084 | struct r100_gpu_lockup lockup; |
||
1179 | serge | 1085 | }; |
1086 | |||
1963 | serge | 1087 | struct evergreen_asic { |
1088 | unsigned num_ses; |
||
1089 | unsigned max_pipes; |
||
1090 | unsigned max_tile_pipes; |
||
1091 | unsigned max_simds; |
||
1092 | unsigned max_backends; |
||
1093 | unsigned max_gprs; |
||
1094 | unsigned max_threads; |
||
1095 | unsigned max_stack_entries; |
||
1096 | unsigned max_hw_contexts; |
||
1097 | unsigned max_gs_threads; |
||
1098 | unsigned sx_max_export_size; |
||
1099 | unsigned sx_max_export_pos_size; |
||
1100 | unsigned sx_max_export_smx_size; |
||
1101 | unsigned sq_num_cf_insts; |
||
1102 | unsigned sx_num_of_sets; |
||
1103 | unsigned sc_prim_fifo_size; |
||
1104 | unsigned sc_hiz_tile_fifo_size; |
||
1105 | unsigned sc_earlyz_tile_fifo_size; |
||
1106 | unsigned tiling_nbanks; |
||
1107 | unsigned tiling_npipes; |
||
1108 | unsigned tiling_group_size; |
||
1109 | unsigned tile_config; |
||
1110 | struct r100_gpu_lockup lockup; |
||
1111 | }; |
||
1112 | |||
1113 | struct cayman_asic { |
||
1114 | unsigned max_shader_engines; |
||
1115 | unsigned max_pipes_per_simd; |
||
1116 | unsigned max_tile_pipes; |
||
1117 | unsigned max_simds_per_se; |
||
1118 | unsigned max_backends_per_se; |
||
1119 | unsigned max_texture_channel_caches; |
||
1120 | unsigned max_gprs; |
||
1121 | unsigned max_threads; |
||
1122 | unsigned max_gs_threads; |
||
1123 | unsigned max_stack_entries; |
||
1124 | unsigned sx_num_of_sets; |
||
1125 | unsigned sx_max_export_size; |
||
1126 | unsigned sx_max_export_pos_size; |
||
1127 | unsigned sx_max_export_smx_size; |
||
1128 | unsigned max_hw_contexts; |
||
1129 | unsigned sq_num_cf_insts; |
||
1130 | unsigned sc_prim_fifo_size; |
||
1131 | unsigned sc_hiz_tile_fifo_size; |
||
1132 | unsigned sc_earlyz_tile_fifo_size; |
||
1133 | |||
1134 | unsigned num_shader_engines; |
||
1135 | unsigned num_shader_pipes_per_simd; |
||
1136 | unsigned num_tile_pipes; |
||
1137 | unsigned num_simds_per_se; |
||
1138 | unsigned num_backends_per_se; |
||
1139 | unsigned backend_disable_mask_per_asic; |
||
1140 | unsigned backend_map; |
||
1141 | unsigned num_texture_channel_caches; |
||
1142 | unsigned mem_max_burst_length_bytes; |
||
1143 | unsigned mem_row_size_in_kb; |
||
1144 | unsigned shader_engine_tile_size; |
||
1145 | unsigned num_gpus; |
||
1146 | unsigned multi_gpu_tile_size; |
||
1147 | |||
1148 | unsigned tile_config; |
||
1149 | struct r100_gpu_lockup lockup; |
||
1150 | }; |
||
1151 | |||
1117 | serge | 1152 | union radeon_asic_config { |
1153 | struct r300_asic r300; |
||
1179 | serge | 1154 | struct r100_asic r100; |
1155 | struct r600_asic r600; |
||
1156 | struct rv770_asic rv770; |
||
1963 | serge | 1157 | struct evergreen_asic evergreen; |
1158 | struct cayman_asic cayman; |
||
1117 | serge | 1159 | }; |
1160 | |||
1161 | /* |
||
1963 | serge | 1162 | * asic initizalization from radeon_asic.c |
1163 | */ |
||
1164 | void radeon_agp_disable(struct radeon_device *rdev); |
||
1165 | int radeon_asic_init(struct radeon_device *rdev); |
||
1179 | serge | 1166 | |
1167 | |||
1168 | |||
1963 | serge | 1169 | /* VRAM scratch page for HDP bug */ |
1170 | struct r700_vram_scratch { |
||
1171 | struct radeon_bo *robj; |
||
1172 | volatile uint32_t *ptr; |
||
1173 | }; |
||
1179 | serge | 1174 | |
1117 | serge | 1175 | /* |
1176 | * Core structure, functions and helpers. |
||
1177 | */ |
||
1178 | typedef uint32_t (*radeon_rreg_t)(struct radeon_device*, uint32_t); |
||
1179 | typedef void (*radeon_wreg_t)(struct radeon_device*, uint32_t, uint32_t); |
||
1180 | |||
1181 | struct radeon_device { |
||
1413 | serge | 1182 | struct device *dev; |
1117 | serge | 1183 | struct drm_device *ddev; |
1184 | struct pci_dev *pdev; |
||
1185 | /* ASIC */ |
||
1186 | union radeon_asic_config config; |
||
1187 | enum radeon_family family; |
||
1188 | unsigned long flags; |
||
1189 | int usec_timeout; |
||
1190 | enum radeon_pll_errata pll_errata; |
||
1191 | int num_gb_pipes; |
||
1413 | serge | 1192 | int num_z_pipes; |
1117 | serge | 1193 | int disp_priority; |
1194 | /* BIOS */ |
||
1195 | uint8_t *bios; |
||
1196 | bool is_atom_bios; |
||
1197 | uint16_t bios_header_start; |
||
1413 | serge | 1198 | struct radeon_bo *stollen_vga_memory; |
1117 | serge | 1199 | /* Register mmio */ |
1963 | serge | 1200 | resource_size_t rmmio_base; |
1201 | resource_size_t rmmio_size; |
||
1117 | serge | 1202 | void *rmmio; |
1120 | serge | 1203 | radeon_rreg_t mc_rreg; |
1204 | radeon_wreg_t mc_wreg; |
||
1205 | radeon_rreg_t pll_rreg; |
||
1206 | radeon_wreg_t pll_wreg; |
||
1179 | serge | 1207 | uint32_t pcie_reg_mask; |
1120 | serge | 1208 | radeon_rreg_t pciep_rreg; |
1209 | radeon_wreg_t pciep_wreg; |
||
1963 | serge | 1210 | /* io port */ |
1211 | void __iomem *rio_mem; |
||
1212 | resource_size_t rio_mem_size; |
||
1120 | serge | 1213 | struct radeon_clock clock; |
1117 | serge | 1214 | struct radeon_mc mc; |
1215 | struct radeon_gart gart; |
||
1216 | struct radeon_mode_info mode_info; |
||
1217 | struct radeon_scratch scratch; |
||
1321 | serge | 1218 | struct radeon_mman mman; |
1117 | serge | 1219 | struct radeon_fence_driver fence_drv; |
1120 | serge | 1220 | struct radeon_cp cp; |
1963 | serge | 1221 | /* cayman compute rings */ |
1222 | struct radeon_cp cp1; |
||
1223 | struct radeon_cp cp2; |
||
1117 | serge | 1224 | struct radeon_ib_pool ib_pool; |
1963 | serge | 1225 | struct radeon_irq irq; |
1117 | serge | 1226 | struct radeon_asic *asic; |
1126 | serge | 1227 | struct radeon_gem gem; |
1179 | serge | 1228 | struct radeon_pm pm; |
1229 | uint32_t bios_scratch[RADEON_BIOS_NUM_SCRATCH]; |
||
1630 | serge | 1230 | struct mutex cs_mutex; |
1117 | serge | 1231 | struct radeon_wb wb; |
1179 | serge | 1232 | struct radeon_dummy_page dummy_page; |
1117 | serge | 1233 | bool gpu_lockup; |
1234 | bool shutdown; |
||
1235 | bool suspend; |
||
1179 | serge | 1236 | bool need_dma32; |
1237 | bool accel_working; |
||
1238 | struct radeon_surface_reg surface_regs[RADEON_GEM_MAX_SURFACES]; |
||
1239 | const struct firmware *me_fw; /* all family ME firmware */ |
||
1240 | const struct firmware *pfp_fw; /* r6/700 PFP firmware */ |
||
1403 | serge | 1241 | const struct firmware *rlc_fw; /* r6/700 RLC firmware */ |
1963 | serge | 1242 | const struct firmware *mc_fw; /* NI MC firmware */ |
1179 | serge | 1243 | struct r600_blit r600_blit; |
1963 | serge | 1244 | struct r700_vram_scratch vram_scratch; |
1268 | serge | 1245 | int msi_enabled; /* msi enabled */ |
2004 | serge | 1246 | struct r600_ih ih; /* r6/700 interrupt ring */ |
1963 | serge | 1247 | // struct work_struct hotplug_work; |
1430 | serge | 1248 | int num_crtc; /* number of crtcs */ |
1630 | serge | 1249 | struct mutex dc_hw_i2c_mutex; /* display controller hw i2c mutex */ |
1963 | serge | 1250 | struct mutex vram_mutex; |
1403 | serge | 1251 | |
1252 | /* audio stuff */ |
||
1963 | serge | 1253 | bool audio_enabled; |
1254 | // struct timer_list audio_timer; |
||
1403 | serge | 1255 | int audio_channels; |
1256 | int audio_rate; |
||
1257 | int audio_bits_per_sample; |
||
1258 | uint8_t audio_status_bits; |
||
1259 | uint8_t audio_category_code; |
||
1430 | serge | 1260 | |
1963 | serge | 1261 | |
1262 | /* i2c buses */ |
||
1263 | struct radeon_i2c_chan *i2c_bus[RADEON_MAX_I2C_BUS]; |
||
1117 | serge | 1264 | }; |
1265 | |||
1266 | int radeon_device_init(struct radeon_device *rdev, |
||
1267 | struct drm_device *ddev, |
||
1268 | struct pci_dev *pdev, |
||
1269 | uint32_t flags); |
||
1270 | void radeon_device_fini(struct radeon_device *rdev); |
||
1271 | int radeon_gpu_wait_for_idle(struct radeon_device *rdev); |
||
1272 | |||
1179 | serge | 1273 | static inline uint32_t r100_mm_rreg(struct radeon_device *rdev, uint32_t reg) |
1117 | serge | 1274 | { |
1403 | serge | 1275 | if (reg < rdev->rmmio_size) |
1179 | serge | 1276 | return readl(((void __iomem *)rdev->rmmio) + reg); |
1277 | else { |
||
1278 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
||
1279 | return readl(((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
||
1280 | } |
||
1117 | serge | 1281 | } |
1282 | |||
1179 | serge | 1283 | static inline void r100_mm_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
1117 | serge | 1284 | { |
1403 | serge | 1285 | if (reg < rdev->rmmio_size) |
1179 | serge | 1286 | writel(v, ((void __iomem *)rdev->rmmio) + reg); |
1287 | else { |
||
1288 | writel(reg, ((void __iomem *)rdev->rmmio) + RADEON_MM_INDEX); |
||
1289 | writel(v, ((void __iomem *)rdev->rmmio) + RADEON_MM_DATA); |
||
1290 | } |
||
1117 | serge | 1291 | } |
1292 | |||
1963 | serge | 1293 | static inline u32 r100_io_rreg(struct radeon_device *rdev, u32 reg) |
1294 | { |
||
1295 | if (reg < rdev->rio_mem_size) |
||
1296 | return ioread32(rdev->rio_mem + reg); |
||
1297 | else { |
||
1298 | iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); |
||
1299 | return ioread32(rdev->rio_mem + RADEON_MM_DATA); |
||
1300 | } |
||
1301 | } |
||
1302 | |||
1303 | static inline void r100_io_wreg(struct radeon_device *rdev, u32 reg, u32 v) |
||
1304 | { |
||
1305 | if (reg < rdev->rio_mem_size) |
||
1306 | iowrite32(v, rdev->rio_mem + reg); |
||
1307 | else { |
||
1308 | iowrite32(reg, rdev->rio_mem + RADEON_MM_INDEX); |
||
1309 | iowrite32(v, rdev->rio_mem + RADEON_MM_DATA); |
||
1310 | } |
||
1311 | } |
||
1312 | |||
1321 | serge | 1313 | /* |
1314 | * Cast helper |
||
1315 | */ |
||
1316 | #define to_radeon_fence(p) ((struct radeon_fence *)(p)) |
||
1117 | serge | 1317 | |
1318 | /* |
||
1319 | * Registers read & write functions. |
||
1320 | */ |
||
1321 | #define RREG8(reg) readb(((void __iomem *)rdev->rmmio) + (reg)) |
||
1322 | #define WREG8(reg, v) writeb(v, ((void __iomem *)rdev->rmmio) + (reg)) |
||
1963 | serge | 1323 | #define RREG16(reg) readw(((void __iomem *)rdev->rmmio) + (reg)) |
1324 | #define WREG16(reg, v) writew(v, ((void __iomem *)rdev->rmmio) + (reg)) |
||
1179 | serge | 1325 | #define RREG32(reg) r100_mm_rreg(rdev, (reg)) |
2004 | serge | 1326 | #define DREG32(reg) printk(KERN_INFO "REGISTER: " #reg " : 0x%08X\n", r100_mm_rreg(rdev, (reg))) |
1179 | serge | 1327 | #define WREG32(reg, v) r100_mm_wreg(rdev, (reg), (v)) |
1117 | serge | 1328 | #define REG_SET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
1329 | #define REG_GET(FIELD, v) (((v) << FIELD##_SHIFT) & FIELD##_MASK) |
||
1330 | #define RREG32_PLL(reg) rdev->pll_rreg(rdev, (reg)) |
||
1331 | #define WREG32_PLL(reg, v) rdev->pll_wreg(rdev, (reg), (v)) |
||
1332 | #define RREG32_MC(reg) rdev->mc_rreg(rdev, (reg)) |
||
1333 | #define WREG32_MC(reg, v) rdev->mc_wreg(rdev, (reg), (v)) |
||
1179 | serge | 1334 | #define RREG32_PCIE(reg) rv370_pcie_rreg(rdev, (reg)) |
1335 | #define WREG32_PCIE(reg, v) rv370_pcie_wreg(rdev, (reg), (v)) |
||
1430 | serge | 1336 | #define RREG32_PCIE_P(reg) rdev->pciep_rreg(rdev, (reg)) |
1337 | #define WREG32_PCIE_P(reg, v) rdev->pciep_wreg(rdev, (reg), (v)) |
||
1117 | serge | 1338 | #define WREG32_P(reg, val, mask) \ |
1339 | do { \ |
||
1340 | uint32_t tmp_ = RREG32(reg); \ |
||
1341 | tmp_ &= (mask); \ |
||
1342 | tmp_ |= ((val) & ~(mask)); \ |
||
1343 | WREG32(reg, tmp_); \ |
||
1344 | } while (0) |
||
1345 | #define WREG32_PLL_P(reg, val, mask) \ |
||
1346 | do { \ |
||
1347 | uint32_t tmp_ = RREG32_PLL(reg); \ |
||
1348 | tmp_ &= (mask); \ |
||
1349 | tmp_ |= ((val) & ~(mask)); \ |
||
1350 | WREG32_PLL(reg, tmp_); \ |
||
1351 | } while (0) |
||
1963 | serge | 1352 | #define RREG32_IO(reg) r100_io_rreg(rdev, (reg)) |
1353 | #define WREG32_IO(reg, v) r100_io_wreg(rdev, (reg), (v)) |
||
1117 | serge | 1354 | |
1179 | serge | 1355 | /* |
1356 | * Indirect registers accessor |
||
1357 | */ |
||
1358 | static inline uint32_t rv370_pcie_rreg(struct radeon_device *rdev, uint32_t reg) |
||
1359 | { |
||
1360 | uint32_t r; |
||
1117 | serge | 1361 | |
1179 | serge | 1362 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
1363 | r = RREG32(RADEON_PCIE_DATA); |
||
1364 | return r; |
||
1365 | } |
||
1366 | |||
1367 | static inline void rv370_pcie_wreg(struct radeon_device *rdev, uint32_t reg, uint32_t v) |
||
1368 | { |
||
1369 | WREG32(RADEON_PCIE_INDEX, ((reg) & rdev->pcie_reg_mask)); |
||
1370 | WREG32(RADEON_PCIE_DATA, (v)); |
||
1371 | } |
||
1372 | |||
1373 | void r100_pll_errata_after_index(struct radeon_device *rdev); |
||
1374 | |||
1375 | |||
1117 | serge | 1376 | /* |
1377 | * ASICs helpers. |
||
1378 | */ |
||
1179 | serge | 1379 | #define ASIC_IS_RN50(rdev) ((rdev->pdev->device == 0x515e) || \ |
1380 | (rdev->pdev->device == 0x5969)) |
||
1117 | serge | 1381 | #define ASIC_IS_RV100(rdev) ((rdev->family == CHIP_RV100) || \ |
1382 | (rdev->family == CHIP_RV200) || \ |
||
1383 | (rdev->family == CHIP_RS100) || \ |
||
1384 | (rdev->family == CHIP_RS200) || \ |
||
1385 | (rdev->family == CHIP_RV250) || \ |
||
1386 | (rdev->family == CHIP_RV280) || \ |
||
1387 | (rdev->family == CHIP_RS300)) |
||
1388 | #define ASIC_IS_R300(rdev) ((rdev->family == CHIP_R300) || \ |
||
1389 | (rdev->family == CHIP_RV350) || \ |
||
1390 | (rdev->family == CHIP_R350) || \ |
||
1391 | (rdev->family == CHIP_RV380) || \ |
||
1392 | (rdev->family == CHIP_R420) || \ |
||
1393 | (rdev->family == CHIP_R423) || \ |
||
1394 | (rdev->family == CHIP_RV410) || \ |
||
1395 | (rdev->family == CHIP_RS400) || \ |
||
1396 | (rdev->family == CHIP_RS480)) |
||
1963 | serge | 1397 | #define ASIC_IS_X2(rdev) ((rdev->ddev->pdev->device == 0x9441) || \ |
1398 | (rdev->ddev->pdev->device == 0x9443) || \ |
||
1399 | (rdev->ddev->pdev->device == 0x944B) || \ |
||
1400 | (rdev->ddev->pdev->device == 0x9506) || \ |
||
1401 | (rdev->ddev->pdev->device == 0x9509) || \ |
||
1402 | (rdev->ddev->pdev->device == 0x950F) || \ |
||
1403 | (rdev->ddev->pdev->device == 0x689C) || \ |
||
1404 | (rdev->ddev->pdev->device == 0x689D)) |
||
1117 | serge | 1405 | #define ASIC_IS_AVIVO(rdev) ((rdev->family >= CHIP_RS600)) |
1963 | serge | 1406 | #define ASIC_IS_DCE2(rdev) ((rdev->family == CHIP_RS600) || \ |
1407 | (rdev->family == CHIP_RS690) || \ |
||
1408 | (rdev->family == CHIP_RS740) || \ |
||
1409 | (rdev->family >= CHIP_R600)) |
||
1117 | serge | 1410 | #define ASIC_IS_DCE3(rdev) ((rdev->family >= CHIP_RV620)) |
1411 | #define ASIC_IS_DCE32(rdev) ((rdev->family >= CHIP_RV730)) |
||
1430 | serge | 1412 | #define ASIC_IS_DCE4(rdev) ((rdev->family >= CHIP_CEDAR)) |
1963 | serge | 1413 | #define ASIC_IS_DCE41(rdev) ((rdev->family >= CHIP_PALM) && \ |
1414 | (rdev->flags & RADEON_IS_IGP)) |
||
1415 | #define ASIC_IS_DCE5(rdev) ((rdev->family >= CHIP_BARTS)) |
||
1117 | serge | 1416 | |
1417 | /* |
||
1418 | * BIOS helpers. |
||
1419 | */ |
||
1420 | #define RBIOS8(i) (rdev->bios[i]) |
||
1421 | #define RBIOS16(i) (RBIOS8(i) | (RBIOS8((i)+1) << 8)) |
||
1422 | #define RBIOS32(i) ((RBIOS16(i)) | (RBIOS16((i)+2) << 16)) |
||
1423 | |||
1424 | int radeon_combios_init(struct radeon_device *rdev); |
||
1425 | void radeon_combios_fini(struct radeon_device *rdev); |
||
1426 | int radeon_atombios_init(struct radeon_device *rdev); |
||
1427 | void radeon_atombios_fini(struct radeon_device *rdev); |
||
1428 | |||
1429 | |||
1430 | /* |
||
1431 | * RING helpers. |
||
1432 | */ |
||
1433 | static inline void radeon_ring_write(struct radeon_device *rdev, uint32_t v) |
||
1434 | { |
||
1435 | #if DRM_DEBUG_CODE |
||
1436 | if (rdev->cp.count_dw <= 0) { |
||
1437 | DRM_ERROR("radeon: writting more dword to ring than expected !\n"); |
||
1438 | } |
||
1439 | #endif |
||
1440 | rdev->cp.ring[rdev->cp.wptr++] = v; |
||
1441 | rdev->cp.wptr &= rdev->cp.ptr_mask; |
||
1442 | rdev->cp.count_dw--; |
||
1443 | rdev->cp.ring_free_dw--; |
||
1444 | } |
||
1445 | |||
1446 | |||
1447 | /* |
||
1448 | * ASICs macro. |
||
1449 | */ |
||
1450 | #define radeon_init(rdev) (rdev)->asic->init((rdev)) |
||
1179 | serge | 1451 | #define radeon_fini(rdev) (rdev)->asic->fini((rdev)) |
1452 | #define radeon_resume(rdev) (rdev)->asic->resume((rdev)) |
||
1453 | #define radeon_suspend(rdev) (rdev)->asic->suspend((rdev)) |
||
1117 | serge | 1454 | #define radeon_cs_parse(p) rdev->asic->cs_parse((p)) |
1179 | serge | 1455 | #define radeon_vga_set_state(rdev, state) (rdev)->asic->vga_set_state((rdev), (state)) |
1963 | serge | 1456 | #define radeon_gpu_is_lockup(rdev) (rdev)->asic->gpu_is_lockup((rdev)) |
1457 | #define radeon_asic_reset(rdev) (rdev)->asic->asic_reset((rdev)) |
||
1117 | serge | 1458 | #define radeon_gart_tlb_flush(rdev) (rdev)->asic->gart_tlb_flush((rdev)) |
1459 | #define radeon_gart_set_page(rdev, i, p) (rdev)->asic->gart_set_page((rdev), (i), (p)) |
||
1179 | serge | 1460 | #define radeon_cp_commit(rdev) (rdev)->asic->cp_commit((rdev)) |
1117 | serge | 1461 | #define radeon_ring_start(rdev) (rdev)->asic->ring_start((rdev)) |
1179 | serge | 1462 | #define radeon_ring_test(rdev) (rdev)->asic->ring_test((rdev)) |
1463 | #define radeon_ring_ib_execute(rdev, ib) (rdev)->asic->ring_ib_execute((rdev), (ib)) |
||
1117 | serge | 1464 | #define radeon_irq_set(rdev) (rdev)->asic->irq_set((rdev)) |
1465 | #define radeon_irq_process(rdev) (rdev)->asic->irq_process((rdev)) |
||
1179 | serge | 1466 | #define radeon_get_vblank_counter(rdev, crtc) (rdev)->asic->get_vblank_counter((rdev), (crtc)) |
1117 | serge | 1467 | #define radeon_fence_ring_emit(rdev, fence) (rdev)->asic->fence_ring_emit((rdev), (fence)) |
1468 | #define radeon_copy_blit(rdev, s, d, np, f) (rdev)->asic->copy_blit((rdev), (s), (d), (np), (f)) |
||
1469 | #define radeon_copy_dma(rdev, s, d, np, f) (rdev)->asic->copy_dma((rdev), (s), (d), (np), (f)) |
||
1470 | #define radeon_copy(rdev, s, d, np, f) (rdev)->asic->copy((rdev), (s), (d), (np), (f)) |
||
1268 | serge | 1471 | #define radeon_get_engine_clock(rdev) (rdev)->asic->get_engine_clock((rdev)) |
1117 | serge | 1472 | #define radeon_set_engine_clock(rdev, e) (rdev)->asic->set_engine_clock((rdev), (e)) |
1268 | serge | 1473 | #define radeon_get_memory_clock(rdev) (rdev)->asic->get_memory_clock((rdev)) |
1321 | serge | 1474 | #define radeon_set_memory_clock(rdev, e) (rdev)->asic->set_memory_clock((rdev), (e)) |
1430 | serge | 1475 | #define radeon_get_pcie_lanes(rdev) (rdev)->asic->get_pcie_lanes((rdev)) |
1117 | serge | 1476 | #define radeon_set_pcie_lanes(rdev, l) (rdev)->asic->set_pcie_lanes((rdev), (l)) |
1477 | #define radeon_set_clock_gating(rdev, e) (rdev)->asic->set_clock_gating((rdev), (e)) |
||
1179 | serge | 1478 | #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->set_surface_reg((rdev), (r), (f), (p), (o), (s))) |
1479 | #define radeon_clear_surface_reg(rdev, r) ((rdev)->asic->clear_surface_reg((rdev), (r))) |
||
1480 | #define radeon_bandwidth_update(rdev) (rdev)->asic->bandwidth_update((rdev)) |
||
1321 | serge | 1481 | #define radeon_hpd_init(rdev) (rdev)->asic->hpd_init((rdev)) |
1482 | #define radeon_hpd_fini(rdev) (rdev)->asic->hpd_fini((rdev)) |
||
1483 | #define radeon_hpd_sense(rdev, hpd) (rdev)->asic->hpd_sense((rdev), (hpd)) |
||
1484 | #define radeon_hpd_set_polarity(rdev, hpd) (rdev)->asic->hpd_set_polarity((rdev), (hpd)) |
||
1963 | serge | 1485 | #define radeon_gui_idle(rdev) (rdev)->asic->gui_idle((rdev)) |
1486 | #define radeon_pm_misc(rdev) (rdev)->asic->pm_misc((rdev)) |
||
1487 | #define radeon_pm_prepare(rdev) (rdev)->asic->pm_prepare((rdev)) |
||
1488 | #define radeon_pm_finish(rdev) (rdev)->asic->pm_finish((rdev)) |
||
1489 | #define radeon_pm_init_profile(rdev) (rdev)->asic->pm_init_profile((rdev)) |
||
1490 | #define radeon_pm_get_dynpm_state(rdev) (rdev)->asic->pm_get_dynpm_state((rdev)) |
||
1491 | #define radeon_pre_page_flip(rdev, crtc) rdev->asic->pre_page_flip((rdev), (crtc)) |
||
1492 | #define radeon_page_flip(rdev, crtc, base) rdev->asic->page_flip((rdev), (crtc), (base)) |
||
1493 | #define radeon_post_page_flip(rdev, crtc) rdev->asic->post_page_flip((rdev), (crtc)) |
||
1117 | serge | 1494 | |
1179 | serge | 1495 | /* Common functions */ |
1403 | serge | 1496 | /* AGP */ |
1963 | serge | 1497 | extern int radeon_gpu_reset(struct radeon_device *rdev); |
1403 | serge | 1498 | extern void radeon_agp_disable(struct radeon_device *rdev); |
1179 | serge | 1499 | extern int radeon_gart_table_vram_pin(struct radeon_device *rdev); |
1430 | serge | 1500 | extern void radeon_gart_restore(struct radeon_device *rdev); |
1179 | serge | 1501 | extern int radeon_modeset_init(struct radeon_device *rdev); |
1502 | extern void radeon_modeset_fini(struct radeon_device *rdev); |
||
1503 | extern bool radeon_card_posted(struct radeon_device *rdev); |
||
1963 | serge | 1504 | extern void radeon_update_bandwidth_info(struct radeon_device *rdev); |
1505 | extern void radeon_update_display_priority(struct radeon_device *rdev); |
||
1321 | serge | 1506 | extern bool radeon_boot_test_post_card(struct radeon_device *rdev); |
1179 | serge | 1507 | extern void radeon_scratch_init(struct radeon_device *rdev); |
1963 | serge | 1508 | extern void radeon_wb_fini(struct radeon_device *rdev); |
1509 | extern int radeon_wb_init(struct radeon_device *rdev); |
||
1510 | extern void radeon_wb_disable(struct radeon_device *rdev); |
||
1179 | serge | 1511 | extern void radeon_surface_init(struct radeon_device *rdev); |
1512 | extern int radeon_cs_parser_init(struct radeon_cs_parser *p, void *data); |
||
1221 | serge | 1513 | extern void radeon_legacy_set_clock_gating(struct radeon_device *rdev, int enable); |
1514 | extern void radeon_atom_set_clock_gating(struct radeon_device *rdev, int enable); |
||
1321 | serge | 1515 | extern void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain); |
1403 | serge | 1516 | extern bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo); |
1430 | serge | 1517 | extern void radeon_vram_location(struct radeon_device *rdev, struct radeon_mc *mc, u64 base); |
1518 | extern void radeon_gtt_location(struct radeon_device *rdev, struct radeon_mc *mc); |
||
1519 | extern int radeon_resume_kms(struct drm_device *dev); |
||
1520 | extern int radeon_suspend_kms(struct drm_device *dev, pm_message_t state); |
||
1963 | serge | 1521 | extern void radeon_ttm_set_active_vram_size(struct radeon_device *rdev, u64 size); |
1117 | serge | 1522 | |
1963 | serge | 1523 | /* |
1524 | * r600 functions used by radeon_encoder.c |
||
1525 | */ |
||
1526 | extern void r600_hdmi_enable(struct drm_encoder *encoder); |
||
1527 | extern void r600_hdmi_disable(struct drm_encoder *encoder); |
||
1528 | extern void r600_hdmi_setmode(struct drm_encoder *encoder, struct drm_display_mode *mode); |
||
1179 | serge | 1529 | |
1963 | serge | 1530 | extern int ni_init_microcode(struct radeon_device *rdev); |
1531 | extern int ni_mc_load_microcode(struct radeon_device *rdev); |
||
1221 | serge | 1532 | |
1963 | serge | 1533 | /* radeon_acpi.c */ |
1534 | #if defined(CONFIG_ACPI) |
||
1535 | extern int radeon_acpi_init(struct radeon_device *rdev); |
||
1536 | #else |
||
1537 | static inline int radeon_acpi_init(struct radeon_device *rdev) { return 0; } |
||
1538 | #endif |
||
1179 | serge | 1539 | |
1321 | serge | 1540 | #include "radeon_object.h" |
1179 | serge | 1541 | |
1117 | serge | 1542 | #define DRM_UDELAY(d) udelay(d) |
1543 | |||
1544 | resource_size_t |
||
1545 | drm_get_resource_start(struct drm_device *dev, unsigned int resource); |
||
1546 | resource_size_t |
||
1547 | drm_get_resource_len(struct drm_device *dev, unsigned int resource); |
||
1548 | |||
1239 | serge | 1549 | bool set_mode(struct drm_device *dev, struct drm_connector *connector, |
1403 | serge | 1550 | videomode_t *mode, bool strict); |
1117 | serge | 1551 | |
1179 | serge | 1552 | |
1963 | serge | 1553 | |
1554 | struct work_struct; |
||
1555 | typedef void (*work_func_t)(struct work_struct *work); |
||
1556 | |||
1557 | /* |
||
1558 | * The first word is the work queue pointer and the flags rolled into |
||
1559 | * one |
||
1560 | */ |
||
1561 | #define work_data_bits(work) ((unsigned long *)(&(work)->data)) |
||
1562 | |||
1563 | struct work_struct { |
||
1564 | atomic_long_t data; |
||
1565 | #define WORK_STRUCT_PENDING 0 /* T if work item pending execution */ |
||
1566 | #define WORK_STRUCT_FLAG_MASK (3UL) |
||
1567 | #define WORK_STRUCT_WQ_DATA_MASK (~WORK_STRUCT_FLAG_MASK) |
||
1568 | struct list_head entry; |
||
1569 | work_func_t func; |
||
1570 | }; |
||
1571 | |||
1117 | serge | 1572 | #endif=>><>><>><>><>>>>>><>><>>=> |