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1117 | serge | 1 | /* |
2 | * Copyright 2008 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * Copyright 2009 Jerome Glisse. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the "Software"), |
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8 | * to deal in the Software without restriction, including without limitation |
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9 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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10 | * and/or sell copies of the Software, and to permit persons to whom the |
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11 | * Software is furnished to do so, subject to the following conditions: |
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12 | * |
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13 | * The above copyright notice and this permission notice shall be included in |
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14 | * all copies or substantial portions of the Software. |
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15 | * |
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16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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19 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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20 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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21 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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22 | * OTHER DEALINGS IN THE SOFTWARE. |
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23 | * |
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24 | * Authors: Dave Airlie |
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25 | * Alex Deucher |
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26 | * Jerome Glisse |
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27 | */ |
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1125 | serge | 28 | #include "drmP.h" |
1117 | serge | 29 | #include "radeon.h" |
1221 | serge | 30 | #include "atom.h" |
31 | #include "r520d.h" |
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1117 | serge | 32 | |
1221 | serge | 33 | /* This files gather functions specifics to: r520,rv530,rv560,rv570,r580 */ |
1117 | serge | 34 | |
1221 | serge | 35 | static int r520_mc_wait_for_idle(struct radeon_device *rdev) |
1117 | serge | 36 | { |
37 | unsigned i; |
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38 | uint32_t tmp; |
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39 | |||
40 | for (i = 0; i < rdev->usec_timeout; i++) { |
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41 | /* read MC_STATUS */ |
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42 | tmp = RREG32_MC(R520_MC_STATUS); |
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43 | if (tmp & R520_MC_STATUS_IDLE) { |
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44 | return 0; |
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45 | } |
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46 | DRM_UDELAY(1); |
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47 | } |
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48 | return -1; |
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49 | } |
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50 | |||
1221 | serge | 51 | static void r520_gpu_init(struct radeon_device *rdev) |
1117 | serge | 52 | { |
53 | unsigned pipe_select_current, gb_pipe_select, tmp; |
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1179 | serge | 54 | ENTER(); |
1117 | serge | 55 | |
56 | r100_hdp_reset(rdev); |
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1221 | serge | 57 | rv515_vga_render_disable(rdev); |
1117 | serge | 58 | /* |
59 | * DST_PIPE_CONFIG 0x170C |
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60 | * GB_TILE_CONFIG 0x4018 |
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61 | * GB_FIFO_SIZE 0x4024 |
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62 | * GB_PIPE_SELECT 0x402C |
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63 | * GB_PIPE_SELECT2 0x4124 |
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64 | * Z_PIPE_SHIFT 0 |
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65 | * Z_PIPE_MASK 0x000000003 |
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66 | * GB_FIFO_SIZE2 0x4128 |
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67 | * SC_SFIFO_SIZE_SHIFT 0 |
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68 | * SC_SFIFO_SIZE_MASK 0x000000003 |
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69 | * SC_MFIFO_SIZE_SHIFT 2 |
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70 | * SC_MFIFO_SIZE_MASK 0x00000000C |
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71 | * FG_SFIFO_SIZE_SHIFT 4 |
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72 | * FG_SFIFO_SIZE_MASK 0x000000030 |
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73 | * ZB_MFIFO_SIZE_SHIFT 6 |
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74 | * ZB_MFIFO_SIZE_MASK 0x0000000C0 |
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75 | * GA_ENHANCE 0x4274 |
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76 | * SU_REG_DEST 0x42C8 |
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77 | */ |
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78 | /* workaround for RV530 */ |
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79 | if (rdev->family == CHIP_RV530) { |
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80 | WREG32(0x4128, 0xFF); |
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81 | } |
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82 | r420_pipes_init(rdev); |
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83 | gb_pipe_select = RREG32(0x402C); |
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84 | tmp = RREG32(0x170C); |
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85 | pipe_select_current = (tmp >> 2) & 3; |
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86 | tmp = (1 << pipe_select_current) | |
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87 | (((gb_pipe_select >> 8) & 0xF) << 4); |
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88 | WREG32_PLL(0x000D, tmp); |
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89 | if (r520_mc_wait_for_idle(rdev)) { |
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90 | printk(KERN_WARNING "Failed to wait MC idle while " |
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91 | "programming pipes. Bad things might happen.\n"); |
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92 | } |
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93 | } |
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94 | |||
95 | static void r520_vram_get_type(struct radeon_device *rdev) |
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96 | { |
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97 | uint32_t tmp; |
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1179 | serge | 98 | ENTER(); |
1117 | serge | 99 | |
100 | rdev->mc.vram_width = 128; |
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101 | rdev->mc.vram_is_ddr = true; |
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102 | tmp = RREG32_MC(R520_MC_CNTL0); |
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103 | switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { |
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104 | case 0: |
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105 | rdev->mc.vram_width = 32; |
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106 | break; |
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107 | case 1: |
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108 | rdev->mc.vram_width = 64; |
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109 | break; |
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110 | case 2: |
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111 | rdev->mc.vram_width = 128; |
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112 | break; |
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113 | case 3: |
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114 | rdev->mc.vram_width = 256; |
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115 | break; |
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116 | default: |
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117 | rdev->mc.vram_width = 128; |
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118 | break; |
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119 | } |
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120 | if (tmp & R520_MC_CHANNEL_SIZE) |
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121 | rdev->mc.vram_width *= 2; |
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122 | } |
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123 | |||
124 | void r520_vram_info(struct radeon_device *rdev) |
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125 | { |
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1179 | serge | 126 | fixed20_12 a; |
127 | |||
1117 | serge | 128 | r520_vram_get_type(rdev); |
129 | |||
1179 | serge | 130 | r100_vram_init_sizes(rdev); |
131 | /* FIXME: we should enforce default clock in case GPU is not in |
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132 | * default setup |
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133 | */ |
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134 | a.full = rfixed_const(100); |
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135 | rdev->pm.sclk.full = rfixed_const(rdev->clock.default_sclk); |
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136 | rdev->pm.sclk.full = rfixed_div(rdev->pm.sclk, a); |
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1117 | serge | 137 | } |
138 | |||
1221 | serge | 139 | void r520_mc_program(struct radeon_device *rdev) |
1119 | serge | 140 | { |
1221 | serge | 141 | struct rv515_mc_save save; |
142 | |||
143 | /* Stops all mc clients */ |
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144 | rv515_mc_stop(rdev, &save); |
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145 | |||
146 | /* Wait for mc idle */ |
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147 | if (r520_mc_wait_for_idle(rdev)) |
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148 | dev_warn(rdev->dev, "Wait MC idle timeout before updating MC.\n"); |
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149 | /* Write VRAM size in case we are limiting it */ |
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150 | WREG32(R_0000F8_CONFIG_MEMSIZE, rdev->mc.real_vram_size); |
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151 | /* Program MC, should be a 32bits limited address space */ |
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152 | WREG32_MC(R_000004_MC_FB_LOCATION, |
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153 | S_000004_MC_FB_START(rdev->mc.vram_start >> 16) | |
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154 | S_000004_MC_FB_TOP(rdev->mc.vram_end >> 16)); |
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155 | WREG32(R_000134_HDP_FB_LOCATION, |
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156 | S_000134_HDP_FB_START(rdev->mc.vram_start >> 16)); |
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157 | if (rdev->flags & RADEON_IS_AGP) { |
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158 | WREG32_MC(R_000005_MC_AGP_LOCATION, |
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159 | S_000005_MC_AGP_START(rdev->mc.gtt_start >> 16) | |
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160 | S_000005_MC_AGP_TOP(rdev->mc.gtt_end >> 16)); |
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161 | WREG32_MC(R_000006_AGP_BASE, lower_32_bits(rdev->mc.agp_base)); |
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162 | WREG32_MC(R_000007_AGP_BASE_2, |
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163 | S_000007_AGP_BASE_ADDR_2(upper_32_bits(rdev->mc.agp_base))); |
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164 | } else { |
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165 | WREG32_MC(R_000005_MC_AGP_LOCATION, 0xFFFFFFFF); |
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166 | WREG32_MC(R_000006_AGP_BASE, 0); |
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167 | WREG32_MC(R_000007_AGP_BASE_2, 0); |
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168 | } |
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169 | |||
170 | rv515_mc_resume(rdev, &save); |
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1119 | serge | 171 | } |
1221 | serge | 172 | |
173 | static int r520_startup(struct radeon_device *rdev) |
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174 | { |
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175 | int r; |
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176 | |||
177 | r520_mc_program(rdev); |
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178 | /* Resume clock */ |
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179 | rv515_clock_startup(rdev); |
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180 | /* Initialize GPU configuration (# pipes, ...) */ |
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181 | r520_gpu_init(rdev); |
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182 | /* Initialize GART (initialize after TTM so we can allocate |
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183 | * memory through TTM but finalize after TTM) */ |
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184 | if (rdev->flags & RADEON_IS_PCIE) { |
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185 | r = rv370_pcie_gart_enable(rdev); |
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186 | if (r) |
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187 | return r; |
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188 | } |
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189 | /* Enable IRQ */ |
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190 | // rdev->irq.sw_int = true; |
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191 | // rs600_irq_set(rdev); |
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192 | /* 1M ring buffer */ |
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193 | // r = r100_cp_init(rdev, 1024 * 1024); |
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194 | // if (r) { |
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195 | // dev_err(rdev->dev, "failled initializing CP (%d).\n", r); |
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196 | // return r; |
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197 | // } |
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198 | // r = r100_wb_init(rdev); |
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199 | // if (r) |
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200 | // dev_err(rdev->dev, "failled initializing WB (%d).\n", r); |
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201 | // r = r100_ib_init(rdev); |
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202 | // if (r) { |
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203 | // dev_err(rdev->dev, "failled initializing IB (%d).\n", r); |
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204 | // return r; |
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205 | // } |
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206 | return 0; |
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207 | } |
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208 | |||
209 | |||
210 | |||
211 | int r520_init(struct radeon_device *rdev) |
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212 | { |
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213 | int r; |
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214 | |||
215 | ENTER(); |
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216 | |||
217 | /* Initialize scratch registers */ |
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218 | radeon_scratch_init(rdev); |
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219 | /* Initialize surface registers */ |
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220 | radeon_surface_init(rdev); |
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221 | /* TODO: disable VGA need to use VGA request */ |
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222 | /* BIOS*/ |
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223 | if (!radeon_get_bios(rdev)) { |
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224 | if (ASIC_IS_AVIVO(rdev)) |
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225 | return -EINVAL; |
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226 | } |
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227 | if (rdev->is_atom_bios) { |
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228 | r = radeon_atombios_init(rdev); |
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229 | if (r) |
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230 | return r; |
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231 | } else { |
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232 | dev_err(rdev->dev, "Expecting atombios for RV515 GPU\n"); |
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233 | return -EINVAL; |
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234 | } |
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235 | /* Reset gpu before posting otherwise ATOM will enter infinite loop */ |
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236 | if (radeon_gpu_reset(rdev)) { |
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237 | dev_warn(rdev->dev, |
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238 | "GPU reset failed ! (0xE40=0x%08X, 0x7C0=0x%08X)\n", |
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239 | RREG32(R_000E40_RBBM_STATUS), |
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240 | RREG32(R_0007C0_CP_STAT)); |
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241 | } |
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242 | /* check if cards are posted or not */ |
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243 | if (!radeon_card_posted(rdev) && rdev->bios) { |
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244 | DRM_INFO("GPU not posted. posting now...\n"); |
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245 | atom_asic_init(rdev->mode_info.atom_context); |
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246 | } |
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247 | /* Initialize clocks */ |
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248 | radeon_get_clock_info(rdev->ddev); |
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249 | /* Get vram informations */ |
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250 | r520_vram_info(rdev); |
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251 | /* Initialize memory controller (also test AGP) */ |
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252 | r = r420_mc_init(rdev); |
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1246 | serge | 253 | dbgprintf("mc vram location %x\n", rdev->mc.vram_location); |
1221 | serge | 254 | if (r) |
255 | return r; |
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256 | rv515_debugfs(rdev); |
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257 | /* Fence driver */ |
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258 | // r = radeon_fence_driver_init(rdev); |
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259 | // if (r) |
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260 | // return r; |
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261 | // r = radeon_irq_kms_init(rdev); |
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262 | // if (r) |
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263 | // return r; |
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264 | /* Memory manager */ |
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265 | r = radeon_object_init(rdev); |
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266 | if (r) |
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267 | return r; |
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268 | r = rv370_pcie_gart_init(rdev); |
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269 | if (r) |
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270 | return r; |
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271 | rv515_set_safe_registers(rdev); |
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272 | rdev->accel_working = true; |
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273 | r = r520_startup(rdev); |
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274 | if (r) { |
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275 | /* Somethings want wront with the accel init stop accel */ |
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276 | dev_err(rdev->dev, "Disabling GPU acceleration\n"); |
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277 | // rv515_suspend(rdev); |
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278 | // r100_cp_fini(rdev); |
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279 | // r100_wb_fini(rdev); |
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280 | // r100_ib_fini(rdev); |
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281 | rv370_pcie_gart_fini(rdev); |
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282 | // radeon_agp_fini(rdev); |
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283 | // radeon_irq_kms_fini(rdev); |
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284 | rdev->accel_working = false; |
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285 | } |
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286 | |||
287 | LEAVE(); |
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288 | |||
289 | return 0; |
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290 | }><>><>> |