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5078 | serge | 1 | /* |
2 | * Copyright 2010 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | * Authors: Alex Deucher |
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23 | */ |
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24 | #include |
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25 | #include "radeon.h" |
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26 | #include "radeon_asic.h" |
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27 | #include "radeon_trace.h" |
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28 | #include "nid.h" |
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29 | |||
30 | u32 cayman_gpu_check_soft_reset(struct radeon_device *rdev); |
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31 | |||
32 | /* |
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33 | * DMA |
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34 | * Starting with R600, the GPU has an asynchronous |
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35 | * DMA engine. The programming model is very similar |
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36 | * to the 3D engine (ring buffer, IBs, etc.), but the |
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37 | * DMA controller has it's own packet format that is |
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38 | * different form the PM4 format used by the 3D engine. |
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39 | * It supports copying data, writing embedded data, |
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40 | * solid fills, and a number of other things. It also |
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41 | * has support for tiling/detiling of buffers. |
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42 | * Cayman and newer support two asynchronous DMA engines. |
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43 | */ |
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44 | |||
45 | /** |
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46 | * cayman_dma_get_rptr - get the current read pointer |
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47 | * |
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48 | * @rdev: radeon_device pointer |
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49 | * @ring: radeon ring pointer |
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50 | * |
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51 | * Get the current rptr from the hardware (cayman+). |
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52 | */ |
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53 | uint32_t cayman_dma_get_rptr(struct radeon_device *rdev, |
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54 | struct radeon_ring *ring) |
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55 | { |
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56 | u32 rptr, reg; |
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57 | |||
58 | if (rdev->wb.enabled) { |
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59 | rptr = rdev->wb.wb[ring->rptr_offs/4]; |
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60 | } else { |
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61 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
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62 | reg = DMA_RB_RPTR + DMA0_REGISTER_OFFSET; |
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63 | else |
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64 | reg = DMA_RB_RPTR + DMA1_REGISTER_OFFSET; |
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65 | |||
66 | rptr = RREG32(reg); |
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67 | } |
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68 | |||
69 | return (rptr & 0x3fffc) >> 2; |
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70 | } |
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71 | |||
72 | /** |
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73 | * cayman_dma_get_wptr - get the current write pointer |
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74 | * |
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75 | * @rdev: radeon_device pointer |
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76 | * @ring: radeon ring pointer |
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77 | * |
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78 | * Get the current wptr from the hardware (cayman+). |
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79 | */ |
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80 | uint32_t cayman_dma_get_wptr(struct radeon_device *rdev, |
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81 | struct radeon_ring *ring) |
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82 | { |
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83 | u32 reg; |
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84 | |||
85 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
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86 | reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET; |
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87 | else |
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88 | reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET; |
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89 | |||
90 | return (RREG32(reg) & 0x3fffc) >> 2; |
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91 | } |
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92 | |||
93 | /** |
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94 | * cayman_dma_set_wptr - commit the write pointer |
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95 | * |
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96 | * @rdev: radeon_device pointer |
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97 | * @ring: radeon ring pointer |
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98 | * |
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99 | * Write the wptr back to the hardware (cayman+). |
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100 | */ |
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101 | void cayman_dma_set_wptr(struct radeon_device *rdev, |
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102 | struct radeon_ring *ring) |
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103 | { |
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104 | u32 reg; |
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105 | |||
106 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
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107 | reg = DMA_RB_WPTR + DMA0_REGISTER_OFFSET; |
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108 | else |
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109 | reg = DMA_RB_WPTR + DMA1_REGISTER_OFFSET; |
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110 | |||
111 | WREG32(reg, (ring->wptr << 2) & 0x3fffc); |
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112 | } |
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113 | |||
114 | /** |
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115 | * cayman_dma_ring_ib_execute - Schedule an IB on the DMA engine |
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116 | * |
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117 | * @rdev: radeon_device pointer |
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118 | * @ib: IB object to schedule |
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119 | * |
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120 | * Schedule an IB in the DMA ring (cayman-SI). |
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121 | */ |
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122 | void cayman_dma_ring_ib_execute(struct radeon_device *rdev, |
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123 | struct radeon_ib *ib) |
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124 | { |
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125 | struct radeon_ring *ring = &rdev->ring[ib->ring]; |
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5271 | serge | 126 | unsigned vm_id = ib->vm ? ib->vm->ids[ib->ring].id : 0; |
5078 | serge | 127 | |
128 | if (rdev->wb.enabled) { |
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129 | u32 next_rptr = ring->wptr + 4; |
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130 | while ((next_rptr & 7) != 5) |
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131 | next_rptr++; |
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132 | next_rptr += 3; |
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133 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_WRITE, 0, 0, 1)); |
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134 | radeon_ring_write(ring, ring->next_rptr_gpu_addr & 0xfffffffc); |
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135 | radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); |
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136 | radeon_ring_write(ring, next_rptr); |
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137 | } |
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138 | |||
139 | /* The indirect buffer packet must end on an 8 DW boundary in the DMA ring. |
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140 | * Pad as necessary with NOPs. |
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141 | */ |
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142 | while ((ring->wptr & 7) != 5) |
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143 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0)); |
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5271 | serge | 144 | radeon_ring_write(ring, DMA_IB_PACKET(DMA_PACKET_INDIRECT_BUFFER, vm_id, 0)); |
5078 | serge | 145 | radeon_ring_write(ring, (ib->gpu_addr & 0xFFFFFFE0)); |
146 | radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); |
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147 | |||
148 | } |
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149 | |||
150 | /** |
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151 | * cayman_dma_stop - stop the async dma engines |
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152 | * |
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153 | * @rdev: radeon_device pointer |
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154 | * |
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155 | * Stop the async dma engines (cayman-SI). |
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156 | */ |
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157 | void cayman_dma_stop(struct radeon_device *rdev) |
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158 | { |
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159 | u32 rb_cntl; |
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160 | |||
161 | if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) || |
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162 | (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX)) |
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163 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
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164 | |||
165 | /* dma0 */ |
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166 | rb_cntl = RREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET); |
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167 | rb_cntl &= ~DMA_RB_ENABLE; |
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168 | WREG32(DMA_RB_CNTL + DMA0_REGISTER_OFFSET, rb_cntl); |
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169 | |||
170 | /* dma1 */ |
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171 | rb_cntl = RREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET); |
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172 | rb_cntl &= ~DMA_RB_ENABLE; |
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173 | WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, rb_cntl); |
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174 | |||
175 | rdev->ring[R600_RING_TYPE_DMA_INDEX].ready = false; |
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176 | rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX].ready = false; |
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177 | } |
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178 | |||
179 | /** |
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180 | * cayman_dma_resume - setup and start the async dma engines |
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181 | * |
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182 | * @rdev: radeon_device pointer |
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183 | * |
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184 | * Set up the DMA ring buffers and enable them. (cayman-SI). |
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185 | * Returns 0 for success, error for failure. |
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186 | */ |
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187 | int cayman_dma_resume(struct radeon_device *rdev) |
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188 | { |
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189 | struct radeon_ring *ring; |
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190 | u32 rb_cntl, dma_cntl, ib_cntl; |
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191 | u32 rb_bufsz; |
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192 | u32 reg_offset, wb_offset; |
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193 | int i, r; |
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194 | |||
195 | for (i = 0; i < 2; i++) { |
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196 | if (i == 0) { |
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197 | ring = &rdev->ring[R600_RING_TYPE_DMA_INDEX]; |
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198 | reg_offset = DMA0_REGISTER_OFFSET; |
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199 | wb_offset = R600_WB_DMA_RPTR_OFFSET; |
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200 | } else { |
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201 | ring = &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]; |
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202 | reg_offset = DMA1_REGISTER_OFFSET; |
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203 | wb_offset = CAYMAN_WB_DMA1_RPTR_OFFSET; |
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204 | } |
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205 | |||
206 | WREG32(DMA_SEM_INCOMPLETE_TIMER_CNTL + reg_offset, 0); |
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207 | WREG32(DMA_SEM_WAIT_FAIL_TIMER_CNTL + reg_offset, 0); |
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208 | |||
209 | /* Set ring buffer size in dwords */ |
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210 | rb_bufsz = order_base_2(ring->ring_size / 4); |
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211 | rb_cntl = rb_bufsz << 1; |
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212 | #ifdef __BIG_ENDIAN |
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213 | rb_cntl |= DMA_RB_SWAP_ENABLE | DMA_RPTR_WRITEBACK_SWAP_ENABLE; |
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214 | #endif |
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215 | WREG32(DMA_RB_CNTL + reg_offset, rb_cntl); |
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216 | |||
217 | /* Initialize the ring buffer's read and write pointers */ |
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218 | WREG32(DMA_RB_RPTR + reg_offset, 0); |
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219 | WREG32(DMA_RB_WPTR + reg_offset, 0); |
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220 | |||
221 | /* set the wb address whether it's enabled or not */ |
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222 | WREG32(DMA_RB_RPTR_ADDR_HI + reg_offset, |
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223 | upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF); |
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224 | WREG32(DMA_RB_RPTR_ADDR_LO + reg_offset, |
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225 | ((rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC)); |
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226 | |||
227 | if (rdev->wb.enabled) |
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228 | rb_cntl |= DMA_RPTR_WRITEBACK_ENABLE; |
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229 | |||
230 | WREG32(DMA_RB_BASE + reg_offset, ring->gpu_addr >> 8); |
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231 | |||
232 | /* enable DMA IBs */ |
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233 | ib_cntl = DMA_IB_ENABLE | CMD_VMID_FORCE; |
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234 | #ifdef __BIG_ENDIAN |
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235 | ib_cntl |= DMA_IB_SWAP_ENABLE; |
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236 | #endif |
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237 | WREG32(DMA_IB_CNTL + reg_offset, ib_cntl); |
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238 | |||
239 | dma_cntl = RREG32(DMA_CNTL + reg_offset); |
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240 | dma_cntl &= ~CTXEMPTY_INT_ENABLE; |
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241 | WREG32(DMA_CNTL + reg_offset, dma_cntl); |
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242 | |||
243 | ring->wptr = 0; |
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244 | WREG32(DMA_RB_WPTR + reg_offset, ring->wptr << 2); |
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245 | |||
246 | WREG32(DMA_RB_CNTL + reg_offset, rb_cntl | DMA_RB_ENABLE); |
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247 | |||
248 | ring->ready = true; |
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249 | |||
250 | r = radeon_ring_test(rdev, ring->idx, ring); |
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251 | if (r) { |
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252 | ring->ready = false; |
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253 | return r; |
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254 | } |
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255 | } |
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256 | |||
257 | if ((rdev->asic->copy.copy_ring_index == R600_RING_TYPE_DMA_INDEX) || |
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258 | (rdev->asic->copy.copy_ring_index == CAYMAN_RING_TYPE_DMA1_INDEX)) |
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259 | radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
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260 | |||
261 | return 0; |
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262 | } |
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263 | |||
264 | /** |
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265 | * cayman_dma_fini - tear down the async dma engines |
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266 | * |
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267 | * @rdev: radeon_device pointer |
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268 | * |
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269 | * Stop the async dma engines and free the rings (cayman-SI). |
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270 | */ |
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271 | void cayman_dma_fini(struct radeon_device *rdev) |
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272 | { |
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273 | cayman_dma_stop(rdev); |
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274 | radeon_ring_fini(rdev, &rdev->ring[R600_RING_TYPE_DMA_INDEX]); |
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275 | radeon_ring_fini(rdev, &rdev->ring[CAYMAN_RING_TYPE_DMA1_INDEX]); |
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276 | } |
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277 | |||
278 | /** |
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279 | * cayman_dma_is_lockup - Check if the DMA engine is locked up |
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280 | * |
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281 | * @rdev: radeon_device pointer |
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282 | * @ring: radeon_ring structure holding ring information |
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283 | * |
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284 | * Check if the async DMA engine is locked up. |
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285 | * Returns true if the engine appears to be locked up, false if not. |
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286 | */ |
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287 | bool cayman_dma_is_lockup(struct radeon_device *rdev, struct radeon_ring *ring) |
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288 | { |
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289 | u32 reset_mask = cayman_gpu_check_soft_reset(rdev); |
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290 | u32 mask; |
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291 | |||
292 | if (ring->idx == R600_RING_TYPE_DMA_INDEX) |
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293 | mask = RADEON_RESET_DMA; |
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294 | else |
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295 | mask = RADEON_RESET_DMA1; |
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296 | |||
297 | if (!(reset_mask & mask)) { |
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298 | radeon_ring_lockup_update(rdev, ring); |
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299 | return false; |
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300 | } |
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301 | return radeon_ring_test_lockup(rdev, ring); |
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302 | } |
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303 | |||
304 | /** |
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305 | * cayman_dma_vm_copy_pages - update PTEs by copying them from the GART |
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306 | * |
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307 | * @rdev: radeon_device pointer |
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308 | * @ib: indirect buffer to fill with commands |
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309 | * @pe: addr of the page entry |
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310 | * @src: src addr where to copy from |
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311 | * @count: number of page entries to update |
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312 | * |
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313 | * Update PTEs by copying them from the GART using the DMA (cayman/TN). |
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314 | */ |
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315 | void cayman_dma_vm_copy_pages(struct radeon_device *rdev, |
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316 | struct radeon_ib *ib, |
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317 | uint64_t pe, uint64_t src, |
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318 | unsigned count) |
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319 | { |
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320 | unsigned ndw; |
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321 | |||
322 | while (count) { |
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323 | ndw = count * 2; |
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324 | if (ndw > 0xFFFFE) |
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325 | ndw = 0xFFFFE; |
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326 | |||
327 | ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_COPY, |
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328 | 0, 0, ndw); |
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329 | ib->ptr[ib->length_dw++] = lower_32_bits(pe); |
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330 | ib->ptr[ib->length_dw++] = lower_32_bits(src); |
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331 | ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; |
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332 | ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; |
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333 | |||
334 | pe += ndw * 4; |
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335 | src += ndw * 4; |
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336 | count -= ndw / 2; |
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337 | } |
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338 | } |
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339 | |||
340 | /** |
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341 | * cayman_dma_vm_write_pages - update PTEs by writing them manually |
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342 | * |
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343 | * @rdev: radeon_device pointer |
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344 | * @ib: indirect buffer to fill with commands |
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345 | * @pe: addr of the page entry |
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346 | * @addr: dst addr to write into pe |
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347 | * @count: number of page entries to update |
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348 | * @incr: increase next addr by incr bytes |
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6104 | serge | 349 | * @flags: hw access flags |
5078 | serge | 350 | * |
351 | * Update PTEs by writing them manually using the DMA (cayman/TN). |
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352 | */ |
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353 | void cayman_dma_vm_write_pages(struct radeon_device *rdev, |
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6104 | serge | 354 | struct radeon_ib *ib, |
355 | uint64_t pe, |
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356 | uint64_t addr, unsigned count, |
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357 | uint32_t incr, uint32_t flags) |
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5078 | serge | 358 | { |
359 | uint64_t value; |
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360 | unsigned ndw; |
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361 | |||
6104 | serge | 362 | while (count) { |
363 | ndw = count * 2; |
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364 | if (ndw > 0xFFFFE) |
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365 | ndw = 0xFFFFE; |
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5078 | serge | 366 | |
6104 | serge | 367 | /* for non-physically contiguous pages (system) */ |
5078 | serge | 368 | ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_WRITE, |
369 | 0, 0, ndw); |
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6104 | serge | 370 | ib->ptr[ib->length_dw++] = pe; |
371 | ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; |
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372 | for (; ndw > 0; ndw -= 2, --count, pe += 8) { |
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373 | if (flags & R600_PTE_SYSTEM) { |
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374 | value = radeon_vm_map_gart(rdev, addr); |
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375 | } else if (flags & R600_PTE_VALID) { |
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376 | value = addr; |
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377 | } else { |
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378 | value = 0; |
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5078 | serge | 379 | } |
6104 | serge | 380 | addr += incr; |
381 | value |= flags; |
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382 | ib->ptr[ib->length_dw++] = value; |
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383 | ib->ptr[ib->length_dw++] = upper_32_bits(value); |
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5078 | serge | 384 | } |
6104 | serge | 385 | } |
5078 | serge | 386 | } |
387 | |||
388 | /** |
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389 | * cayman_dma_vm_set_pages - update the page tables using the DMA |
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390 | * |
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391 | * @rdev: radeon_device pointer |
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392 | * @ib: indirect buffer to fill with commands |
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393 | * @pe: addr of the page entry |
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394 | * @addr: dst addr to write into pe |
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395 | * @count: number of page entries to update |
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396 | * @incr: increase next addr by incr bytes |
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397 | * @flags: hw access flags |
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398 | * |
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399 | * Update the page tables using the DMA (cayman/TN). |
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400 | */ |
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401 | void cayman_dma_vm_set_pages(struct radeon_device *rdev, |
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402 | struct radeon_ib *ib, |
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403 | uint64_t pe, |
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404 | uint64_t addr, unsigned count, |
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405 | uint32_t incr, uint32_t flags) |
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406 | { |
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407 | uint64_t value; |
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408 | unsigned ndw; |
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409 | |||
6104 | serge | 410 | while (count) { |
411 | ndw = count * 2; |
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412 | if (ndw > 0xFFFFE) |
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413 | ndw = 0xFFFFE; |
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5078 | serge | 414 | |
6104 | serge | 415 | if (flags & R600_PTE_VALID) |
416 | value = addr; |
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417 | else |
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418 | value = 0; |
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5078 | serge | 419 | |
6104 | serge | 420 | /* for physically contiguous pages (vram) */ |
421 | ib->ptr[ib->length_dw++] = DMA_PTE_PDE_PACKET(ndw); |
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422 | ib->ptr[ib->length_dw++] = pe; /* dst addr */ |
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423 | ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; |
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424 | ib->ptr[ib->length_dw++] = flags; /* mask */ |
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425 | ib->ptr[ib->length_dw++] = 0; |
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426 | ib->ptr[ib->length_dw++] = value; /* value */ |
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427 | ib->ptr[ib->length_dw++] = upper_32_bits(value); |
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428 | ib->ptr[ib->length_dw++] = incr; /* increment size */ |
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429 | ib->ptr[ib->length_dw++] = 0; |
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5078 | serge | 430 | |
6104 | serge | 431 | pe += ndw * 4; |
432 | addr += (ndw / 2) * incr; |
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433 | count -= ndw / 2; |
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434 | } |
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5078 | serge | 435 | } |
436 | |||
437 | /** |
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438 | * cayman_dma_vm_pad_ib - pad the IB to the required number of dw |
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439 | * |
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440 | * @ib: indirect buffer to fill with padding |
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441 | * |
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442 | */ |
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443 | void cayman_dma_vm_pad_ib(struct radeon_ib *ib) |
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444 | { |
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445 | while (ib->length_dw & 0x7) |
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446 | ib->ptr[ib->length_dw++] = DMA_PACKET(DMA_PACKET_NOP, 0, 0, 0); |
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447 | } |
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448 | |||
5271 | serge | 449 | void cayman_dma_vm_flush(struct radeon_device *rdev, struct radeon_ring *ring, |
450 | unsigned vm_id, uint64_t pd_addr) |
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5078 | serge | 451 | { |
452 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0)); |
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5271 | serge | 453 | radeon_ring_write(ring, (0xf << 16) | ((VM_CONTEXT0_PAGE_TABLE_BASE_ADDR + (vm_id << 2)) >> 2)); |
454 | radeon_ring_write(ring, pd_addr >> 12); |
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5078 | serge | 455 | |
456 | /* flush hdp cache */ |
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457 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0)); |
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458 | radeon_ring_write(ring, (0xf << 16) | (HDP_MEM_COHERENCY_FLUSH_CNTL >> 2)); |
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459 | radeon_ring_write(ring, 1); |
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460 | |||
461 | /* bits 0-7 are the VM contexts0-7 */ |
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462 | radeon_ring_write(ring, DMA_PACKET(DMA_PACKET_SRBM_WRITE, 0, 0, 0)); |
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463 | radeon_ring_write(ring, (0xf << 16) | (VM_INVALIDATE_REQUEST >> 2)); |
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5271 | serge | 464 | radeon_ring_write(ring, 1 << vm_id); |
6104 | serge | 465 | |
466 | /* wait for invalidate to complete */ |
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467 | radeon_ring_write(ring, DMA_SRBM_READ_PACKET); |
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468 | radeon_ring_write(ring, (0xff << 20) | (VM_INVALIDATE_REQUEST >> 2)); |
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469 | radeon_ring_write(ring, 0); /* mask */ |
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470 | radeon_ring_write(ring, 0); /* value */ |
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5078 | serge | 471 | }><>><>><>><>><>><>><>><>>><>><> |
472 |