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2005 | serge | 1 | /* |
2 | * Copyright 2010 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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21 | * DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Alex Deucher |
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25 | */ |
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26 | |||
27 | #include "drmP.h" |
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28 | #include "drm.h" |
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29 | #include "radeon_drm.h" |
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30 | #include "radeon.h" |
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31 | |||
32 | #include "evergreend.h" |
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33 | #include "evergreen_blit_shaders.h" |
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34 | #include "cayman_blit_shaders.h" |
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35 | |||
36 | #define DI_PT_RECTLIST 0x11 |
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37 | #define DI_INDEX_SIZE_16_BIT 0x0 |
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38 | #define DI_SRC_SEL_AUTO_INDEX 0x2 |
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39 | |||
40 | #define FMT_8 0x1 |
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41 | #define FMT_5_6_5 0x8 |
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42 | #define FMT_8_8_8_8 0x1a |
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43 | #define COLOR_8 0x1 |
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44 | #define COLOR_5_6_5 0x8 |
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45 | #define COLOR_8_8_8_8 0x1a |
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46 | |||
47 | /* emits 17 */ |
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48 | static void |
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49 | set_render_target(struct radeon_device *rdev, int format, |
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50 | int w, int h, u64 gpu_addr) |
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51 | { |
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52 | u32 cb_color_info; |
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53 | int pitch, slice; |
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54 | |||
55 | h = ALIGN(h, 8); |
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56 | if (h < 8) |
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57 | h = 8; |
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58 | |||
59 | cb_color_info = ((format << 2) | (1 << 24) | (1 << 8)); |
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60 | pitch = (w / 8) - 1; |
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61 | slice = ((w * h) / 64) - 1; |
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62 | |||
63 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 15)); |
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64 | radeon_ring_write(rdev, (CB_COLOR0_BASE - PACKET3_SET_CONTEXT_REG_START) >> 2); |
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65 | radeon_ring_write(rdev, gpu_addr >> 8); |
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66 | radeon_ring_write(rdev, pitch); |
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67 | radeon_ring_write(rdev, slice); |
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68 | radeon_ring_write(rdev, 0); |
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69 | radeon_ring_write(rdev, cb_color_info); |
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70 | radeon_ring_write(rdev, (1 << 4)); |
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71 | radeon_ring_write(rdev, (w - 1) | ((h - 1) << 16)); |
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72 | radeon_ring_write(rdev, 0); |
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73 | radeon_ring_write(rdev, 0); |
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74 | radeon_ring_write(rdev, 0); |
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75 | radeon_ring_write(rdev, 0); |
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76 | radeon_ring_write(rdev, 0); |
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77 | radeon_ring_write(rdev, 0); |
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78 | radeon_ring_write(rdev, 0); |
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79 | radeon_ring_write(rdev, 0); |
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80 | } |
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81 | |||
82 | /* emits 5dw */ |
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83 | static void |
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84 | cp_set_surface_sync(struct radeon_device *rdev, |
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85 | u32 sync_type, u32 size, |
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86 | u64 mc_addr) |
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87 | { |
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88 | u32 cp_coher_size; |
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89 | |||
90 | if (size == 0xffffffff) |
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91 | cp_coher_size = 0xffffffff; |
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92 | else |
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93 | cp_coher_size = ((size + 255) >> 8); |
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94 | |||
95 | radeon_ring_write(rdev, PACKET3(PACKET3_SURFACE_SYNC, 3)); |
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96 | radeon_ring_write(rdev, sync_type); |
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97 | radeon_ring_write(rdev, cp_coher_size); |
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98 | radeon_ring_write(rdev, mc_addr >> 8); |
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99 | radeon_ring_write(rdev, 10); /* poll interval */ |
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100 | } |
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101 | |||
102 | /* emits 11dw + 1 surface sync = 16dw */ |
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103 | static void |
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104 | set_shaders(struct radeon_device *rdev) |
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105 | { |
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106 | u64 gpu_addr; |
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107 | |||
108 | /* VS */ |
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109 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; |
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110 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 3)); |
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111 | radeon_ring_write(rdev, (SQ_PGM_START_VS - PACKET3_SET_CONTEXT_REG_START) >> 2); |
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112 | radeon_ring_write(rdev, gpu_addr >> 8); |
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113 | radeon_ring_write(rdev, 2); |
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114 | radeon_ring_write(rdev, 0); |
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115 | |||
116 | /* PS */ |
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117 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.ps_offset; |
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118 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 4)); |
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119 | radeon_ring_write(rdev, (SQ_PGM_START_PS - PACKET3_SET_CONTEXT_REG_START) >> 2); |
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120 | radeon_ring_write(rdev, gpu_addr >> 8); |
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121 | radeon_ring_write(rdev, 1); |
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122 | radeon_ring_write(rdev, 0); |
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123 | radeon_ring_write(rdev, 2); |
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124 | |||
125 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.vs_offset; |
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126 | cp_set_surface_sync(rdev, PACKET3_SH_ACTION_ENA, 512, gpu_addr); |
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127 | } |
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128 | |||
129 | /* emits 10 + 1 sync (5) = 15 */ |
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130 | static void |
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131 | set_vtx_resource(struct radeon_device *rdev, u64 gpu_addr) |
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132 | { |
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133 | u32 sq_vtx_constant_word2, sq_vtx_constant_word3; |
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134 | |||
135 | /* high addr, stride */ |
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136 | sq_vtx_constant_word2 = ((upper_32_bits(gpu_addr) & 0xff) | (16 << 8)); |
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137 | #ifdef __BIG_ENDIAN |
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138 | sq_vtx_constant_word2 |= (2 << 30); |
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139 | #endif |
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140 | /* xyzw swizzles */ |
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141 | sq_vtx_constant_word3 = (0 << 3) | (1 << 6) | (2 << 9) | (3 << 12); |
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142 | |||
143 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8)); |
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144 | radeon_ring_write(rdev, 0x580); |
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145 | radeon_ring_write(rdev, gpu_addr & 0xffffffff); |
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146 | radeon_ring_write(rdev, 48 - 1); /* size */ |
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147 | radeon_ring_write(rdev, sq_vtx_constant_word2); |
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148 | radeon_ring_write(rdev, sq_vtx_constant_word3); |
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149 | radeon_ring_write(rdev, 0); |
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150 | radeon_ring_write(rdev, 0); |
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151 | radeon_ring_write(rdev, 0); |
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152 | radeon_ring_write(rdev, SQ_TEX_VTX_VALID_BUFFER << 30); |
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153 | |||
154 | if ((rdev->family == CHIP_CEDAR) || |
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155 | (rdev->family == CHIP_PALM) || |
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156 | (rdev->family == CHIP_SUMO) || |
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157 | (rdev->family == CHIP_SUMO2) || |
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158 | (rdev->family == CHIP_CAICOS)) |
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159 | cp_set_surface_sync(rdev, |
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160 | PACKET3_TC_ACTION_ENA, 48, gpu_addr); |
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161 | else |
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162 | cp_set_surface_sync(rdev, |
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163 | PACKET3_VC_ACTION_ENA, 48, gpu_addr); |
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164 | |||
165 | } |
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166 | |||
167 | /* emits 10 */ |
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168 | static void |
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169 | set_tex_resource(struct radeon_device *rdev, |
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170 | int format, int w, int h, int pitch, |
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171 | u64 gpu_addr) |
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172 | { |
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173 | u32 sq_tex_resource_word0, sq_tex_resource_word1; |
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174 | u32 sq_tex_resource_word4, sq_tex_resource_word7; |
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175 | |||
176 | if (h < 1) |
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177 | h = 1; |
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178 | |||
179 | sq_tex_resource_word0 = (1 << 0); /* 2D */ |
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180 | sq_tex_resource_word0 |= ((((pitch >> 3) - 1) << 6) | |
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181 | ((w - 1) << 18)); |
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182 | sq_tex_resource_word1 = ((h - 1) << 0) | (1 << 28); |
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183 | /* xyzw swizzles */ |
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184 | sq_tex_resource_word4 = (0 << 16) | (1 << 19) | (2 << 22) | (3 << 25); |
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185 | |||
186 | sq_tex_resource_word7 = format | (SQ_TEX_VTX_VALID_TEXTURE << 30); |
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187 | |||
188 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_RESOURCE, 8)); |
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189 | radeon_ring_write(rdev, 0); |
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190 | radeon_ring_write(rdev, sq_tex_resource_word0); |
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191 | radeon_ring_write(rdev, sq_tex_resource_word1); |
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192 | radeon_ring_write(rdev, gpu_addr >> 8); |
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193 | radeon_ring_write(rdev, gpu_addr >> 8); |
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194 | radeon_ring_write(rdev, sq_tex_resource_word4); |
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195 | radeon_ring_write(rdev, 0); |
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196 | radeon_ring_write(rdev, 0); |
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197 | radeon_ring_write(rdev, sq_tex_resource_word7); |
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198 | } |
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199 | |||
200 | /* emits 12 */ |
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201 | static void |
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202 | set_scissors(struct radeon_device *rdev, int x1, int y1, |
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203 | int x2, int y2) |
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204 | { |
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205 | /* workaround some hw bugs */ |
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206 | if (x2 == 0) |
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207 | x1 = 1; |
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208 | if (y2 == 0) |
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209 | y1 = 1; |
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210 | if (rdev->family == CHIP_CAYMAN) { |
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211 | if ((x2 == 1) && (y2 == 1)) |
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212 | x2 = 2; |
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213 | } |
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214 | |||
215 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
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216 | radeon_ring_write(rdev, (PA_SC_SCREEN_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); |
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217 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16)); |
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218 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
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219 | |||
220 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
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221 | radeon_ring_write(rdev, (PA_SC_GENERIC_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); |
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222 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); |
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223 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
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224 | |||
225 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONTEXT_REG, 2)); |
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226 | radeon_ring_write(rdev, (PA_SC_WINDOW_SCISSOR_TL - PACKET3_SET_CONTEXT_REG_START) >> 2); |
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227 | radeon_ring_write(rdev, (x1 << 0) | (y1 << 16) | (1 << 31)); |
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228 | radeon_ring_write(rdev, (x2 << 0) | (y2 << 16)); |
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229 | } |
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230 | |||
231 | /* emits 10 */ |
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232 | static void |
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233 | draw_auto(struct radeon_device *rdev) |
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234 | { |
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235 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
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236 | radeon_ring_write(rdev, (VGT_PRIMITIVE_TYPE - PACKET3_SET_CONFIG_REG_START) >> 2); |
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237 | radeon_ring_write(rdev, DI_PT_RECTLIST); |
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238 | |||
239 | radeon_ring_write(rdev, PACKET3(PACKET3_INDEX_TYPE, 0)); |
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240 | radeon_ring_write(rdev, |
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241 | #ifdef __BIG_ENDIAN |
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242 | (2 << 2) | |
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243 | #endif |
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244 | DI_INDEX_SIZE_16_BIT); |
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245 | |||
246 | radeon_ring_write(rdev, PACKET3(PACKET3_NUM_INSTANCES, 0)); |
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247 | radeon_ring_write(rdev, 1); |
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248 | |||
249 | radeon_ring_write(rdev, PACKET3(PACKET3_DRAW_INDEX_AUTO, 1)); |
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250 | radeon_ring_write(rdev, 3); |
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251 | radeon_ring_write(rdev, DI_SRC_SEL_AUTO_INDEX); |
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252 | |||
253 | } |
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254 | |||
255 | /* emits 39 */ |
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256 | static void |
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257 | set_default_state(struct radeon_device *rdev) |
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258 | { |
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259 | u32 sq_config, sq_gpr_resource_mgmt_1, sq_gpr_resource_mgmt_2, sq_gpr_resource_mgmt_3; |
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260 | u32 sq_thread_resource_mgmt, sq_thread_resource_mgmt_2; |
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261 | u32 sq_stack_resource_mgmt_1, sq_stack_resource_mgmt_2, sq_stack_resource_mgmt_3; |
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262 | int num_ps_gprs, num_vs_gprs, num_temp_gprs; |
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263 | int num_gs_gprs, num_es_gprs, num_hs_gprs, num_ls_gprs; |
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264 | int num_ps_threads, num_vs_threads, num_gs_threads, num_es_threads; |
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265 | int num_hs_threads, num_ls_threads; |
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266 | int num_ps_stack_entries, num_vs_stack_entries, num_gs_stack_entries, num_es_stack_entries; |
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267 | int num_hs_stack_entries, num_ls_stack_entries; |
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268 | u64 gpu_addr; |
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269 | int dwords; |
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270 | |||
271 | /* set clear context state */ |
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272 | radeon_ring_write(rdev, PACKET3(PACKET3_CLEAR_STATE, 0)); |
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273 | radeon_ring_write(rdev, 0); |
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274 | |||
275 | if (rdev->family < CHIP_CAYMAN) { |
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276 | switch (rdev->family) { |
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277 | case CHIP_CEDAR: |
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278 | default: |
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279 | num_ps_gprs = 93; |
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280 | num_vs_gprs = 46; |
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281 | num_temp_gprs = 4; |
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282 | num_gs_gprs = 31; |
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283 | num_es_gprs = 31; |
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284 | num_hs_gprs = 23; |
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285 | num_ls_gprs = 23; |
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286 | num_ps_threads = 96; |
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287 | num_vs_threads = 16; |
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288 | num_gs_threads = 16; |
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289 | num_es_threads = 16; |
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290 | num_hs_threads = 16; |
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291 | num_ls_threads = 16; |
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292 | num_ps_stack_entries = 42; |
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293 | num_vs_stack_entries = 42; |
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294 | num_gs_stack_entries = 42; |
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295 | num_es_stack_entries = 42; |
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296 | num_hs_stack_entries = 42; |
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297 | num_ls_stack_entries = 42; |
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298 | break; |
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299 | case CHIP_REDWOOD: |
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300 | num_ps_gprs = 93; |
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301 | num_vs_gprs = 46; |
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302 | num_temp_gprs = 4; |
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303 | num_gs_gprs = 31; |
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304 | num_es_gprs = 31; |
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305 | num_hs_gprs = 23; |
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306 | num_ls_gprs = 23; |
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307 | num_ps_threads = 128; |
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308 | num_vs_threads = 20; |
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309 | num_gs_threads = 20; |
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310 | num_es_threads = 20; |
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311 | num_hs_threads = 20; |
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312 | num_ls_threads = 20; |
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313 | num_ps_stack_entries = 42; |
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314 | num_vs_stack_entries = 42; |
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315 | num_gs_stack_entries = 42; |
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316 | num_es_stack_entries = 42; |
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317 | num_hs_stack_entries = 42; |
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318 | num_ls_stack_entries = 42; |
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319 | break; |
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320 | case CHIP_JUNIPER: |
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321 | num_ps_gprs = 93; |
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322 | num_vs_gprs = 46; |
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323 | num_temp_gprs = 4; |
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324 | num_gs_gprs = 31; |
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325 | num_es_gprs = 31; |
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326 | num_hs_gprs = 23; |
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327 | num_ls_gprs = 23; |
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328 | num_ps_threads = 128; |
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329 | num_vs_threads = 20; |
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330 | num_gs_threads = 20; |
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331 | num_es_threads = 20; |
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332 | num_hs_threads = 20; |
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333 | num_ls_threads = 20; |
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334 | num_ps_stack_entries = 85; |
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335 | num_vs_stack_entries = 85; |
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336 | num_gs_stack_entries = 85; |
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337 | num_es_stack_entries = 85; |
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338 | num_hs_stack_entries = 85; |
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339 | num_ls_stack_entries = 85; |
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340 | break; |
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341 | case CHIP_CYPRESS: |
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342 | case CHIP_HEMLOCK: |
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343 | num_ps_gprs = 93; |
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344 | num_vs_gprs = 46; |
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345 | num_temp_gprs = 4; |
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346 | num_gs_gprs = 31; |
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347 | num_es_gprs = 31; |
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348 | num_hs_gprs = 23; |
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349 | num_ls_gprs = 23; |
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350 | num_ps_threads = 128; |
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351 | num_vs_threads = 20; |
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352 | num_gs_threads = 20; |
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353 | num_es_threads = 20; |
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354 | num_hs_threads = 20; |
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355 | num_ls_threads = 20; |
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356 | num_ps_stack_entries = 85; |
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357 | num_vs_stack_entries = 85; |
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358 | num_gs_stack_entries = 85; |
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359 | num_es_stack_entries = 85; |
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360 | num_hs_stack_entries = 85; |
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361 | num_ls_stack_entries = 85; |
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362 | break; |
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363 | case CHIP_PALM: |
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364 | num_ps_gprs = 93; |
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365 | num_vs_gprs = 46; |
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366 | num_temp_gprs = 4; |
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367 | num_gs_gprs = 31; |
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368 | num_es_gprs = 31; |
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369 | num_hs_gprs = 23; |
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370 | num_ls_gprs = 23; |
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371 | num_ps_threads = 96; |
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372 | num_vs_threads = 16; |
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373 | num_gs_threads = 16; |
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374 | num_es_threads = 16; |
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375 | num_hs_threads = 16; |
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376 | num_ls_threads = 16; |
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377 | num_ps_stack_entries = 42; |
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378 | num_vs_stack_entries = 42; |
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379 | num_gs_stack_entries = 42; |
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380 | num_es_stack_entries = 42; |
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381 | num_hs_stack_entries = 42; |
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382 | num_ls_stack_entries = 42; |
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383 | break; |
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384 | case CHIP_SUMO: |
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385 | num_ps_gprs = 93; |
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386 | num_vs_gprs = 46; |
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387 | num_temp_gprs = 4; |
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388 | num_gs_gprs = 31; |
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389 | num_es_gprs = 31; |
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390 | num_hs_gprs = 23; |
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391 | num_ls_gprs = 23; |
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392 | num_ps_threads = 96; |
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393 | num_vs_threads = 25; |
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394 | num_gs_threads = 25; |
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395 | num_es_threads = 25; |
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396 | num_hs_threads = 25; |
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397 | num_ls_threads = 25; |
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398 | num_ps_stack_entries = 42; |
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399 | num_vs_stack_entries = 42; |
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400 | num_gs_stack_entries = 42; |
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401 | num_es_stack_entries = 42; |
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402 | num_hs_stack_entries = 42; |
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403 | num_ls_stack_entries = 42; |
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404 | break; |
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405 | case CHIP_SUMO2: |
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406 | num_ps_gprs = 93; |
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407 | num_vs_gprs = 46; |
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408 | num_temp_gprs = 4; |
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409 | num_gs_gprs = 31; |
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410 | num_es_gprs = 31; |
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411 | num_hs_gprs = 23; |
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412 | num_ls_gprs = 23; |
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413 | num_ps_threads = 96; |
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414 | num_vs_threads = 25; |
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415 | num_gs_threads = 25; |
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416 | num_es_threads = 25; |
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417 | num_hs_threads = 25; |
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418 | num_ls_threads = 25; |
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419 | num_ps_stack_entries = 85; |
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420 | num_vs_stack_entries = 85; |
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421 | num_gs_stack_entries = 85; |
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422 | num_es_stack_entries = 85; |
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423 | num_hs_stack_entries = 85; |
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424 | num_ls_stack_entries = 85; |
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425 | break; |
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426 | case CHIP_BARTS: |
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427 | num_ps_gprs = 93; |
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428 | num_vs_gprs = 46; |
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429 | num_temp_gprs = 4; |
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430 | num_gs_gprs = 31; |
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431 | num_es_gprs = 31; |
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432 | num_hs_gprs = 23; |
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433 | num_ls_gprs = 23; |
||
434 | num_ps_threads = 128; |
||
435 | num_vs_threads = 20; |
||
436 | num_gs_threads = 20; |
||
437 | num_es_threads = 20; |
||
438 | num_hs_threads = 20; |
||
439 | num_ls_threads = 20; |
||
440 | num_ps_stack_entries = 85; |
||
441 | num_vs_stack_entries = 85; |
||
442 | num_gs_stack_entries = 85; |
||
443 | num_es_stack_entries = 85; |
||
444 | num_hs_stack_entries = 85; |
||
445 | num_ls_stack_entries = 85; |
||
446 | break; |
||
447 | case CHIP_TURKS: |
||
448 | num_ps_gprs = 93; |
||
449 | num_vs_gprs = 46; |
||
450 | num_temp_gprs = 4; |
||
451 | num_gs_gprs = 31; |
||
452 | num_es_gprs = 31; |
||
453 | num_hs_gprs = 23; |
||
454 | num_ls_gprs = 23; |
||
455 | num_ps_threads = 128; |
||
456 | num_vs_threads = 20; |
||
457 | num_gs_threads = 20; |
||
458 | num_es_threads = 20; |
||
459 | num_hs_threads = 20; |
||
460 | num_ls_threads = 20; |
||
461 | num_ps_stack_entries = 42; |
||
462 | num_vs_stack_entries = 42; |
||
463 | num_gs_stack_entries = 42; |
||
464 | num_es_stack_entries = 42; |
||
465 | num_hs_stack_entries = 42; |
||
466 | num_ls_stack_entries = 42; |
||
467 | break; |
||
468 | case CHIP_CAICOS: |
||
469 | num_ps_gprs = 93; |
||
470 | num_vs_gprs = 46; |
||
471 | num_temp_gprs = 4; |
||
472 | num_gs_gprs = 31; |
||
473 | num_es_gprs = 31; |
||
474 | num_hs_gprs = 23; |
||
475 | num_ls_gprs = 23; |
||
476 | num_ps_threads = 128; |
||
477 | num_vs_threads = 10; |
||
478 | num_gs_threads = 10; |
||
479 | num_es_threads = 10; |
||
480 | num_hs_threads = 10; |
||
481 | num_ls_threads = 10; |
||
482 | num_ps_stack_entries = 42; |
||
483 | num_vs_stack_entries = 42; |
||
484 | num_gs_stack_entries = 42; |
||
485 | num_es_stack_entries = 42; |
||
486 | num_hs_stack_entries = 42; |
||
487 | num_ls_stack_entries = 42; |
||
488 | break; |
||
489 | } |
||
490 | |||
491 | if ((rdev->family == CHIP_CEDAR) || |
||
492 | (rdev->family == CHIP_PALM) || |
||
493 | (rdev->family == CHIP_SUMO) || |
||
494 | (rdev->family == CHIP_SUMO2) || |
||
495 | (rdev->family == CHIP_CAICOS)) |
||
496 | sq_config = 0; |
||
497 | else |
||
498 | sq_config = VC_ENABLE; |
||
499 | |||
500 | sq_config |= (EXPORT_SRC_C | |
||
501 | CS_PRIO(0) | |
||
502 | LS_PRIO(0) | |
||
503 | HS_PRIO(0) | |
||
504 | PS_PRIO(0) | |
||
505 | VS_PRIO(1) | |
||
506 | GS_PRIO(2) | |
||
507 | ES_PRIO(3)); |
||
508 | |||
509 | sq_gpr_resource_mgmt_1 = (NUM_PS_GPRS(num_ps_gprs) | |
||
510 | NUM_VS_GPRS(num_vs_gprs) | |
||
511 | NUM_CLAUSE_TEMP_GPRS(num_temp_gprs)); |
||
512 | sq_gpr_resource_mgmt_2 = (NUM_GS_GPRS(num_gs_gprs) | |
||
513 | NUM_ES_GPRS(num_es_gprs)); |
||
514 | sq_gpr_resource_mgmt_3 = (NUM_HS_GPRS(num_hs_gprs) | |
||
515 | NUM_LS_GPRS(num_ls_gprs)); |
||
516 | sq_thread_resource_mgmt = (NUM_PS_THREADS(num_ps_threads) | |
||
517 | NUM_VS_THREADS(num_vs_threads) | |
||
518 | NUM_GS_THREADS(num_gs_threads) | |
||
519 | NUM_ES_THREADS(num_es_threads)); |
||
520 | sq_thread_resource_mgmt_2 = (NUM_HS_THREADS(num_hs_threads) | |
||
521 | NUM_LS_THREADS(num_ls_threads)); |
||
522 | sq_stack_resource_mgmt_1 = (NUM_PS_STACK_ENTRIES(num_ps_stack_entries) | |
||
523 | NUM_VS_STACK_ENTRIES(num_vs_stack_entries)); |
||
524 | sq_stack_resource_mgmt_2 = (NUM_GS_STACK_ENTRIES(num_gs_stack_entries) | |
||
525 | NUM_ES_STACK_ENTRIES(num_es_stack_entries)); |
||
526 | sq_stack_resource_mgmt_3 = (NUM_HS_STACK_ENTRIES(num_hs_stack_entries) | |
||
527 | NUM_LS_STACK_ENTRIES(num_ls_stack_entries)); |
||
528 | |||
529 | /* disable dyn gprs */ |
||
530 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
||
531 | radeon_ring_write(rdev, (SQ_DYN_GPR_CNTL_PS_FLUSH_REQ - PACKET3_SET_CONFIG_REG_START) >> 2); |
||
532 | radeon_ring_write(rdev, 0); |
||
533 | |||
534 | /* setup LDS */ |
||
535 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 1)); |
||
536 | radeon_ring_write(rdev, (SQ_LDS_RESOURCE_MGMT - PACKET3_SET_CONFIG_REG_START) >> 2); |
||
537 | radeon_ring_write(rdev, 0x10001000); |
||
538 | |||
539 | /* SQ config */ |
||
540 | radeon_ring_write(rdev, PACKET3(PACKET3_SET_CONFIG_REG, 11)); |
||
541 | radeon_ring_write(rdev, (SQ_CONFIG - PACKET3_SET_CONFIG_REG_START) >> 2); |
||
542 | radeon_ring_write(rdev, sq_config); |
||
543 | radeon_ring_write(rdev, sq_gpr_resource_mgmt_1); |
||
544 | radeon_ring_write(rdev, sq_gpr_resource_mgmt_2); |
||
545 | radeon_ring_write(rdev, sq_gpr_resource_mgmt_3); |
||
546 | radeon_ring_write(rdev, 0); |
||
547 | radeon_ring_write(rdev, 0); |
||
548 | radeon_ring_write(rdev, sq_thread_resource_mgmt); |
||
549 | radeon_ring_write(rdev, sq_thread_resource_mgmt_2); |
||
550 | radeon_ring_write(rdev, sq_stack_resource_mgmt_1); |
||
551 | radeon_ring_write(rdev, sq_stack_resource_mgmt_2); |
||
552 | radeon_ring_write(rdev, sq_stack_resource_mgmt_3); |
||
553 | } |
||
554 | |||
555 | /* CONTEXT_CONTROL */ |
||
556 | radeon_ring_write(rdev, 0xc0012800); |
||
557 | radeon_ring_write(rdev, 0x80000000); |
||
558 | radeon_ring_write(rdev, 0x80000000); |
||
559 | |||
560 | /* SQ_VTX_BASE_VTX_LOC */ |
||
561 | radeon_ring_write(rdev, 0xc0026f00); |
||
562 | radeon_ring_write(rdev, 0x00000000); |
||
563 | radeon_ring_write(rdev, 0x00000000); |
||
564 | radeon_ring_write(rdev, 0x00000000); |
||
565 | |||
566 | /* SET_SAMPLER */ |
||
567 | radeon_ring_write(rdev, 0xc0036e00); |
||
568 | radeon_ring_write(rdev, 0x00000000); |
||
569 | radeon_ring_write(rdev, 0x00000012); |
||
570 | radeon_ring_write(rdev, 0x00000000); |
||
571 | radeon_ring_write(rdev, 0x00000000); |
||
572 | |||
573 | /* set to DX10/11 mode */ |
||
574 | radeon_ring_write(rdev, PACKET3(PACKET3_MODE_CONTROL, 0)); |
||
575 | radeon_ring_write(rdev, 1); |
||
576 | |||
577 | /* emit an IB pointing at default state */ |
||
578 | dwords = ALIGN(rdev->r600_blit.state_len, 0x10); |
||
579 | gpu_addr = rdev->r600_blit.shader_gpu_addr + rdev->r600_blit.state_offset; |
||
580 | radeon_ring_write(rdev, PACKET3(PACKET3_INDIRECT_BUFFER, 2)); |
||
581 | radeon_ring_write(rdev, gpu_addr & 0xFFFFFFFC); |
||
582 | radeon_ring_write(rdev, upper_32_bits(gpu_addr) & 0xFF); |
||
583 | radeon_ring_write(rdev, dwords); |
||
584 | |||
585 | } |
||
586 | |||
587 | static inline uint32_t i2f(uint32_t input) |
||
588 | { |
||
589 | u32 result, i, exponent, fraction; |
||
590 | |||
591 | if ((input & 0x3fff) == 0) |
||
592 | result = 0; /* 0 is a special case */ |
||
593 | else { |
||
594 | exponent = 140; /* exponent biased by 127; */ |
||
595 | fraction = (input & 0x3fff) << 10; /* cheat and only |
||
596 | handle numbers below 2^^15 */ |
||
597 | for (i = 0; i < 14; i++) { |
||
598 | if (fraction & 0x800000) |
||
599 | break; |
||
600 | else { |
||
601 | fraction = fraction << 1; /* keep |
||
602 | shifting left until top bit = 1 */ |
||
603 | exponent = exponent - 1; |
||
604 | } |
||
605 | } |
||
606 | result = exponent << 23 | (fraction & 0x7fffff); /* mask |
||
607 | off top bit; assumed 1 */ |
||
608 | } |
||
609 | return result; |
||
610 | } |
||
611 | |||
612 | int evergreen_blit_init(struct radeon_device *rdev) |
||
613 | { |
||
614 | u32 obj_size; |
||
615 | int i, r, dwords; |
||
616 | void *ptr; |
||
617 | u32 packet2s[16]; |
||
618 | int num_packet2s = 0; |
||
619 | |||
620 | /* pin copy shader into vram if already initialized */ |
||
621 | if (rdev->r600_blit.shader_obj) |
||
622 | goto done; |
||
623 | |||
624 | mutex_init(&rdev->r600_blit.mutex); |
||
625 | rdev->r600_blit.state_offset = 0; |
||
626 | |||
627 | if (rdev->family < CHIP_CAYMAN) |
||
628 | rdev->r600_blit.state_len = evergreen_default_size; |
||
629 | else |
||
630 | rdev->r600_blit.state_len = cayman_default_size; |
||
631 | |||
632 | dwords = rdev->r600_blit.state_len; |
||
633 | while (dwords & 0xf) { |
||
634 | packet2s[num_packet2s++] = cpu_to_le32(PACKET2(0)); |
||
635 | dwords++; |
||
636 | } |
||
637 | |||
638 | obj_size = dwords * 4; |
||
639 | obj_size = ALIGN(obj_size, 256); |
||
640 | |||
641 | rdev->r600_blit.vs_offset = obj_size; |
||
642 | if (rdev->family < CHIP_CAYMAN) |
||
643 | obj_size += evergreen_vs_size * 4; |
||
644 | else |
||
645 | obj_size += cayman_vs_size * 4; |
||
646 | obj_size = ALIGN(obj_size, 256); |
||
647 | |||
648 | rdev->r600_blit.ps_offset = obj_size; |
||
649 | if (rdev->family < CHIP_CAYMAN) |
||
650 | obj_size += evergreen_ps_size * 4; |
||
651 | else |
||
652 | obj_size += cayman_ps_size * 4; |
||
653 | obj_size = ALIGN(obj_size, 256); |
||
654 | |||
655 | r = radeon_bo_create(rdev, obj_size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM, |
||
656 | &rdev->r600_blit.shader_obj); |
||
657 | if (r) { |
||
658 | DRM_ERROR("evergreen failed to allocate shader\n"); |
||
659 | return r; |
||
660 | } |
||
661 | |||
662 | DRM_DEBUG("evergreen blit allocated bo %08x vs %08x ps %08x\n", |
||
663 | obj_size, |
||
664 | rdev->r600_blit.vs_offset, rdev->r600_blit.ps_offset); |
||
665 | |||
666 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
||
667 | if (unlikely(r != 0)) |
||
668 | return r; |
||
669 | r = radeon_bo_kmap(rdev->r600_blit.shader_obj, &ptr); |
||
670 | if (r) { |
||
671 | DRM_ERROR("failed to map blit object %d\n", r); |
||
672 | return r; |
||
673 | } |
||
674 | |||
675 | if (rdev->family < CHIP_CAYMAN) { |
||
676 | memcpy(ptr + rdev->r600_blit.state_offset, |
||
677 | evergreen_default_state, rdev->r600_blit.state_len * 4); |
||
678 | |||
679 | if (num_packet2s) |
||
680 | memcpy(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), |
||
681 | packet2s, num_packet2s * 4); |
||
682 | for (i = 0; i < evergreen_vs_size; i++) |
||
683 | *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(evergreen_vs[i]); |
||
684 | for (i = 0; i < evergreen_ps_size; i++) |
||
685 | *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(evergreen_ps[i]); |
||
686 | } else { |
||
687 | memcpy(ptr + rdev->r600_blit.state_offset, |
||
688 | cayman_default_state, rdev->r600_blit.state_len * 4); |
||
689 | |||
690 | if (num_packet2s) |
||
691 | memcpy(ptr + rdev->r600_blit.state_offset + (rdev->r600_blit.state_len * 4), |
||
692 | packet2s, num_packet2s * 4); |
||
693 | for (i = 0; i < cayman_vs_size; i++) |
||
694 | *(u32 *)((unsigned long)ptr + rdev->r600_blit.vs_offset + i * 4) = cpu_to_le32(cayman_vs[i]); |
||
695 | for (i = 0; i < cayman_ps_size; i++) |
||
696 | *(u32 *)((unsigned long)ptr + rdev->r600_blit.ps_offset + i * 4) = cpu_to_le32(cayman_ps[i]); |
||
697 | } |
||
698 | radeon_bo_kunmap(rdev->r600_blit.shader_obj); |
||
699 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
||
700 | |||
701 | done: |
||
702 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
||
703 | if (unlikely(r != 0)) |
||
704 | return r; |
||
705 | r = radeon_bo_pin(rdev->r600_blit.shader_obj, RADEON_GEM_DOMAIN_VRAM, |
||
706 | &rdev->r600_blit.shader_gpu_addr); |
||
707 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
||
708 | if (r) { |
||
709 | dev_err(rdev->dev, "(%d) pin blit object failed\n", r); |
||
710 | return r; |
||
711 | } |
||
712 | // radeon_ttm_set_active_vram_size(rdev, rdev->mc.real_vram_size); |
||
713 | return 0; |
||
714 | } |
||
715 | |||
716 | void evergreen_blit_fini(struct radeon_device *rdev) |
||
717 | { |
||
718 | int r; |
||
719 | |||
720 | // radeon_ttm_set_active_vram_size(rdev, rdev->mc.visible_vram_size); |
||
721 | if (rdev->r600_blit.shader_obj == NULL) |
||
722 | return; |
||
723 | /* If we can't reserve the bo, unref should be enough to destroy |
||
724 | * it when it becomes idle. |
||
725 | */ |
||
726 | r = radeon_bo_reserve(rdev->r600_blit.shader_obj, false); |
||
727 | if (!r) { |
||
728 | radeon_bo_unpin(rdev->r600_blit.shader_obj); |
||
729 | radeon_bo_unreserve(rdev->r600_blit.shader_obj); |
||
730 | } |
||
731 | radeon_bo_unref(&rdev->r600_blit.shader_obj); |
||
732 | } |
||
733 | |||
734 | static int evergreen_vb_ib_get(struct radeon_device *rdev) |
||
735 | { |
||
736 | int r; |
||
737 | r = radeon_ib_get(rdev, &rdev->r600_blit.vb_ib); |
||
738 | if (r) { |
||
739 | DRM_ERROR("failed to get IB for vertex buffer\n"); |
||
740 | return r; |
||
741 | } |
||
742 | |||
743 | rdev->r600_blit.vb_total = 64*1024; |
||
744 | rdev->r600_blit.vb_used = 0; |
||
745 | return 0; |
||
746 | } |
||
747 | |||
748 | static void evergreen_vb_ib_put(struct radeon_device *rdev) |
||
749 | { |
||
750 | radeon_fence_emit(rdev, rdev->r600_blit.vb_ib->fence); |
||
751 | radeon_ib_free(rdev, &rdev->r600_blit.vb_ib); |
||
752 | } |
||
753 | |||
754 | int evergreen_blit_prepare_copy(struct radeon_device *rdev, int size_bytes) |
||
755 | { |
||
756 | int r; |
||
757 | int ring_size, line_size; |
||
758 | int max_size; |
||
759 | /* loops of emits + fence emit possible */ |
||
760 | int dwords_per_loop = 74, num_loops; |
||
761 | |||
762 | r = evergreen_vb_ib_get(rdev); |
||
763 | if (r) |
||
764 | return r; |
||
765 | |||
766 | /* 8 bpp vs 32 bpp for xfer unit */ |
||
767 | if (size_bytes & 3) |
||
768 | line_size = 8192; |
||
769 | else |
||
770 | line_size = 8192 * 4; |
||
771 | |||
772 | max_size = 8192 * line_size; |
||
773 | |||
774 | /* major loops cover the max size transfer */ |
||
775 | num_loops = ((size_bytes + max_size) / max_size); |
||
776 | /* minor loops cover the extra non aligned bits */ |
||
777 | num_loops += ((size_bytes % line_size) ? 1 : 0); |
||
778 | /* calculate number of loops correctly */ |
||
779 | ring_size = num_loops * dwords_per_loop; |
||
780 | /* set default + shaders */ |
||
781 | ring_size += 55; /* shaders + def state */ |
||
782 | ring_size += 10; /* fence emit for VB IB */ |
||
783 | ring_size += 5; /* done copy */ |
||
784 | ring_size += 10; /* fence emit for done copy */ |
||
785 | r = radeon_ring_lock(rdev, ring_size); |
||
786 | if (r) |
||
787 | return r; |
||
788 | |||
789 | set_default_state(rdev); /* 36 */ |
||
790 | set_shaders(rdev); /* 16 */ |
||
791 | return 0; |
||
792 | } |
||
793 | |||
794 | void evergreen_blit_done_copy(struct radeon_device *rdev, struct radeon_fence *fence) |
||
795 | { |
||
796 | int r; |
||
797 | |||
798 | if (rdev->r600_blit.vb_ib) |
||
799 | evergreen_vb_ib_put(rdev); |
||
800 | |||
801 | if (fence) |
||
802 | r = radeon_fence_emit(rdev, fence); |
||
803 | |||
804 | radeon_ring_unlock_commit(rdev); |
||
805 | } |
||
806 | |||
807 | void evergreen_kms_blit_copy(struct radeon_device *rdev, |
||
808 | u64 src_gpu_addr, u64 dst_gpu_addr, |
||
809 | int size_bytes) |
||
810 | { |
||
811 | int max_bytes; |
||
812 | u64 vb_gpu_addr; |
||
813 | u32 *vb; |
||
814 | |||
815 | DRM_DEBUG("emitting copy %16llx %16llx %d %d\n", src_gpu_addr, dst_gpu_addr, |
||
816 | size_bytes, rdev->r600_blit.vb_used); |
||
817 | vb = (u32 *)(rdev->r600_blit.vb_ib->ptr + rdev->r600_blit.vb_used); |
||
818 | if ((size_bytes & 3) || (src_gpu_addr & 3) || (dst_gpu_addr & 3)) { |
||
819 | max_bytes = 8192; |
||
820 | |||
821 | while (size_bytes) { |
||
822 | int cur_size = size_bytes; |
||
823 | int src_x = src_gpu_addr & 255; |
||
824 | int dst_x = dst_gpu_addr & 255; |
||
825 | int h = 1; |
||
826 | src_gpu_addr = src_gpu_addr & ~255ULL; |
||
827 | dst_gpu_addr = dst_gpu_addr & ~255ULL; |
||
828 | |||
829 | if (!src_x && !dst_x) { |
||
830 | h = (cur_size / max_bytes); |
||
831 | if (h > 8192) |
||
832 | h = 8192; |
||
833 | if (h == 0) |
||
834 | h = 1; |
||
835 | else |
||
836 | cur_size = max_bytes; |
||
837 | } else { |
||
838 | if (cur_size > max_bytes) |
||
839 | cur_size = max_bytes; |
||
840 | if (cur_size > (max_bytes - dst_x)) |
||
841 | cur_size = (max_bytes - dst_x); |
||
842 | if (cur_size > (max_bytes - src_x)) |
||
843 | cur_size = (max_bytes - src_x); |
||
844 | } |
||
845 | |||
846 | if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) { |
||
847 | // WARN_ON(1); |
||
848 | } |
||
849 | |||
850 | vb[0] = i2f(dst_x); |
||
851 | vb[1] = 0; |
||
852 | vb[2] = i2f(src_x); |
||
853 | vb[3] = 0; |
||
854 | |||
855 | vb[4] = i2f(dst_x); |
||
856 | vb[5] = i2f(h); |
||
857 | vb[6] = i2f(src_x); |
||
858 | vb[7] = i2f(h); |
||
859 | |||
860 | vb[8] = i2f(dst_x + cur_size); |
||
861 | vb[9] = i2f(h); |
||
862 | vb[10] = i2f(src_x + cur_size); |
||
863 | vb[11] = i2f(h); |
||
864 | |||
865 | /* src 10 */ |
||
866 | set_tex_resource(rdev, FMT_8, |
||
867 | src_x + cur_size, h, src_x + cur_size, |
||
868 | src_gpu_addr); |
||
869 | |||
870 | /* 5 */ |
||
871 | cp_set_surface_sync(rdev, |
||
872 | PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); |
||
873 | |||
874 | |||
875 | /* dst 17 */ |
||
876 | set_render_target(rdev, COLOR_8, |
||
877 | dst_x + cur_size, h, |
||
878 | dst_gpu_addr); |
||
879 | |||
880 | /* scissors 12 */ |
||
881 | set_scissors(rdev, dst_x, 0, dst_x + cur_size, h); |
||
882 | |||
883 | /* 15 */ |
||
884 | vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used; |
||
885 | set_vtx_resource(rdev, vb_gpu_addr); |
||
886 | |||
887 | /* draw 10 */ |
||
888 | draw_auto(rdev); |
||
889 | |||
890 | /* 5 */ |
||
891 | cp_set_surface_sync(rdev, |
||
892 | PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, |
||
893 | cur_size * h, dst_gpu_addr); |
||
894 | |||
895 | vb += 12; |
||
896 | rdev->r600_blit.vb_used += 12 * 4; |
||
897 | |||
898 | src_gpu_addr += cur_size * h; |
||
899 | dst_gpu_addr += cur_size * h; |
||
900 | size_bytes -= cur_size * h; |
||
901 | } |
||
902 | } else { |
||
903 | max_bytes = 8192 * 4; |
||
904 | |||
905 | while (size_bytes) { |
||
906 | int cur_size = size_bytes; |
||
907 | int src_x = (src_gpu_addr & 255); |
||
908 | int dst_x = (dst_gpu_addr & 255); |
||
909 | int h = 1; |
||
910 | src_gpu_addr = src_gpu_addr & ~255ULL; |
||
911 | dst_gpu_addr = dst_gpu_addr & ~255ULL; |
||
912 | |||
913 | if (!src_x && !dst_x) { |
||
914 | h = (cur_size / max_bytes); |
||
915 | if (h > 8192) |
||
916 | h = 8192; |
||
917 | if (h == 0) |
||
918 | h = 1; |
||
919 | else |
||
920 | cur_size = max_bytes; |
||
921 | } else { |
||
922 | if (cur_size > max_bytes) |
||
923 | cur_size = max_bytes; |
||
924 | if (cur_size > (max_bytes - dst_x)) |
||
925 | cur_size = (max_bytes - dst_x); |
||
926 | if (cur_size > (max_bytes - src_x)) |
||
927 | cur_size = (max_bytes - src_x); |
||
928 | } |
||
929 | |||
930 | if ((rdev->r600_blit.vb_used + 48) > rdev->r600_blit.vb_total) { |
||
931 | // WARN_ON(1); |
||
932 | } |
||
933 | |||
934 | vb[0] = i2f(dst_x / 4); |
||
935 | vb[1] = 0; |
||
936 | vb[2] = i2f(src_x / 4); |
||
937 | vb[3] = 0; |
||
938 | |||
939 | vb[4] = i2f(dst_x / 4); |
||
940 | vb[5] = i2f(h); |
||
941 | vb[6] = i2f(src_x / 4); |
||
942 | vb[7] = i2f(h); |
||
943 | |||
944 | vb[8] = i2f((dst_x + cur_size) / 4); |
||
945 | vb[9] = i2f(h); |
||
946 | vb[10] = i2f((src_x + cur_size) / 4); |
||
947 | vb[11] = i2f(h); |
||
948 | |||
949 | /* src 10 */ |
||
950 | set_tex_resource(rdev, FMT_8_8_8_8, |
||
951 | (src_x + cur_size) / 4, |
||
952 | h, (src_x + cur_size) / 4, |
||
953 | src_gpu_addr); |
||
954 | /* 5 */ |
||
955 | cp_set_surface_sync(rdev, |
||
956 | PACKET3_TC_ACTION_ENA, (src_x + cur_size * h), src_gpu_addr); |
||
957 | |||
958 | /* dst 17 */ |
||
959 | set_render_target(rdev, COLOR_8_8_8_8, |
||
960 | (dst_x + cur_size) / 4, h, |
||
961 | dst_gpu_addr); |
||
962 | |||
963 | /* scissors 12 */ |
||
964 | set_scissors(rdev, (dst_x / 4), 0, (dst_x + cur_size / 4), h); |
||
965 | |||
966 | /* Vertex buffer setup 15 */ |
||
967 | vb_gpu_addr = rdev->r600_blit.vb_ib->gpu_addr + rdev->r600_blit.vb_used; |
||
968 | set_vtx_resource(rdev, vb_gpu_addr); |
||
969 | |||
970 | /* draw 10 */ |
||
971 | draw_auto(rdev); |
||
972 | |||
973 | /* 5 */ |
||
974 | cp_set_surface_sync(rdev, |
||
975 | PACKET3_CB_ACTION_ENA | PACKET3_CB0_DEST_BASE_ENA, |
||
976 | cur_size * h, dst_gpu_addr); |
||
977 | |||
978 | /* 74 ring dwords per loop */ |
||
979 | vb += 12; |
||
980 | rdev->r600_blit.vb_used += 12 * 4; |
||
981 | |||
982 | src_gpu_addr += cur_size * h; |
||
983 | dst_gpu_addr += cur_size * h; |
||
984 | size_bytes -= cur_size * h; |
||
985 | } |
||
986 | } |
||
987 | }>>>>>>>>><>><>>><>>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>>><>><>><>><>><>><>><>><>><>><>><>><>> |
||
988 |