Rev 6104 | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
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5078 | serge | 1 | /* |
2 | * Copyright 2013 Advanced Micro Devices, Inc. |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice shall be included in |
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12 | * all copies or substantial portions of the Software. |
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13 | * |
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14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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15 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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16 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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17 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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18 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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20 | * OTHER DEALINGS IN THE SOFTWARE. |
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21 | * |
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22 | */ |
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23 | #include |
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24 | #include |
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25 | #include "radeon.h" |
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6104 | serge | 26 | #include "radeon_audio.h" |
5078 | serge | 27 | #include "sid.h" |
28 | |||
6104 | serge | 29 | #define DCE8_DCCG_AUDIO_DTO1_PHASE 0x05b8 |
30 | #define DCE8_DCCG_AUDIO_DTO1_MODULE 0x05bc |
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31 | |||
32 | u32 dce6_endpoint_rreg(struct radeon_device *rdev, |
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5078 | serge | 33 | u32 block_offset, u32 reg) |
34 | { |
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35 | unsigned long flags; |
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36 | u32 r; |
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37 | |||
38 | spin_lock_irqsave(&rdev->end_idx_lock, flags); |
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39 | WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); |
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40 | r = RREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset); |
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41 | spin_unlock_irqrestore(&rdev->end_idx_lock, flags); |
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42 | |||
43 | return r; |
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44 | } |
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45 | |||
6104 | serge | 46 | void dce6_endpoint_wreg(struct radeon_device *rdev, |
5078 | serge | 47 | u32 block_offset, u32 reg, u32 v) |
48 | { |
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49 | unsigned long flags; |
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50 | |||
51 | spin_lock_irqsave(&rdev->end_idx_lock, flags); |
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52 | if (ASIC_IS_DCE8(rdev)) |
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53 | WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, reg); |
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54 | else |
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55 | WREG32(AZ_F0_CODEC_ENDPOINT_INDEX + block_offset, |
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56 | AZ_ENDPOINT_REG_WRITE_EN | AZ_ENDPOINT_REG_INDEX(reg)); |
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57 | WREG32(AZ_F0_CODEC_ENDPOINT_DATA + block_offset, v); |
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58 | spin_unlock_irqrestore(&rdev->end_idx_lock, flags); |
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59 | } |
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60 | |||
61 | static void dce6_afmt_get_connected_pins(struct radeon_device *rdev) |
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62 | { |
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63 | int i; |
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64 | u32 offset, tmp; |
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65 | |||
66 | for (i = 0; i < rdev->audio.num_pins; i++) { |
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67 | offset = rdev->audio.pin[i].offset; |
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68 | tmp = RREG32_ENDPOINT(offset, |
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69 | AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT); |
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70 | if (((tmp & PORT_CONNECTIVITY_MASK) >> PORT_CONNECTIVITY_SHIFT) == 1) |
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71 | rdev->audio.pin[i].connected = false; |
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72 | else |
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73 | rdev->audio.pin[i].connected = true; |
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74 | } |
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75 | } |
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76 | |||
77 | struct r600_audio_pin *dce6_audio_get_pin(struct radeon_device *rdev) |
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78 | { |
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6104 | serge | 79 | struct drm_encoder *encoder; |
80 | struct radeon_encoder *radeon_encoder; |
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81 | struct radeon_encoder_atom_dig *dig; |
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82 | struct r600_audio_pin *pin = NULL; |
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83 | int i, pin_count; |
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5078 | serge | 84 | |
85 | dce6_afmt_get_connected_pins(rdev); |
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86 | |||
87 | for (i = 0; i < rdev->audio.num_pins; i++) { |
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6104 | serge | 88 | if (rdev->audio.pin[i].connected) { |
89 | pin = &rdev->audio.pin[i]; |
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90 | pin_count = 0; |
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91 | |||
92 | list_for_each_entry(encoder, &rdev->ddev->mode_config.encoder_list, head) { |
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93 | if (radeon_encoder_is_digital(encoder)) { |
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94 | radeon_encoder = to_radeon_encoder(encoder); |
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95 | dig = radeon_encoder->enc_priv; |
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96 | if (dig->pin == pin) |
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97 | pin_count++; |
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98 | } |
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99 | } |
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100 | |||
101 | if (pin_count == 0) |
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102 | return pin; |
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103 | } |
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5078 | serge | 104 | } |
6104 | serge | 105 | if (!pin) |
106 | DRM_ERROR("No connected audio pins found!\n"); |
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107 | return pin; |
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5078 | serge | 108 | } |
109 | |||
110 | void dce6_afmt_select_pin(struct drm_encoder *encoder) |
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111 | { |
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112 | struct radeon_device *rdev = encoder->dev->dev_private; |
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113 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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114 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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115 | |||
6104 | serge | 116 | if (!dig || !dig->afmt || !dig->pin) |
5078 | serge | 117 | return; |
118 | |||
6104 | serge | 119 | WREG32(AFMT_AUDIO_SRC_CONTROL + dig->afmt->offset, |
120 | AFMT_AUDIO_SRC_SELECT(dig->pin->id)); |
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5078 | serge | 121 | } |
122 | |||
123 | void dce6_afmt_write_latency_fields(struct drm_encoder *encoder, |
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6104 | serge | 124 | struct drm_connector *connector, |
5078 | serge | 125 | struct drm_display_mode *mode) |
126 | { |
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127 | struct radeon_device *rdev = encoder->dev->dev_private; |
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128 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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129 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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6104 | serge | 130 | u32 tmp = 0; |
5078 | serge | 131 | |
6104 | serge | 132 | if (!dig || !dig->afmt || !dig->pin) |
5078 | serge | 133 | return; |
134 | |||
135 | if (mode->flags & DRM_MODE_FLAG_INTERLACE) { |
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136 | if (connector->latency_present[1]) |
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137 | tmp = VIDEO_LIPSYNC(connector->video_latency[1]) | |
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138 | AUDIO_LIPSYNC(connector->audio_latency[1]); |
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139 | else |
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140 | tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0); |
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141 | } else { |
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142 | if (connector->latency_present[0]) |
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143 | tmp = VIDEO_LIPSYNC(connector->video_latency[0]) | |
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144 | AUDIO_LIPSYNC(connector->audio_latency[0]); |
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145 | else |
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146 | tmp = VIDEO_LIPSYNC(0) | AUDIO_LIPSYNC(0); |
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147 | } |
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6104 | serge | 148 | WREG32_ENDPOINT(dig->pin->offset, |
149 | AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC, tmp); |
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5078 | serge | 150 | } |
151 | |||
6104 | serge | 152 | void dce6_afmt_hdmi_write_speaker_allocation(struct drm_encoder *encoder, |
153 | u8 *sadb, int sad_count) |
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5078 | serge | 154 | { |
155 | struct radeon_device *rdev = encoder->dev->dev_private; |
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156 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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157 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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6104 | serge | 158 | u32 tmp; |
5078 | serge | 159 | |
6104 | serge | 160 | if (!dig || !dig->afmt || !dig->pin) |
5078 | serge | 161 | return; |
162 | |||
163 | /* program the speaker allocation */ |
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6104 | serge | 164 | tmp = RREG32_ENDPOINT(dig->pin->offset, |
165 | AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); |
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5078 | serge | 166 | tmp &= ~(DP_CONNECTION | SPEAKER_ALLOCATION_MASK); |
167 | /* set HDMI mode */ |
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168 | tmp |= HDMI_CONNECTION; |
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169 | if (sad_count) |
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170 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
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171 | else |
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172 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
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6104 | serge | 173 | WREG32_ENDPOINT(dig->pin->offset, |
174 | AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); |
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5078 | serge | 175 | } |
176 | |||
6104 | serge | 177 | void dce6_afmt_dp_write_speaker_allocation(struct drm_encoder *encoder, |
178 | u8 *sadb, int sad_count) |
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5078 | serge | 179 | { |
180 | struct radeon_device *rdev = encoder->dev->dev_private; |
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181 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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182 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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6104 | serge | 183 | u32 tmp; |
5078 | serge | 184 | |
6104 | serge | 185 | if (!dig || !dig->afmt || !dig->pin) |
186 | return; |
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187 | |||
188 | /* program the speaker allocation */ |
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189 | tmp = RREG32_ENDPOINT(dig->pin->offset, |
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190 | AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER); |
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191 | tmp &= ~(HDMI_CONNECTION | SPEAKER_ALLOCATION_MASK); |
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192 | /* set DP mode */ |
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193 | tmp |= DP_CONNECTION; |
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194 | if (sad_count) |
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195 | tmp |= SPEAKER_ALLOCATION(sadb[0]); |
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196 | else |
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197 | tmp |= SPEAKER_ALLOCATION(5); /* stereo */ |
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198 | WREG32_ENDPOINT(dig->pin->offset, |
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199 | AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER, tmp); |
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200 | } |
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201 | |||
202 | void dce6_afmt_write_sad_regs(struct drm_encoder *encoder, |
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203 | struct cea_sad *sads, int sad_count) |
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204 | { |
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205 | int i; |
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206 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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207 | struct radeon_encoder_atom_dig *dig = radeon_encoder->enc_priv; |
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208 | struct radeon_device *rdev = encoder->dev->dev_private; |
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5078 | serge | 209 | static const u16 eld_reg_to_type[][2] = { |
210 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0, HDMI_AUDIO_CODING_TYPE_PCM }, |
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211 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1, HDMI_AUDIO_CODING_TYPE_AC3 }, |
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212 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2, HDMI_AUDIO_CODING_TYPE_MPEG1 }, |
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213 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3, HDMI_AUDIO_CODING_TYPE_MP3 }, |
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214 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4, HDMI_AUDIO_CODING_TYPE_MPEG2 }, |
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215 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5, HDMI_AUDIO_CODING_TYPE_AAC_LC }, |
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216 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6, HDMI_AUDIO_CODING_TYPE_DTS }, |
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217 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7, HDMI_AUDIO_CODING_TYPE_ATRAC }, |
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218 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9, HDMI_AUDIO_CODING_TYPE_EAC3 }, |
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219 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10, HDMI_AUDIO_CODING_TYPE_DTS_HD }, |
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220 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11, HDMI_AUDIO_CODING_TYPE_MLP }, |
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221 | { AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13, HDMI_AUDIO_CODING_TYPE_WMA_PRO }, |
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222 | }; |
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223 | |||
6104 | serge | 224 | if (!dig || !dig->afmt || !dig->pin) |
5078 | serge | 225 | return; |
226 | |||
227 | for (i = 0; i < ARRAY_SIZE(eld_reg_to_type); i++) { |
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228 | u32 value = 0; |
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229 | u8 stereo_freqs = 0; |
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230 | int max_channels = -1; |
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231 | int j; |
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232 | |||
233 | for (j = 0; j < sad_count; j++) { |
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234 | struct cea_sad *sad = &sads[j]; |
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235 | |||
236 | if (sad->format == eld_reg_to_type[i][1]) { |
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237 | if (sad->channels > max_channels) { |
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238 | value = MAX_CHANNELS(sad->channels) | |
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239 | DESCRIPTOR_BYTE_2(sad->byte2) | |
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240 | SUPPORTED_FREQUENCIES(sad->freq); |
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241 | max_channels = sad->channels; |
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242 | } |
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243 | |||
244 | if (sad->format == HDMI_AUDIO_CODING_TYPE_PCM) |
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245 | stereo_freqs |= sad->freq; |
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246 | else |
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247 | break; |
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248 | } |
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249 | } |
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250 | |||
251 | value |= SUPPORTED_FREQUENCIES_STEREO(stereo_freqs); |
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252 | |||
6104 | serge | 253 | WREG32_ENDPOINT(dig->pin->offset, eld_reg_to_type[i][0], value); |
5078 | serge | 254 | } |
255 | } |
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256 | |||
257 | void dce6_audio_enable(struct radeon_device *rdev, |
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258 | struct r600_audio_pin *pin, |
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5271 | serge | 259 | u8 enable_mask) |
5078 | serge | 260 | { |
261 | if (!pin) |
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262 | return; |
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263 | |||
5271 | serge | 264 | WREG32_ENDPOINT(pin->offset, AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL, |
265 | enable_mask ? AUDIO_ENABLED : 0); |
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5078 | serge | 266 | } |
267 | |||
6104 | serge | 268 | void dce6_hdmi_audio_set_dto(struct radeon_device *rdev, |
269 | struct radeon_crtc *crtc, unsigned int clock) |
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5078 | serge | 270 | { |
6104 | serge | 271 | /* Two dtos; generally use dto0 for HDMI */ |
272 | u32 value = 0; |
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5078 | serge | 273 | |
6104 | serge | 274 | if (crtc) |
275 | value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); |
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5078 | serge | 276 | |
6104 | serge | 277 | WREG32(DCCG_AUDIO_DTO_SOURCE, value); |
5078 | serge | 278 | |
6104 | serge | 279 | /* Express [24MHz / target pixel clock] as an exact rational |
280 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
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281 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
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282 | */ |
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283 | WREG32(DCCG_AUDIO_DTO0_PHASE, 24000); |
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284 | WREG32(DCCG_AUDIO_DTO0_MODULE, clock); |
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5078 | serge | 285 | } |
286 | |||
6104 | serge | 287 | void dce6_dp_audio_set_dto(struct radeon_device *rdev, |
288 | struct radeon_crtc *crtc, unsigned int clock) |
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5078 | serge | 289 | { |
6104 | serge | 290 | /* Two dtos; generally use dto1 for DP */ |
291 | u32 value = 0; |
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292 | value |= DCCG_AUDIO_DTO_SEL; |
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5078 | serge | 293 | |
6104 | serge | 294 | if (crtc) |
295 | value |= DCCG_AUDIO_DTO0_SOURCE_SEL(crtc->crtc_id); |
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5078 | serge | 296 | |
6104 | serge | 297 | WREG32(DCCG_AUDIO_DTO_SOURCE, value); |
5078 | serge | 298 | |
6104 | serge | 299 | /* Express [24MHz / target pixel clock] as an exact rational |
300 | * number (coefficient of two integer numbers. DCCG_AUDIO_DTOx_PHASE |
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301 | * is the numerator, DCCG_AUDIO_DTOx_MODULE is the denominator |
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302 | */ |
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303 | if (ASIC_IS_DCE8(rdev)) { |
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6321 | serge | 304 | unsigned int div = (RREG32(DENTIST_DISPCLK_CNTL) & |
305 | DENTIST_DPREFCLK_WDIVIDER_MASK) >> |
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306 | DENTIST_DPREFCLK_WDIVIDER_SHIFT; |
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307 | div = radeon_audio_decode_dfs_div(div); |
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308 | |||
309 | if (div) |
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310 | clock = clock * 100 / div; |
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311 | |||
6104 | serge | 312 | WREG32(DCE8_DCCG_AUDIO_DTO1_PHASE, 24000); |
313 | WREG32(DCE8_DCCG_AUDIO_DTO1_MODULE, clock); |
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314 | } else { |
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315 | WREG32(DCCG_AUDIO_DTO1_PHASE, 24000); |
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316 | WREG32(DCCG_AUDIO_DTO1_MODULE, clock); |
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317 | } |
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5078 | serge | 318 | }>>>> |