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1123 | serge | 1 | /* |
2 | * Copyright 2007-8 Advanced Micro Devices, Inc. |
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3 | * Copyright 2008 Red Hat Inc. |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be included in |
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13 | * all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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21 | * OTHER DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: Dave Airlie |
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24 | * Alex Deucher |
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25 | */ |
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1179 | serge | 26 | #include |
27 | #include |
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28 | #include |
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1123 | serge | 29 | #include "radeon_fixed.h" |
30 | #include "radeon.h" |
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31 | #include "atom.h" |
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32 | #include "atom-bits.h" |
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33 | |||
1179 | serge | 34 | /* evil but including atombios.h is much worse */ |
35 | bool radeon_atom_get_tv_timings(struct radeon_device *rdev, int index, |
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36 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION *crtc_timing, |
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37 | int32_t *pixel_clock); |
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38 | static void atombios_overscan_setup(struct drm_crtc *crtc, |
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39 | struct drm_display_mode *mode, |
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40 | struct drm_display_mode *adjusted_mode) |
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41 | { |
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42 | struct drm_device *dev = crtc->dev; |
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43 | struct radeon_device *rdev = dev->dev_private; |
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44 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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45 | SET_CRTC_OVERSCAN_PS_ALLOCATION args; |
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46 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_OverScan); |
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47 | int a1, a2; |
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48 | |||
49 | memset(&args, 0, sizeof(args)); |
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50 | |||
51 | args.usOverscanRight = 0; |
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52 | args.usOverscanLeft = 0; |
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53 | args.usOverscanBottom = 0; |
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54 | args.usOverscanTop = 0; |
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55 | args.ucCRTC = radeon_crtc->crtc_id; |
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56 | |||
57 | switch (radeon_crtc->rmx_type) { |
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58 | case RMX_CENTER: |
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59 | args.usOverscanTop = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; |
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60 | args.usOverscanBottom = (adjusted_mode->crtc_vdisplay - mode->crtc_vdisplay) / 2; |
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61 | args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; |
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62 | args.usOverscanRight = (adjusted_mode->crtc_hdisplay - mode->crtc_hdisplay) / 2; |
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63 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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64 | break; |
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65 | case RMX_ASPECT: |
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66 | a1 = mode->crtc_vdisplay * adjusted_mode->crtc_hdisplay; |
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67 | a2 = adjusted_mode->crtc_vdisplay * mode->crtc_hdisplay; |
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68 | |||
69 | if (a1 > a2) { |
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70 | args.usOverscanLeft = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; |
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71 | args.usOverscanRight = (adjusted_mode->crtc_hdisplay - (a2 / mode->crtc_vdisplay)) / 2; |
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72 | } else if (a2 > a1) { |
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73 | args.usOverscanLeft = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; |
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74 | args.usOverscanRight = (adjusted_mode->crtc_vdisplay - (a1 / mode->crtc_hdisplay)) / 2; |
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75 | } |
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76 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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77 | break; |
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78 | case RMX_FULL: |
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79 | default: |
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80 | args.usOverscanRight = 0; |
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81 | args.usOverscanLeft = 0; |
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82 | args.usOverscanBottom = 0; |
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83 | args.usOverscanTop = 0; |
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84 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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85 | break; |
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86 | } |
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87 | } |
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88 | |||
89 | static void atombios_scaler_setup(struct drm_crtc *crtc) |
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90 | { |
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91 | struct drm_device *dev = crtc->dev; |
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92 | struct radeon_device *rdev = dev->dev_private; |
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93 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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94 | ENABLE_SCALER_PS_ALLOCATION args; |
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95 | int index = GetIndexIntoMasterTable(COMMAND, EnableScaler); |
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96 | |||
97 | /* fixme - fill in enc_priv for atom dac */ |
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98 | enum radeon_tv_std tv_std = TV_STD_NTSC; |
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99 | bool is_tv = false, is_cv = false; |
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100 | struct drm_encoder *encoder; |
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101 | |||
102 | if (!ASIC_IS_AVIVO(rdev) && radeon_crtc->crtc_id) |
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103 | return; |
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104 | |||
105 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
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106 | /* find tv std */ |
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107 | if (encoder->crtc == crtc) { |
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108 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
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109 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
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110 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
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111 | tv_std = tv_dac->tv_std; |
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112 | is_tv = true; |
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113 | } |
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114 | } |
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115 | } |
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116 | |||
117 | memset(&args, 0, sizeof(args)); |
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118 | |||
119 | args.ucScaler = radeon_crtc->crtc_id; |
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120 | |||
121 | if (is_tv) { |
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122 | switch (tv_std) { |
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123 | case TV_STD_NTSC: |
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124 | default: |
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125 | args.ucTVStandard = ATOM_TV_NTSC; |
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126 | break; |
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127 | case TV_STD_PAL: |
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128 | args.ucTVStandard = ATOM_TV_PAL; |
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129 | break; |
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130 | case TV_STD_PAL_M: |
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131 | args.ucTVStandard = ATOM_TV_PALM; |
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132 | break; |
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133 | case TV_STD_PAL_60: |
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134 | args.ucTVStandard = ATOM_TV_PAL60; |
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135 | break; |
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136 | case TV_STD_NTSC_J: |
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137 | args.ucTVStandard = ATOM_TV_NTSCJ; |
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138 | break; |
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139 | case TV_STD_SCART_PAL: |
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140 | args.ucTVStandard = ATOM_TV_PAL; /* ??? */ |
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141 | break; |
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142 | case TV_STD_SECAM: |
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143 | args.ucTVStandard = ATOM_TV_SECAM; |
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144 | break; |
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145 | case TV_STD_PAL_CN: |
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146 | args.ucTVStandard = ATOM_TV_PALCN; |
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147 | break; |
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148 | } |
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149 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
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150 | } else if (is_cv) { |
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151 | args.ucTVStandard = ATOM_TV_CV; |
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152 | args.ucEnable = SCALER_ENABLE_MULTITAP_MODE; |
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153 | } else { |
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154 | switch (radeon_crtc->rmx_type) { |
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155 | case RMX_FULL: |
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156 | args.ucEnable = ATOM_SCALER_EXPANSION; |
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157 | break; |
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158 | case RMX_CENTER: |
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159 | args.ucEnable = ATOM_SCALER_CENTER; |
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160 | break; |
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161 | case RMX_ASPECT: |
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162 | args.ucEnable = ATOM_SCALER_EXPANSION; |
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163 | break; |
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164 | default: |
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165 | if (ASIC_IS_AVIVO(rdev)) |
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166 | args.ucEnable = ATOM_SCALER_DISABLE; |
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167 | else |
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168 | args.ucEnable = ATOM_SCALER_CENTER; |
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169 | break; |
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170 | } |
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171 | } |
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172 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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173 | if ((is_tv || is_cv) |
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174 | && rdev->family >= CHIP_RV515 && rdev->family <= CHIP_R580) { |
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175 | atom_rv515_force_tv_scaler(rdev, radeon_crtc); |
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176 | } |
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177 | } |
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178 | |||
1123 | serge | 179 | static void atombios_lock_crtc(struct drm_crtc *crtc, int lock) |
180 | { |
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181 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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182 | struct drm_device *dev = crtc->dev; |
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183 | struct radeon_device *rdev = dev->dev_private; |
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184 | int index = |
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185 | GetIndexIntoMasterTable(COMMAND, UpdateCRTC_DoubleBufferRegisters); |
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186 | ENABLE_CRTC_PS_ALLOCATION args; |
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187 | |||
188 | memset(&args, 0, sizeof(args)); |
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189 | |||
190 | args.ucCRTC = radeon_crtc->crtc_id; |
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191 | args.ucEnable = lock; |
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192 | |||
193 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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194 | } |
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195 | |||
196 | static void atombios_enable_crtc(struct drm_crtc *crtc, int state) |
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197 | { |
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198 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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199 | struct drm_device *dev = crtc->dev; |
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200 | struct radeon_device *rdev = dev->dev_private; |
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201 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTC); |
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202 | ENABLE_CRTC_PS_ALLOCATION args; |
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203 | |||
204 | memset(&args, 0, sizeof(args)); |
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205 | |||
206 | args.ucCRTC = radeon_crtc->crtc_id; |
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207 | args.ucEnable = state; |
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208 | |||
209 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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210 | } |
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211 | |||
212 | static void atombios_enable_crtc_memreq(struct drm_crtc *crtc, int state) |
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213 | { |
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214 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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215 | struct drm_device *dev = crtc->dev; |
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216 | struct radeon_device *rdev = dev->dev_private; |
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217 | int index = GetIndexIntoMasterTable(COMMAND, EnableCRTCMemReq); |
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218 | ENABLE_CRTC_PS_ALLOCATION args; |
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219 | |||
220 | memset(&args, 0, sizeof(args)); |
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221 | |||
222 | args.ucCRTC = radeon_crtc->crtc_id; |
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223 | args.ucEnable = state; |
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224 | |||
225 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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226 | } |
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227 | |||
228 | static void atombios_blank_crtc(struct drm_crtc *crtc, int state) |
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229 | { |
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230 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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231 | struct drm_device *dev = crtc->dev; |
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232 | struct radeon_device *rdev = dev->dev_private; |
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233 | int index = GetIndexIntoMasterTable(COMMAND, BlankCRTC); |
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234 | BLANK_CRTC_PS_ALLOCATION args; |
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235 | |||
236 | memset(&args, 0, sizeof(args)); |
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237 | |||
238 | args.ucCRTC = radeon_crtc->crtc_id; |
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239 | args.ucBlanking = state; |
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240 | |||
241 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
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242 | } |
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243 | |||
244 | void atombios_crtc_dpms(struct drm_crtc *crtc, int mode) |
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245 | { |
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246 | struct drm_device *dev = crtc->dev; |
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247 | struct radeon_device *rdev = dev->dev_private; |
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248 | |||
249 | switch (mode) { |
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250 | case DRM_MODE_DPMS_ON: |
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251 | if (ASIC_IS_DCE3(rdev)) |
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252 | atombios_enable_crtc_memreq(crtc, 1); |
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253 | atombios_enable_crtc(crtc, 1); |
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254 | atombios_blank_crtc(crtc, 0); |
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255 | break; |
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256 | case DRM_MODE_DPMS_STANDBY: |
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257 | case DRM_MODE_DPMS_SUSPEND: |
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258 | case DRM_MODE_DPMS_OFF: |
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259 | atombios_blank_crtc(crtc, 1); |
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260 | atombios_enable_crtc(crtc, 0); |
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261 | if (ASIC_IS_DCE3(rdev)) |
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262 | atombios_enable_crtc_memreq(crtc, 0); |
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263 | break; |
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264 | } |
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265 | |||
266 | if (mode != DRM_MODE_DPMS_OFF) { |
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267 | radeon_crtc_load_lut(crtc); |
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268 | } |
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269 | } |
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270 | |||
271 | static void |
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272 | atombios_set_crtc_dtd_timing(struct drm_crtc *crtc, |
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273 | SET_CRTC_USING_DTD_TIMING_PARAMETERS * crtc_param) |
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274 | { |
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275 | struct drm_device *dev = crtc->dev; |
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276 | struct radeon_device *rdev = dev->dev_private; |
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277 | SET_CRTC_USING_DTD_TIMING_PARAMETERS conv_param; |
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278 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_UsingDTDTiming); |
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279 | |||
280 | conv_param.usH_Size = cpu_to_le16(crtc_param->usH_Size); |
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281 | conv_param.usH_Blanking_Time = |
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282 | cpu_to_le16(crtc_param->usH_Blanking_Time); |
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283 | conv_param.usV_Size = cpu_to_le16(crtc_param->usV_Size); |
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284 | conv_param.usV_Blanking_Time = |
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285 | cpu_to_le16(crtc_param->usV_Blanking_Time); |
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286 | conv_param.usH_SyncOffset = cpu_to_le16(crtc_param->usH_SyncOffset); |
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287 | conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth); |
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288 | conv_param.usV_SyncOffset = cpu_to_le16(crtc_param->usV_SyncOffset); |
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289 | conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth); |
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290 | conv_param.susModeMiscInfo.usAccess = |
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291 | cpu_to_le16(crtc_param->susModeMiscInfo.usAccess); |
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292 | conv_param.ucCRTC = crtc_param->ucCRTC; |
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293 | |||
294 | printk("executing set crtc dtd timing\n"); |
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295 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param); |
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296 | } |
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297 | |||
298 | void atombios_crtc_set_timing(struct drm_crtc *crtc, |
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299 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION * |
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300 | crtc_param) |
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301 | { |
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302 | struct drm_device *dev = crtc->dev; |
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303 | struct radeon_device *rdev = dev->dev_private; |
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304 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION conv_param; |
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305 | int index = GetIndexIntoMasterTable(COMMAND, SetCRTC_Timing); |
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306 | |||
307 | conv_param.usH_Total = cpu_to_le16(crtc_param->usH_Total); |
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308 | conv_param.usH_Disp = cpu_to_le16(crtc_param->usH_Disp); |
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309 | conv_param.usH_SyncStart = cpu_to_le16(crtc_param->usH_SyncStart); |
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310 | conv_param.usH_SyncWidth = cpu_to_le16(crtc_param->usH_SyncWidth); |
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311 | conv_param.usV_Total = cpu_to_le16(crtc_param->usV_Total); |
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312 | conv_param.usV_Disp = cpu_to_le16(crtc_param->usV_Disp); |
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313 | conv_param.usV_SyncStart = cpu_to_le16(crtc_param->usV_SyncStart); |
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314 | conv_param.usV_SyncWidth = cpu_to_le16(crtc_param->usV_SyncWidth); |
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315 | conv_param.susModeMiscInfo.usAccess = |
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316 | cpu_to_le16(crtc_param->susModeMiscInfo.usAccess); |
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317 | conv_param.ucCRTC = crtc_param->ucCRTC; |
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318 | conv_param.ucOverscanRight = crtc_param->ucOverscanRight; |
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319 | conv_param.ucOverscanLeft = crtc_param->ucOverscanLeft; |
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320 | conv_param.ucOverscanBottom = crtc_param->ucOverscanBottom; |
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321 | conv_param.ucOverscanTop = crtc_param->ucOverscanTop; |
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322 | conv_param.ucReserved = crtc_param->ucReserved; |
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323 | |||
324 | printk("executing set crtc timing\n"); |
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325 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&conv_param); |
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326 | } |
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327 | |||
328 | void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode *mode) |
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329 | { |
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330 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
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331 | struct drm_device *dev = crtc->dev; |
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332 | struct radeon_device *rdev = dev->dev_private; |
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333 | struct drm_encoder *encoder = NULL; |
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334 | struct radeon_encoder *radeon_encoder = NULL; |
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335 | uint8_t frev, crev; |
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336 | int index = GetIndexIntoMasterTable(COMMAND, SetPixelClock); |
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337 | SET_PIXEL_CLOCK_PS_ALLOCATION args; |
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338 | PIXEL_CLOCK_PARAMETERS *spc1_ptr; |
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339 | PIXEL_CLOCK_PARAMETERS_V2 *spc2_ptr; |
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340 | PIXEL_CLOCK_PARAMETERS_V3 *spc3_ptr; |
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341 | uint32_t sclock = mode->clock; |
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342 | uint32_t ref_div = 0, fb_div = 0, frac_fb_div = 0, post_div = 0; |
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343 | struct radeon_pll *pll; |
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344 | int pll_flags = 0; |
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345 | |||
346 | memset(&args, 0, sizeof(args)); |
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347 | |||
348 | if (ASIC_IS_AVIVO(rdev)) { |
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349 | uint32_t ss_cntl; |
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350 | |||
1179 | serge | 351 | if ((rdev->family == CHIP_RS600) || |
352 | (rdev->family == CHIP_RS690) || |
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353 | (rdev->family == CHIP_RS740)) |
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354 | pll_flags |= (RADEON_PLL_USE_FRAC_FB_DIV | |
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355 | RADEON_PLL_PREFER_CLOSEST_LOWER); |
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356 | |||
1123 | serge | 357 | if (ASIC_IS_DCE32(rdev) && mode->clock > 200000) /* range limits??? */ |
358 | pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
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359 | else |
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360 | pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
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361 | |||
362 | /* disable spread spectrum clocking for now -- thanks Hedy Lamarr */ |
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363 | if (radeon_crtc->crtc_id == 0) { |
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364 | ss_cntl = RREG32(AVIVO_P1PLL_INT_SS_CNTL); |
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365 | WREG32(AVIVO_P1PLL_INT_SS_CNTL, ss_cntl & ~1); |
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366 | } else { |
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367 | ss_cntl = RREG32(AVIVO_P2PLL_INT_SS_CNTL); |
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368 | WREG32(AVIVO_P2PLL_INT_SS_CNTL, ss_cntl & ~1); |
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369 | } |
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370 | } else { |
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371 | pll_flags |= RADEON_PLL_LEGACY; |
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372 | |||
373 | if (mode->clock > 200000) /* range limits??? */ |
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374 | pll_flags |= RADEON_PLL_PREFER_HIGH_FB_DIV; |
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375 | else |
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376 | pll_flags |= RADEON_PLL_PREFER_LOW_REF_DIV; |
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377 | |||
378 | } |
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379 | |||
380 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
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381 | if (encoder->crtc == crtc) { |
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382 | if (!ASIC_IS_AVIVO(rdev)) { |
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383 | if (encoder->encoder_type != |
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384 | DRM_MODE_ENCODER_DAC) |
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385 | pll_flags |= RADEON_PLL_NO_ODD_POST_DIV; |
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386 | if (!ASIC_IS_AVIVO(rdev) |
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387 | && (encoder->encoder_type == |
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388 | DRM_MODE_ENCODER_LVDS)) |
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389 | pll_flags |= RADEON_PLL_USE_REF_DIV; |
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390 | } |
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391 | radeon_encoder = to_radeon_encoder(encoder); |
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1179 | serge | 392 | break; |
1123 | serge | 393 | } |
394 | } |
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395 | |||
396 | if (radeon_crtc->crtc_id == 0) |
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397 | pll = &rdev->clock.p1pll; |
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398 | else |
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399 | pll = &rdev->clock.p2pll; |
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400 | |||
401 | radeon_compute_pll(pll, mode->clock, &sclock, &fb_div, &frac_fb_div, |
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402 | &ref_div, &post_div, pll_flags); |
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403 | |||
404 | atom_parse_cmd_header(rdev->mode_info.atom_context, index, &frev, |
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405 | &crev); |
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406 | |||
407 | switch (frev) { |
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408 | case 1: |
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409 | switch (crev) { |
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410 | case 1: |
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411 | spc1_ptr = (PIXEL_CLOCK_PARAMETERS *) & args.sPCLKInput; |
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412 | spc1_ptr->usPixelClock = cpu_to_le16(sclock); |
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413 | spc1_ptr->usRefDiv = cpu_to_le16(ref_div); |
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414 | spc1_ptr->usFbDiv = cpu_to_le16(fb_div); |
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415 | spc1_ptr->ucFracFbDiv = frac_fb_div; |
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416 | spc1_ptr->ucPostDiv = post_div; |
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417 | spc1_ptr->ucPpll = |
||
418 | radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; |
||
419 | spc1_ptr->ucCRTC = radeon_crtc->crtc_id; |
||
420 | spc1_ptr->ucRefDivSrc = 1; |
||
421 | break; |
||
422 | case 2: |
||
423 | spc2_ptr = |
||
424 | (PIXEL_CLOCK_PARAMETERS_V2 *) & args.sPCLKInput; |
||
425 | spc2_ptr->usPixelClock = cpu_to_le16(sclock); |
||
426 | spc2_ptr->usRefDiv = cpu_to_le16(ref_div); |
||
427 | spc2_ptr->usFbDiv = cpu_to_le16(fb_div); |
||
428 | spc2_ptr->ucFracFbDiv = frac_fb_div; |
||
429 | spc2_ptr->ucPostDiv = post_div; |
||
430 | spc2_ptr->ucPpll = |
||
431 | radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; |
||
432 | spc2_ptr->ucCRTC = radeon_crtc->crtc_id; |
||
433 | spc2_ptr->ucRefDivSrc = 1; |
||
434 | break; |
||
435 | case 3: |
||
436 | if (!encoder) |
||
437 | return; |
||
438 | spc3_ptr = |
||
439 | (PIXEL_CLOCK_PARAMETERS_V3 *) & args.sPCLKInput; |
||
440 | spc3_ptr->usPixelClock = cpu_to_le16(sclock); |
||
441 | spc3_ptr->usRefDiv = cpu_to_le16(ref_div); |
||
442 | spc3_ptr->usFbDiv = cpu_to_le16(fb_div); |
||
443 | spc3_ptr->ucFracFbDiv = frac_fb_div; |
||
444 | spc3_ptr->ucPostDiv = post_div; |
||
445 | spc3_ptr->ucPpll = |
||
446 | radeon_crtc->crtc_id ? ATOM_PPLL2 : ATOM_PPLL1; |
||
447 | spc3_ptr->ucMiscInfo = (radeon_crtc->crtc_id << 2); |
||
448 | spc3_ptr->ucTransmitterId = radeon_encoder->encoder_id; |
||
449 | spc3_ptr->ucEncoderMode = |
||
450 | atombios_get_encoder_mode(encoder); |
||
451 | break; |
||
452 | default: |
||
453 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
||
454 | return; |
||
455 | } |
||
456 | break; |
||
457 | default: |
||
458 | DRM_ERROR("Unknown table version %d %d\n", frev, crev); |
||
459 | return; |
||
460 | } |
||
461 | |||
462 | printk("executing set pll\n"); |
||
463 | atom_execute_table(rdev->mode_info.atom_context, index, (uint32_t *)&args); |
||
464 | } |
||
465 | |||
466 | int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y, |
||
467 | struct drm_framebuffer *old_fb) |
||
468 | { |
||
469 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
470 | struct drm_device *dev = crtc->dev; |
||
471 | struct radeon_device *rdev = dev->dev_private; |
||
472 | struct radeon_framebuffer *radeon_fb; |
||
473 | struct drm_gem_object *obj; |
||
474 | struct drm_radeon_gem_object *obj_priv; |
||
475 | uint64_t fb_location; |
||
1179 | serge | 476 | uint32_t fb_format, fb_pitch_pixels, tiling_flags; |
1123 | serge | 477 | |
478 | if (!crtc->fb) |
||
479 | return -EINVAL; |
||
480 | |||
1179 | serge | 481 | dbgprintf("x = %d y = %d width = %d height = %d\n", |
482 | x, y, crtc->fb->width, crtc->fb->height); |
||
483 | dbgprintf("hdisplay = %d\n", crtc->mode.hdisplay); |
||
484 | |||
1123 | serge | 485 | radeon_fb = to_radeon_framebuffer(crtc->fb); |
486 | |||
487 | obj = radeon_fb->obj; |
||
488 | obj_priv = obj->driver_private; |
||
489 | |||
1179 | serge | 490 | // if (radeon_gem_object_pin(obj, RADEON_GEM_DOMAIN_VRAM, &fb_location)) { |
491 | // return -EINVAL; |
||
492 | // } |
||
1123 | serge | 493 | |
1128 | serge | 494 | fb_location = 0; //rdev->mc.vram_location; |
1126 | serge | 495 | |
496 | dbgprintf("fb_location %x\n", fb_location); |
||
1179 | serge | 497 | dbgprintf("bpp %d\n", crtc->fb->bits_per_pixel); |
1126 | serge | 498 | |
1123 | serge | 499 | switch (crtc->fb->bits_per_pixel) { |
1179 | serge | 500 | case 8: |
501 | fb_format = |
||
502 | AVIVO_D1GRPH_CONTROL_DEPTH_8BPP | |
||
503 | AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; |
||
504 | break; |
||
1123 | serge | 505 | case 15: |
506 | fb_format = |
||
507 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
||
508 | AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; |
||
509 | break; |
||
510 | case 16: |
||
511 | fb_format = |
||
512 | AVIVO_D1GRPH_CONTROL_DEPTH_16BPP | |
||
513 | AVIVO_D1GRPH_CONTROL_16BPP_RGB565; |
||
514 | break; |
||
515 | case 24: |
||
516 | case 32: |
||
517 | fb_format = |
||
518 | AVIVO_D1GRPH_CONTROL_DEPTH_32BPP | |
||
519 | AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; |
||
520 | break; |
||
521 | default: |
||
522 | DRM_ERROR("Unsupported screen depth %d\n", |
||
523 | crtc->fb->bits_per_pixel); |
||
524 | return -EINVAL; |
||
525 | } |
||
526 | |||
1179 | serge | 527 | // radeon_object_get_tiling_flags(obj->driver_private, |
528 | // &tiling_flags, NULL); |
||
529 | // if (tiling_flags & RADEON_TILING_MACRO) |
||
530 | // fb_format |= AVIVO_D1GRPH_MACRO_ADDRESS_MODE; |
||
531 | |||
532 | // if (tiling_flags & RADEON_TILING_MICRO) |
||
533 | // fb_format |= AVIVO_D1GRPH_TILED; |
||
534 | |||
1123 | serge | 535 | if (radeon_crtc->crtc_id == 0) |
536 | WREG32(AVIVO_D1VGA_CONTROL, 0); |
||
537 | else |
||
538 | WREG32(AVIVO_D2VGA_CONTROL, 0); |
||
539 | WREG32(AVIVO_D1GRPH_PRIMARY_SURFACE_ADDRESS + radeon_crtc->crtc_offset, |
||
540 | (u32) fb_location); |
||
541 | WREG32(AVIVO_D1GRPH_SECONDARY_SURFACE_ADDRESS + |
||
542 | radeon_crtc->crtc_offset, (u32) fb_location); |
||
543 | WREG32(AVIVO_D1GRPH_CONTROL + radeon_crtc->crtc_offset, fb_format); |
||
544 | |||
545 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_X + radeon_crtc->crtc_offset, 0); |
||
546 | WREG32(AVIVO_D1GRPH_SURFACE_OFFSET_Y + radeon_crtc->crtc_offset, 0); |
||
547 | WREG32(AVIVO_D1GRPH_X_START + radeon_crtc->crtc_offset, 0); |
||
548 | WREG32(AVIVO_D1GRPH_Y_START + radeon_crtc->crtc_offset, 0); |
||
549 | WREG32(AVIVO_D1GRPH_X_END + radeon_crtc->crtc_offset, crtc->fb->width); |
||
550 | WREG32(AVIVO_D1GRPH_Y_END + radeon_crtc->crtc_offset, crtc->fb->height); |
||
551 | |||
552 | fb_pitch_pixels = crtc->fb->pitch / (crtc->fb->bits_per_pixel / 8); |
||
553 | WREG32(AVIVO_D1GRPH_PITCH + radeon_crtc->crtc_offset, fb_pitch_pixels); |
||
554 | WREG32(AVIVO_D1GRPH_ENABLE + radeon_crtc->crtc_offset, 1); |
||
555 | |||
556 | WREG32(AVIVO_D1MODE_DESKTOP_HEIGHT + radeon_crtc->crtc_offset, |
||
557 | crtc->mode.vdisplay); |
||
558 | x &= ~3; |
||
559 | y &= ~1; |
||
560 | WREG32(AVIVO_D1MODE_VIEWPORT_START + radeon_crtc->crtc_offset, |
||
561 | (x << 16) | y); |
||
562 | WREG32(AVIVO_D1MODE_VIEWPORT_SIZE + radeon_crtc->crtc_offset, |
||
563 | (crtc->mode.hdisplay << 16) | crtc->mode.vdisplay); |
||
564 | |||
565 | if (crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) |
||
566 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, |
||
567 | AVIVO_D1MODE_INTERLEAVE_EN); |
||
568 | else |
||
569 | WREG32(AVIVO_D1MODE_DATA_FORMAT + radeon_crtc->crtc_offset, 0); |
||
570 | |||
571 | if (old_fb && old_fb != crtc->fb) { |
||
1179 | serge | 572 | // radeon_fb = to_radeon_framebuffer(old_fb); |
1123 | serge | 573 | // radeon_gem_object_unpin(radeon_fb->obj); |
574 | } |
||
575 | return 0; |
||
576 | } |
||
577 | |||
578 | int atombios_crtc_mode_set(struct drm_crtc *crtc, |
||
579 | struct drm_display_mode *mode, |
||
580 | struct drm_display_mode *adjusted_mode, |
||
581 | int x, int y, struct drm_framebuffer *old_fb) |
||
582 | { |
||
583 | struct radeon_crtc *radeon_crtc = to_radeon_crtc(crtc); |
||
584 | struct drm_device *dev = crtc->dev; |
||
585 | struct radeon_device *rdev = dev->dev_private; |
||
586 | struct drm_encoder *encoder; |
||
587 | SET_CRTC_TIMING_PARAMETERS_PS_ALLOCATION crtc_timing; |
||
1179 | serge | 588 | int need_tv_timings = 0; |
589 | bool ret; |
||
1123 | serge | 590 | |
591 | /* TODO color tiling */ |
||
592 | memset(&crtc_timing, 0, sizeof(crtc_timing)); |
||
593 | |||
594 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) { |
||
1179 | serge | 595 | /* find tv std */ |
596 | if (encoder->crtc == crtc) { |
||
597 | struct radeon_encoder *radeon_encoder = to_radeon_encoder(encoder); |
||
1123 | serge | 598 | |
1179 | serge | 599 | if (radeon_encoder->active_device & ATOM_DEVICE_TV_SUPPORT) { |
600 | struct radeon_encoder_atom_dac *tv_dac = radeon_encoder->enc_priv; |
||
601 | if (tv_dac) { |
||
602 | if (tv_dac->tv_std == TV_STD_NTSC || |
||
603 | tv_dac->tv_std == TV_STD_NTSC_J || |
||
604 | tv_dac->tv_std == TV_STD_PAL_M) |
||
605 | need_tv_timings = 1; |
||
606 | else |
||
607 | need_tv_timings = 2; |
||
608 | break; |
||
609 | } |
||
610 | } |
||
611 | } |
||
1123 | serge | 612 | } |
613 | |||
614 | crtc_timing.ucCRTC = radeon_crtc->crtc_id; |
||
1179 | serge | 615 | if (need_tv_timings) { |
616 | ret = radeon_atom_get_tv_timings(rdev, need_tv_timings - 1, |
||
617 | &crtc_timing, &adjusted_mode->clock); |
||
618 | if (ret == false) |
||
619 | need_tv_timings = 0; |
||
620 | } |
||
621 | |||
622 | if (!need_tv_timings) { |
||
1123 | serge | 623 | crtc_timing.usH_Total = adjusted_mode->crtc_htotal; |
624 | crtc_timing.usH_Disp = adjusted_mode->crtc_hdisplay; |
||
625 | crtc_timing.usH_SyncStart = adjusted_mode->crtc_hsync_start; |
||
626 | crtc_timing.usH_SyncWidth = |
||
627 | adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; |
||
628 | |||
629 | crtc_timing.usV_Total = adjusted_mode->crtc_vtotal; |
||
630 | crtc_timing.usV_Disp = adjusted_mode->crtc_vdisplay; |
||
631 | crtc_timing.usV_SyncStart = adjusted_mode->crtc_vsync_start; |
||
632 | crtc_timing.usV_SyncWidth = |
||
633 | adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; |
||
634 | |||
635 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
||
636 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_VSYNC_POLARITY; |
||
637 | |||
638 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
||
639 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_HSYNC_POLARITY; |
||
640 | |||
641 | if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC) |
||
642 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_COMPOSITESYNC; |
||
643 | |||
644 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
||
645 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_INTERLACE; |
||
646 | |||
647 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
||
648 | crtc_timing.susModeMiscInfo.usAccess |= ATOM_DOUBLE_CLOCK_MODE; |
||
1179 | serge | 649 | } |
1123 | serge | 650 | |
651 | atombios_crtc_set_pll(crtc, adjusted_mode); |
||
652 | atombios_crtc_set_timing(crtc, &crtc_timing); |
||
653 | |||
654 | if (ASIC_IS_AVIVO(rdev)) |
||
655 | atombios_crtc_set_base(crtc, x, y, old_fb); |
||
656 | else { |
||
657 | if (radeon_crtc->crtc_id == 0) { |
||
658 | SET_CRTC_USING_DTD_TIMING_PARAMETERS crtc_dtd_timing; |
||
659 | memset(&crtc_dtd_timing, 0, sizeof(crtc_dtd_timing)); |
||
660 | |||
661 | /* setup FP shadow regs on R4xx */ |
||
662 | crtc_dtd_timing.ucCRTC = radeon_crtc->crtc_id; |
||
663 | crtc_dtd_timing.usH_Size = adjusted_mode->crtc_hdisplay; |
||
664 | crtc_dtd_timing.usV_Size = adjusted_mode->crtc_vdisplay; |
||
665 | crtc_dtd_timing.usH_Blanking_Time = |
||
666 | adjusted_mode->crtc_hblank_end - |
||
667 | adjusted_mode->crtc_hdisplay; |
||
668 | crtc_dtd_timing.usV_Blanking_Time = |
||
669 | adjusted_mode->crtc_vblank_end - |
||
670 | adjusted_mode->crtc_vdisplay; |
||
671 | crtc_dtd_timing.usH_SyncOffset = |
||
672 | adjusted_mode->crtc_hsync_start - |
||
673 | adjusted_mode->crtc_hdisplay; |
||
674 | crtc_dtd_timing.usV_SyncOffset = |
||
675 | adjusted_mode->crtc_vsync_start - |
||
676 | adjusted_mode->crtc_vdisplay; |
||
677 | crtc_dtd_timing.usH_SyncWidth = |
||
678 | adjusted_mode->crtc_hsync_end - |
||
679 | adjusted_mode->crtc_hsync_start; |
||
680 | crtc_dtd_timing.usV_SyncWidth = |
||
681 | adjusted_mode->crtc_vsync_end - |
||
682 | adjusted_mode->crtc_vsync_start; |
||
683 | /* crtc_dtd_timing.ucH_Border = adjusted_mode->crtc_hborder; */ |
||
684 | /* crtc_dtd_timing.ucV_Border = adjusted_mode->crtc_vborder; */ |
||
685 | |||
686 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
||
687 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
||
688 | ATOM_VSYNC_POLARITY; |
||
689 | |||
690 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
||
691 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
||
692 | ATOM_HSYNC_POLARITY; |
||
693 | |||
694 | if (adjusted_mode->flags & DRM_MODE_FLAG_CSYNC) |
||
695 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
||
696 | ATOM_COMPOSITESYNC; |
||
697 | |||
698 | if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) |
||
699 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
||
700 | ATOM_INTERLACE; |
||
701 | |||
702 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) |
||
703 | crtc_dtd_timing.susModeMiscInfo.usAccess |= |
||
704 | ATOM_DOUBLE_CLOCK_MODE; |
||
705 | |||
706 | atombios_set_crtc_dtd_timing(crtc, &crtc_dtd_timing); |
||
707 | } |
||
708 | radeon_crtc_set_base(crtc, x, y, old_fb); |
||
709 | radeon_legacy_atom_set_surface(crtc); |
||
710 | } |
||
1179 | serge | 711 | atombios_overscan_setup(crtc, mode, adjusted_mode); |
712 | atombios_scaler_setup(crtc); |
||
713 | radeon_bandwidth_update(rdev); |
||
1123 | serge | 714 | return 0; |
715 | } |
||
716 | |||
717 | static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc, |
||
718 | struct drm_display_mode *mode, |
||
719 | struct drm_display_mode *adjusted_mode) |
||
720 | { |
||
1179 | serge | 721 | if (!radeon_crtc_scaling_mode_fixup(crtc, mode, adjusted_mode)) |
722 | return false; |
||
1123 | serge | 723 | return true; |
724 | } |
||
725 | |||
726 | static void atombios_crtc_prepare(struct drm_crtc *crtc) |
||
727 | { |
||
728 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_OFF); |
||
729 | atombios_lock_crtc(crtc, 1); |
||
730 | } |
||
731 | |||
732 | static void atombios_crtc_commit(struct drm_crtc *crtc) |
||
733 | { |
||
734 | atombios_crtc_dpms(crtc, DRM_MODE_DPMS_ON); |
||
735 | atombios_lock_crtc(crtc, 0); |
||
736 | } |
||
737 | |||
738 | static const struct drm_crtc_helper_funcs atombios_helper_funcs = { |
||
739 | .dpms = atombios_crtc_dpms, |
||
740 | .mode_fixup = atombios_crtc_mode_fixup, |
||
741 | .mode_set = atombios_crtc_mode_set, |
||
742 | .mode_set_base = atombios_crtc_set_base, |
||
743 | .prepare = atombios_crtc_prepare, |
||
744 | .commit = atombios_crtc_commit, |
||
745 | }; |
||
746 | |||
747 | void radeon_atombios_init_crtc(struct drm_device *dev, |
||
748 | struct radeon_crtc *radeon_crtc) |
||
749 | { |
||
750 | if (radeon_crtc->crtc_id == 1) |
||
751 | radeon_crtc->crtc_offset = |
||
752 | AVIVO_D2CRTC_H_TOTAL - AVIVO_D1CRTC_H_TOTAL; |
||
753 | drm_crtc_helper_add(&radeon_crtc->base, &atombios_helper_funcs); |
||
754 | }><>><>><>=> |