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Rev | Author | Line No. | Line |
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4560 | Serge | 1 | /* |
2 | * Copyright © 2013 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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21 | * DEALINGS IN THE SOFTWARE. |
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22 | * |
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23 | * Author: Jani Nikula |
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24 | */ |
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25 | |||
26 | #include |
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6084 | serge | 27 | #include |
4560 | Serge | 28 | #include |
29 | #include |
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30 | #include |
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6084 | serge | 31 | #include |
32 | #include |
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4560 | Serge | 33 | #include |
6084 | serge | 34 | #include |
4560 | Serge | 35 | #include "i915_drv.h" |
36 | #include "intel_drv.h" |
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37 | #include "intel_dsi.h" |
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38 | |||
6084 | serge | 39 | static const struct { |
40 | u16 panel_id; |
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41 | struct drm_panel * (*init)(struct intel_dsi *intel_dsi, u16 panel_id); |
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42 | } intel_dsi_drivers[] = { |
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5060 | serge | 43 | { |
44 | .panel_id = MIPI_DSI_GENERIC_PANEL_ID, |
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6084 | serge | 45 | .init = vbt_panel_init, |
5060 | serge | 46 | }, |
4560 | Serge | 47 | }; |
48 | |||
6084 | serge | 49 | static void wait_for_dsi_fifo_empty(struct intel_dsi *intel_dsi, enum port port) |
50 | { |
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51 | struct drm_encoder *encoder = &intel_dsi->base.base; |
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52 | struct drm_device *dev = encoder->dev; |
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53 | struct drm_i915_private *dev_priv = dev->dev_private; |
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54 | u32 mask; |
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55 | |||
56 | mask = LP_CTRL_FIFO_EMPTY | HS_CTRL_FIFO_EMPTY | |
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57 | LP_DATA_FIFO_EMPTY | HS_DATA_FIFO_EMPTY; |
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58 | |||
59 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & mask) == mask, 100)) |
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60 | DRM_ERROR("DPI FIFOs are not empty\n"); |
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61 | } |
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62 | |||
6937 | serge | 63 | static void write_data(struct drm_i915_private *dev_priv, |
64 | i915_reg_t reg, |
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6084 | serge | 65 | const u8 *data, u32 len) |
66 | { |
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67 | u32 i, j; |
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68 | |||
69 | for (i = 0; i < len; i += 4) { |
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70 | u32 val = 0; |
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71 | |||
72 | for (j = 0; j < min_t(u32, len - i, 4); j++) |
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73 | val |= *data++ << 8 * j; |
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74 | |||
75 | I915_WRITE(reg, val); |
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76 | } |
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77 | } |
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78 | |||
6937 | serge | 79 | static void read_data(struct drm_i915_private *dev_priv, |
80 | i915_reg_t reg, |
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6084 | serge | 81 | u8 *data, u32 len) |
82 | { |
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83 | u32 i, j; |
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84 | |||
85 | for (i = 0; i < len; i += 4) { |
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86 | u32 val = I915_READ(reg); |
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87 | |||
88 | for (j = 0; j < min_t(u32, len - i, 4); j++) |
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89 | *data++ = val >> 8 * j; |
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90 | } |
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91 | } |
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92 | |||
93 | static ssize_t intel_dsi_host_transfer(struct mipi_dsi_host *host, |
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94 | const struct mipi_dsi_msg *msg) |
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95 | { |
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96 | struct intel_dsi_host *intel_dsi_host = to_intel_dsi_host(host); |
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97 | struct drm_device *dev = intel_dsi_host->intel_dsi->base.base.dev; |
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98 | struct drm_i915_private *dev_priv = dev->dev_private; |
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99 | enum port port = intel_dsi_host->port; |
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100 | struct mipi_dsi_packet packet; |
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101 | ssize_t ret; |
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102 | const u8 *header, *data; |
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6937 | serge | 103 | i915_reg_t data_reg, ctrl_reg; |
104 | u32 data_mask, ctrl_mask; |
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6084 | serge | 105 | |
106 | ret = mipi_dsi_create_packet(&packet, msg); |
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107 | if (ret < 0) |
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108 | return ret; |
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109 | |||
110 | header = packet.header; |
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111 | data = packet.payload; |
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112 | |||
113 | if (msg->flags & MIPI_DSI_MSG_USE_LPM) { |
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114 | data_reg = MIPI_LP_GEN_DATA(port); |
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115 | data_mask = LP_DATA_FIFO_FULL; |
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116 | ctrl_reg = MIPI_LP_GEN_CTRL(port); |
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117 | ctrl_mask = LP_CTRL_FIFO_FULL; |
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118 | } else { |
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119 | data_reg = MIPI_HS_GEN_DATA(port); |
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120 | data_mask = HS_DATA_FIFO_FULL; |
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121 | ctrl_reg = MIPI_HS_GEN_CTRL(port); |
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122 | ctrl_mask = HS_CTRL_FIFO_FULL; |
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123 | } |
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124 | |||
125 | /* note: this is never true for reads */ |
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126 | if (packet.payload_length) { |
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127 | |||
128 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & data_mask) == 0, 50)) |
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129 | DRM_ERROR("Timeout waiting for HS/LP DATA FIFO !full\n"); |
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130 | |||
131 | write_data(dev_priv, data_reg, packet.payload, |
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132 | packet.payload_length); |
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133 | } |
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134 | |||
135 | if (msg->rx_len) { |
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136 | I915_WRITE(MIPI_INTR_STAT(port), GEN_READ_DATA_AVAIL); |
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137 | } |
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138 | |||
139 | if (wait_for((I915_READ(MIPI_GEN_FIFO_STAT(port)) & ctrl_mask) == 0, 50)) { |
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140 | DRM_ERROR("Timeout waiting for HS/LP CTRL FIFO !full\n"); |
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141 | } |
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142 | |||
143 | I915_WRITE(ctrl_reg, header[2] << 16 | header[1] << 8 | header[0]); |
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144 | |||
145 | /* ->rx_len is set only for reads */ |
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146 | if (msg->rx_len) { |
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147 | data_mask = GEN_READ_DATA_AVAIL; |
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148 | if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & data_mask) == data_mask, 50)) |
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149 | DRM_ERROR("Timeout waiting for read data.\n"); |
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150 | |||
151 | read_data(dev_priv, data_reg, msg->rx_buf, msg->rx_len); |
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152 | } |
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153 | |||
154 | /* XXX: fix for reads and writes */ |
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155 | return 4 + packet.payload_length; |
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156 | } |
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157 | |||
158 | static int intel_dsi_host_attach(struct mipi_dsi_host *host, |
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159 | struct mipi_dsi_device *dsi) |
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160 | { |
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161 | return 0; |
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162 | } |
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163 | |||
164 | static int intel_dsi_host_detach(struct mipi_dsi_host *host, |
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165 | struct mipi_dsi_device *dsi) |
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166 | { |
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167 | return 0; |
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168 | } |
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169 | |||
170 | static const struct mipi_dsi_host_ops intel_dsi_host_ops = { |
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171 | .attach = intel_dsi_host_attach, |
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172 | .detach = intel_dsi_host_detach, |
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173 | .transfer = intel_dsi_host_transfer, |
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174 | }; |
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175 | |||
176 | static struct intel_dsi_host *intel_dsi_host_init(struct intel_dsi *intel_dsi, |
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177 | enum port port) |
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178 | { |
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179 | struct intel_dsi_host *host; |
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180 | struct mipi_dsi_device *device; |
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181 | |||
182 | host = kzalloc(sizeof(*host), GFP_KERNEL); |
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183 | if (!host) |
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184 | return NULL; |
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185 | |||
186 | host->base.ops = &intel_dsi_host_ops; |
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187 | host->intel_dsi = intel_dsi; |
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188 | host->port = port; |
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189 | |||
190 | /* |
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191 | * We should call mipi_dsi_host_register(&host->base) here, but we don't |
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192 | * have a host->dev, and we don't have OF stuff either. So just use the |
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193 | * dsi framework as a library and hope for the best. Create the dsi |
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194 | * devices by ourselves here too. Need to be careful though, because we |
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195 | * don't initialize any of the driver model devices here. |
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196 | */ |
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197 | device = kzalloc(sizeof(*device), GFP_KERNEL); |
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198 | if (!device) { |
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199 | kfree(host); |
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200 | return NULL; |
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201 | } |
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202 | |||
203 | device->host = &host->base; |
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204 | host->device = device; |
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205 | |||
206 | return host; |
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207 | } |
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208 | |||
209 | /* |
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210 | * send a video mode command |
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211 | * |
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212 | * XXX: commands with data in MIPI_DPI_DATA? |
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213 | */ |
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214 | static int dpi_send_cmd(struct intel_dsi *intel_dsi, u32 cmd, bool hs, |
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215 | enum port port) |
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216 | { |
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217 | struct drm_encoder *encoder = &intel_dsi->base.base; |
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218 | struct drm_device *dev = encoder->dev; |
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219 | struct drm_i915_private *dev_priv = dev->dev_private; |
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220 | u32 mask; |
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221 | |||
222 | /* XXX: pipe, hs */ |
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223 | if (hs) |
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224 | cmd &= ~DPI_LP_MODE; |
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225 | else |
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226 | cmd |= DPI_LP_MODE; |
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227 | |||
228 | /* clear bit */ |
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229 | I915_WRITE(MIPI_INTR_STAT(port), SPL_PKT_SENT_INTERRUPT); |
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230 | |||
231 | /* XXX: old code skips write if control unchanged */ |
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232 | if (cmd == I915_READ(MIPI_DPI_CONTROL(port))) |
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233 | DRM_ERROR("Same special packet %02x twice in a row.\n", cmd); |
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234 | |||
235 | I915_WRITE(MIPI_DPI_CONTROL(port), cmd); |
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236 | |||
237 | mask = SPL_PKT_SENT_INTERRUPT; |
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238 | if (wait_for((I915_READ(MIPI_INTR_STAT(port)) & mask) == mask, 100)) |
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239 | DRM_ERROR("Video mode command 0x%08x send failed.\n", cmd); |
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240 | |||
241 | return 0; |
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242 | } |
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243 | |||
4560 | Serge | 244 | static void band_gap_reset(struct drm_i915_private *dev_priv) |
245 | { |
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6084 | serge | 246 | mutex_lock(&dev_priv->sb_lock); |
4560 | Serge | 247 | |
248 | vlv_flisdsi_write(dev_priv, 0x08, 0x0001); |
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249 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0005); |
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250 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0025); |
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251 | udelay(150); |
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252 | vlv_flisdsi_write(dev_priv, 0x0F, 0x0000); |
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253 | vlv_flisdsi_write(dev_priv, 0x08, 0x0000); |
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254 | |||
6084 | serge | 255 | mutex_unlock(&dev_priv->sb_lock); |
4560 | Serge | 256 | } |
257 | |||
258 | static inline bool is_vid_mode(struct intel_dsi *intel_dsi) |
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259 | { |
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5060 | serge | 260 | return intel_dsi->operation_mode == INTEL_DSI_VIDEO_MODE; |
4560 | Serge | 261 | } |
262 | |||
263 | static inline bool is_cmd_mode(struct intel_dsi *intel_dsi) |
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264 | { |
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5060 | serge | 265 | return intel_dsi->operation_mode == INTEL_DSI_COMMAND_MODE; |
4560 | Serge | 266 | } |
267 | |||
268 | static bool intel_dsi_compute_config(struct intel_encoder *encoder, |
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6937 | serge | 269 | struct intel_crtc_state *pipe_config) |
4560 | Serge | 270 | { |
271 | struct intel_dsi *intel_dsi = container_of(encoder, struct intel_dsi, |
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272 | base); |
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273 | struct intel_connector *intel_connector = intel_dsi->attached_connector; |
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274 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
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6937 | serge | 275 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
4560 | Serge | 276 | |
277 | DRM_DEBUG_KMS("\n"); |
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278 | |||
6937 | serge | 279 | pipe_config->has_dsi_encoder = true; |
280 | |||
4560 | Serge | 281 | if (fixed_mode) |
282 | intel_fixed_panel_mode(fixed_mode, adjusted_mode); |
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283 | |||
5060 | serge | 284 | /* DSI uses short packets for sync events, so clear mode flags for DSI */ |
285 | adjusted_mode->flags = 0; |
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286 | |||
4560 | Serge | 287 | return true; |
288 | } |
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289 | |||
6084 | serge | 290 | static void bxt_dsi_device_ready(struct intel_encoder *encoder) |
4560 | Serge | 291 | { |
292 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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6084 | serge | 293 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
294 | enum port port; |
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4560 | Serge | 295 | u32 val; |
296 | |||
297 | DRM_DEBUG_KMS("\n"); |
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298 | |||
6084 | serge | 299 | /* Exit Low power state in 4 steps*/ |
300 | for_each_dsi_port(port, intel_dsi->ports) { |
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301 | |||
302 | /* 1. Enable MIPI PHY transparent latch */ |
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303 | val = I915_READ(BXT_MIPI_PORT_CTRL(port)); |
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304 | I915_WRITE(BXT_MIPI_PORT_CTRL(port), val | LP_OUTPUT_HOLD); |
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305 | usleep_range(2000, 2500); |
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306 | |||
307 | /* 2. Enter ULPS */ |
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308 | val = I915_READ(MIPI_DEVICE_READY(port)); |
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309 | val &= ~ULPS_STATE_MASK; |
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310 | val |= (ULPS_STATE_ENTER | DEVICE_READY); |
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311 | I915_WRITE(MIPI_DEVICE_READY(port), val); |
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312 | usleep_range(2, 3); |
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313 | |||
314 | /* 3. Exit ULPS */ |
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315 | val = I915_READ(MIPI_DEVICE_READY(port)); |
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316 | val &= ~ULPS_STATE_MASK; |
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317 | val |= (ULPS_STATE_EXIT | DEVICE_READY); |
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318 | I915_WRITE(MIPI_DEVICE_READY(port), val); |
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319 | usleep_range(1000, 1500); |
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320 | |||
321 | /* Clear ULPS and set device ready */ |
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322 | val = I915_READ(MIPI_DEVICE_READY(port)); |
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323 | val &= ~ULPS_STATE_MASK; |
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324 | val |= DEVICE_READY; |
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325 | I915_WRITE(MIPI_DEVICE_READY(port), val); |
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326 | } |
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327 | } |
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328 | |||
329 | static void vlv_dsi_device_ready(struct intel_encoder *encoder) |
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330 | { |
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331 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
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332 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
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333 | enum port port; |
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334 | u32 val; |
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335 | |||
336 | DRM_DEBUG_KMS("\n"); |
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337 | |||
338 | mutex_lock(&dev_priv->sb_lock); |
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5060 | serge | 339 | /* program rcomp for compliance, reduce from 50 ohms to 45 ohms |
340 | * needed everytime after power gate */ |
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341 | vlv_flisdsi_write(dev_priv, 0x04, 0x0004); |
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6084 | serge | 342 | mutex_unlock(&dev_priv->sb_lock); |
5060 | serge | 343 | |
344 | /* bandgap reset is needed after everytime we do power gate */ |
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345 | band_gap_reset(dev_priv); |
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346 | |||
6084 | serge | 347 | for_each_dsi_port(port, intel_dsi->ports) { |
5060 | serge | 348 | |
6084 | serge | 349 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_ENTER); |
350 | usleep_range(2500, 3000); |
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4560 | Serge | 351 | |
6084 | serge | 352 | /* Enable MIPI PHY transparent latch |
353 | * Common bit for both MIPI Port A & MIPI Port C |
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354 | * No similar bit in MIPI Port C reg |
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355 | */ |
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356 | val = I915_READ(MIPI_PORT_CTRL(PORT_A)); |
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357 | I915_WRITE(MIPI_PORT_CTRL(PORT_A), val | LP_OUTPUT_HOLD); |
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358 | usleep_range(1000, 1500); |
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4560 | Serge | 359 | |
6084 | serge | 360 | I915_WRITE(MIPI_DEVICE_READY(port), ULPS_STATE_EXIT); |
361 | usleep_range(2500, 3000); |
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362 | |||
363 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY); |
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364 | usleep_range(2500, 3000); |
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365 | } |
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4560 | Serge | 366 | } |
367 | |||
6084 | serge | 368 | static void intel_dsi_device_ready(struct intel_encoder *encoder) |
4560 | Serge | 369 | { |
370 | struct drm_device *dev = encoder->base.dev; |
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6084 | serge | 371 | |
6937 | serge | 372 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) |
6084 | serge | 373 | vlv_dsi_device_ready(encoder); |
374 | else if (IS_BROXTON(dev)) |
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375 | bxt_dsi_device_ready(encoder); |
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376 | } |
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377 | |||
378 | static void intel_dsi_port_enable(struct intel_encoder *encoder) |
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379 | { |
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380 | struct drm_device *dev = encoder->base.dev; |
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4560 | Serge | 381 | struct drm_i915_private *dev_priv = dev->dev_private; |
382 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
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383 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
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6084 | serge | 384 | enum port port; |
6937 | serge | 385 | |
386 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) { |
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4560 | Serge | 387 | u32 temp; |
388 | |||
6084 | serge | 389 | temp = I915_READ(VLV_CHICKEN_3); |
390 | temp &= ~PIXEL_OVERLAP_CNT_MASK | |
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391 | intel_dsi->pixel_overlap << |
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392 | PIXEL_OVERLAP_CNT_SHIFT; |
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393 | I915_WRITE(VLV_CHICKEN_3, temp); |
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394 | } |
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395 | |||
396 | for_each_dsi_port(port, intel_dsi->ports) { |
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6937 | serge | 397 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? |
398 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); |
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399 | u32 temp; |
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6084 | serge | 400 | |
401 | temp = I915_READ(port_ctrl); |
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402 | |||
403 | temp &= ~LANE_CONFIGURATION_MASK; |
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404 | temp &= ~DUAL_LINK_MODE_MASK; |
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405 | |||
406 | if (intel_dsi->ports == ((1 << PORT_A) | (1 << PORT_C))) { |
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407 | temp |= (intel_dsi->dual_link - 1) |
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408 | << DUAL_LINK_MODE_SHIFT; |
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409 | temp |= intel_crtc->pipe ? |
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410 | LANE_CONFIGURATION_DUAL_LINK_B : |
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411 | LANE_CONFIGURATION_DUAL_LINK_A; |
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412 | } |
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413 | /* assert ip_tg_enable signal */ |
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414 | I915_WRITE(port_ctrl, temp | DPI_ENABLE); |
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415 | POSTING_READ(port_ctrl); |
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416 | } |
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417 | } |
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418 | |||
419 | static void intel_dsi_port_disable(struct intel_encoder *encoder) |
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420 | { |
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421 | struct drm_device *dev = encoder->base.dev; |
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422 | struct drm_i915_private *dev_priv = dev->dev_private; |
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423 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
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424 | enum port port; |
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6937 | serge | 425 | |
426 | for_each_dsi_port(port, intel_dsi->ports) { |
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427 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? |
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428 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); |
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6084 | serge | 429 | u32 temp; |
430 | |||
431 | /* de-assert ip_tg_enable signal */ |
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432 | temp = I915_READ(port_ctrl); |
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433 | I915_WRITE(port_ctrl, temp & ~DPI_ENABLE); |
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434 | POSTING_READ(port_ctrl); |
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435 | } |
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436 | } |
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437 | |||
438 | static void intel_dsi_enable(struct intel_encoder *encoder) |
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439 | { |
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440 | struct drm_device *dev = encoder->base.dev; |
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441 | struct drm_i915_private *dev_priv = dev->dev_private; |
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442 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
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443 | enum port port; |
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444 | |||
4560 | Serge | 445 | DRM_DEBUG_KMS("\n"); |
446 | |||
6084 | serge | 447 | if (is_cmd_mode(intel_dsi)) { |
448 | for_each_dsi_port(port, intel_dsi->ports) |
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449 | I915_WRITE(MIPI_MAX_RETURN_PKT_SIZE(port), 8 * 4); |
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450 | } else { |
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4560 | Serge | 451 | msleep(20); /* XXX */ |
6084 | serge | 452 | for_each_dsi_port(port, intel_dsi->ports) |
453 | dpi_send_cmd(intel_dsi, TURN_ON, false, port); |
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4560 | Serge | 454 | msleep(100); |
455 | |||
6084 | serge | 456 | drm_panel_enable(intel_dsi->panel); |
5060 | serge | 457 | |
6084 | serge | 458 | for_each_dsi_port(port, intel_dsi->ports) |
459 | wait_for_dsi_fifo_empty(intel_dsi, port); |
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5060 | serge | 460 | |
6084 | serge | 461 | intel_dsi_port_enable(encoder); |
4560 | Serge | 462 | } |
6084 | serge | 463 | |
464 | intel_panel_enable_backlight(intel_dsi->attached_connector); |
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5060 | serge | 465 | } |
4560 | Serge | 466 | |
6937 | serge | 467 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder); |
468 | |||
5060 | serge | 469 | static void intel_dsi_pre_enable(struct intel_encoder *encoder) |
470 | { |
||
471 | struct drm_device *dev = encoder->base.dev; |
||
472 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
473 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
||
474 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
||
475 | enum pipe pipe = intel_crtc->pipe; |
||
6084 | serge | 476 | enum port port; |
5060 | serge | 477 | u32 tmp; |
478 | |||
479 | DRM_DEBUG_KMS("\n"); |
||
480 | |||
6937 | serge | 481 | intel_dsi_prepare(encoder); |
482 | intel_enable_dsi_pll(encoder); |
||
483 | |||
6084 | serge | 484 | /* Panel Enable over CRC PMIC */ |
485 | if (intel_dsi->gpio_panel) |
||
486 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 1); |
||
5060 | serge | 487 | |
6084 | serge | 488 | msleep(intel_dsi->panel_on_delay); |
5060 | serge | 489 | |
6937 | serge | 490 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
6084 | serge | 491 | /* |
492 | * Disable DPOunit clock gating, can stall pipe |
||
493 | * and we need DPLL REFA always enabled |
||
494 | */ |
||
495 | tmp = I915_READ(DPLL(pipe)); |
||
496 | tmp |= DPLL_REF_CLK_ENABLE_VLV; |
||
497 | I915_WRITE(DPLL(pipe), tmp); |
||
5060 | serge | 498 | |
6084 | serge | 499 | /* update the hw state for DPLL */ |
500 | intel_crtc->config->dpll_hw_state.dpll = |
||
501 | DPLL_INTEGRATED_REF_CLK_VLV | |
||
502 | DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; |
||
503 | |||
504 | tmp = I915_READ(DSPCLK_GATE_D); |
||
505 | tmp |= DPOUNIT_CLOCK_GATE_DISABLE; |
||
506 | I915_WRITE(DSPCLK_GATE_D, tmp); |
||
507 | } |
||
508 | |||
5060 | serge | 509 | /* put device in ready state */ |
510 | intel_dsi_device_ready(encoder); |
||
511 | |||
6084 | serge | 512 | drm_panel_prepare(intel_dsi->panel); |
5060 | serge | 513 | |
6084 | serge | 514 | for_each_dsi_port(port, intel_dsi->ports) |
515 | wait_for_dsi_fifo_empty(intel_dsi, port); |
||
5060 | serge | 516 | |
517 | /* Enable port in pre-enable phase itself because as per hw team |
||
518 | * recommendation, port should be enabled befor plane & pipe */ |
||
519 | intel_dsi_enable(encoder); |
||
4560 | Serge | 520 | } |
521 | |||
5060 | serge | 522 | static void intel_dsi_enable_nop(struct intel_encoder *encoder) |
523 | { |
||
524 | DRM_DEBUG_KMS("\n"); |
||
525 | |||
526 | /* for DSI port enable has to be done before pipe |
||
527 | * and plane enable, so port enable is done in |
||
528 | * pre_enable phase itself unlike other encoders |
||
529 | */ |
||
530 | } |
||
531 | |||
532 | static void intel_dsi_pre_disable(struct intel_encoder *encoder) |
||
533 | { |
||
534 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
||
6084 | serge | 535 | enum port port; |
5060 | serge | 536 | |
537 | DRM_DEBUG_KMS("\n"); |
||
538 | |||
6084 | serge | 539 | intel_panel_disable_backlight(intel_dsi->attached_connector); |
540 | |||
5060 | serge | 541 | if (is_vid_mode(intel_dsi)) { |
542 | /* Send Shutdown command to the panel in LP mode */ |
||
6084 | serge | 543 | for_each_dsi_port(port, intel_dsi->ports) |
544 | dpi_send_cmd(intel_dsi, SHUTDOWN, false, port); |
||
5060 | serge | 545 | msleep(10); |
546 | } |
||
547 | } |
||
548 | |||
4560 | Serge | 549 | static void intel_dsi_disable(struct intel_encoder *encoder) |
550 | { |
||
551 | struct drm_device *dev = encoder->base.dev; |
||
552 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
553 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
||
6084 | serge | 554 | enum port port; |
4560 | Serge | 555 | u32 temp; |
556 | |||
557 | DRM_DEBUG_KMS("\n"); |
||
558 | |||
559 | if (is_vid_mode(intel_dsi)) { |
||
6084 | serge | 560 | for_each_dsi_port(port, intel_dsi->ports) |
561 | wait_for_dsi_fifo_empty(intel_dsi, port); |
||
4560 | Serge | 562 | |
6084 | serge | 563 | intel_dsi_port_disable(encoder); |
4560 | Serge | 564 | msleep(2); |
565 | } |
||
566 | |||
6084 | serge | 567 | for_each_dsi_port(port, intel_dsi->ports) { |
568 | /* Panel commands can be sent when clock is in LP11 */ |
||
569 | I915_WRITE(MIPI_DEVICE_READY(port), 0x0); |
||
5060 | serge | 570 | |
6084 | serge | 571 | intel_dsi_reset_clocks(encoder, port); |
572 | I915_WRITE(MIPI_EOT_DISABLE(port), CLOCKSTOP); |
||
5060 | serge | 573 | |
6084 | serge | 574 | temp = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
575 | temp &= ~VID_MODE_FORMAT_MASK; |
||
576 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), temp); |
||
5060 | serge | 577 | |
6084 | serge | 578 | I915_WRITE(MIPI_DEVICE_READY(port), 0x1); |
579 | } |
||
4560 | Serge | 580 | /* if disable packets are sent before sending shutdown packet then in |
581 | * some next enable sequence send turn on packet error is observed */ |
||
6084 | serge | 582 | drm_panel_disable(intel_dsi->panel); |
5060 | serge | 583 | |
6084 | serge | 584 | for_each_dsi_port(port, intel_dsi->ports) |
585 | wait_for_dsi_fifo_empty(intel_dsi, port); |
||
4560 | Serge | 586 | } |
587 | |||
588 | static void intel_dsi_clear_device_ready(struct intel_encoder *encoder) |
||
589 | { |
||
6084 | serge | 590 | struct drm_device *dev = encoder->base.dev; |
4560 | Serge | 591 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
6084 | serge | 592 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
593 | enum port port; |
||
4560 | Serge | 594 | |
595 | DRM_DEBUG_KMS("\n"); |
||
6084 | serge | 596 | for_each_dsi_port(port, intel_dsi->ports) { |
6937 | serge | 597 | /* Common bit for both MIPI Port A & MIPI Port C on VLV/CHV */ |
598 | i915_reg_t port_ctrl = IS_BROXTON(dev) ? |
||
599 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(PORT_A); |
||
600 | u32 val; |
||
4560 | Serge | 601 | |
6084 | serge | 602 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
603 | ULPS_STATE_ENTER); |
||
604 | usleep_range(2000, 2500); |
||
4560 | Serge | 605 | |
6084 | serge | 606 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
607 | ULPS_STATE_EXIT); |
||
608 | usleep_range(2000, 2500); |
||
4560 | Serge | 609 | |
6084 | serge | 610 | I915_WRITE(MIPI_DEVICE_READY(port), DEVICE_READY | |
611 | ULPS_STATE_ENTER); |
||
612 | usleep_range(2000, 2500); |
||
4560 | Serge | 613 | |
6084 | serge | 614 | /* Wait till Clock lanes are in LP-00 state for MIPI Port A |
615 | * only. MIPI Port C has no similar bit for checking |
||
616 | */ |
||
617 | if (wait_for(((I915_READ(port_ctrl) & AFE_LATCHOUT) |
||
618 | == 0x00000), 30)) |
||
619 | DRM_ERROR("DSI LP not going Low\n"); |
||
4560 | Serge | 620 | |
6084 | serge | 621 | /* Disable MIPI PHY transparent latch */ |
622 | val = I915_READ(port_ctrl); |
||
623 | I915_WRITE(port_ctrl, val & ~LP_OUTPUT_HOLD); |
||
624 | usleep_range(1000, 1500); |
||
4560 | Serge | 625 | |
6084 | serge | 626 | I915_WRITE(MIPI_DEVICE_READY(port), 0x00); |
627 | usleep_range(2000, 2500); |
||
628 | } |
||
629 | |||
630 | intel_disable_dsi_pll(encoder); |
||
4560 | Serge | 631 | } |
5060 | serge | 632 | |
4560 | Serge | 633 | static void intel_dsi_post_disable(struct intel_encoder *encoder) |
634 | { |
||
5060 | serge | 635 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
4560 | Serge | 636 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
5060 | serge | 637 | u32 val; |
4560 | Serge | 638 | |
639 | DRM_DEBUG_KMS("\n"); |
||
640 | |||
5060 | serge | 641 | intel_dsi_disable(encoder); |
642 | |||
4560 | Serge | 643 | intel_dsi_clear_device_ready(encoder); |
644 | |||
5060 | serge | 645 | val = I915_READ(DSPCLK_GATE_D); |
646 | val &= ~DPOUNIT_CLOCK_GATE_DISABLE; |
||
647 | I915_WRITE(DSPCLK_GATE_D, val); |
||
648 | |||
6084 | serge | 649 | drm_panel_unprepare(intel_dsi->panel); |
5060 | serge | 650 | |
651 | msleep(intel_dsi->panel_off_delay); |
||
652 | msleep(intel_dsi->panel_pwr_cycle_delay); |
||
6084 | serge | 653 | |
654 | /* Panel Disable over CRC PMIC */ |
||
655 | if (intel_dsi->gpio_panel) |
||
656 | gpiod_set_value_cansleep(intel_dsi->gpio_panel, 0); |
||
4560 | Serge | 657 | } |
658 | |||
659 | static bool intel_dsi_get_hw_state(struct intel_encoder *encoder, |
||
660 | enum pipe *pipe) |
||
661 | { |
||
662 | struct drm_i915_private *dev_priv = encoder->base.dev->dev_private; |
||
6084 | serge | 663 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(&encoder->base); |
664 | struct drm_device *dev = encoder->base.dev; |
||
5060 | serge | 665 | enum intel_display_power_domain power_domain; |
6084 | serge | 666 | enum port port; |
6937 | serge | 667 | bool ret; |
4560 | Serge | 668 | |
669 | DRM_DEBUG_KMS("\n"); |
||
670 | |||
5060 | serge | 671 | power_domain = intel_display_port_power_domain(encoder); |
6937 | serge | 672 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
5060 | serge | 673 | return false; |
674 | |||
6937 | serge | 675 | ret = false; |
676 | |||
4560 | Serge | 677 | /* XXX: this only works for one DSI output */ |
6084 | serge | 678 | for_each_dsi_port(port, intel_dsi->ports) { |
6937 | serge | 679 | i915_reg_t ctrl_reg = IS_BROXTON(dev) ? |
680 | BXT_MIPI_PORT_CTRL(port) : MIPI_PORT_CTRL(port); |
||
681 | u32 dpi_enabled, func; |
||
682 | |||
6084 | serge | 683 | func = I915_READ(MIPI_DSI_FUNC_PRG(port)); |
684 | dpi_enabled = I915_READ(ctrl_reg) & DPI_ENABLE; |
||
4560 | Serge | 685 | |
6084 | serge | 686 | /* Due to some hardware limitations on BYT, MIPI Port C DPI |
687 | * Enable bit does not get set. To check whether DSI Port C |
||
688 | * was enabled in BIOS, check the Pipe B enable bit |
||
689 | */ |
||
6937 | serge | 690 | if (IS_VALLEYVIEW(dev) && port == PORT_C) |
6084 | serge | 691 | dpi_enabled = I915_READ(PIPECONF(PIPE_B)) & |
692 | PIPECONF_ENABLE; |
||
693 | |||
694 | if (dpi_enabled || (func & CMD_MODE_DATA_WIDTH_MASK)) { |
||
695 | if (I915_READ(MIPI_DEVICE_READY(port)) & DEVICE_READY) { |
||
696 | *pipe = port == PORT_A ? PIPE_A : PIPE_B; |
||
6937 | serge | 697 | ret = true; |
698 | |||
699 | goto out; |
||
4560 | Serge | 700 | } |
701 | } |
||
702 | } |
||
6937 | serge | 703 | out: |
704 | intel_display_power_put(dev_priv, power_domain); |
||
4560 | Serge | 705 | |
6937 | serge | 706 | return ret; |
4560 | Serge | 707 | } |
708 | |||
709 | static void intel_dsi_get_config(struct intel_encoder *encoder, |
||
6084 | serge | 710 | struct intel_crtc_state *pipe_config) |
4560 | Serge | 711 | { |
6084 | serge | 712 | u32 pclk = 0; |
4560 | Serge | 713 | DRM_DEBUG_KMS("\n"); |
714 | |||
6937 | serge | 715 | pipe_config->has_dsi_encoder = true; |
716 | |||
5060 | serge | 717 | /* |
718 | * DPLL_MD is not used in case of DSI, reading will get some default value |
||
719 | * set dpll_md = 0 |
||
720 | */ |
||
721 | pipe_config->dpll_hw_state.dpll_md = 0; |
||
722 | |||
6084 | serge | 723 | if (IS_BROXTON(encoder->base.dev)) |
724 | pclk = bxt_get_dsi_pclk(encoder, pipe_config->pipe_bpp); |
||
6937 | serge | 725 | else if (IS_VALLEYVIEW(encoder->base.dev) || |
726 | IS_CHERRYVIEW(encoder->base.dev)) |
||
6084 | serge | 727 | pclk = vlv_get_dsi_pclk(encoder, pipe_config->pipe_bpp); |
728 | |||
5060 | serge | 729 | if (!pclk) |
730 | return; |
||
731 | |||
6084 | serge | 732 | pipe_config->base.adjusted_mode.crtc_clock = pclk; |
5060 | serge | 733 | pipe_config->port_clock = pclk; |
4560 | Serge | 734 | } |
735 | |||
736 | static enum drm_mode_status |
||
737 | intel_dsi_mode_valid(struct drm_connector *connector, |
||
738 | struct drm_display_mode *mode) |
||
739 | { |
||
740 | struct intel_connector *intel_connector = to_intel_connector(connector); |
||
741 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
||
6084 | serge | 742 | int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; |
4560 | Serge | 743 | |
744 | DRM_DEBUG_KMS("\n"); |
||
745 | |||
746 | if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { |
||
747 | DRM_DEBUG_KMS("MODE_NO_DBLESCAN\n"); |
||
748 | return MODE_NO_DBLESCAN; |
||
749 | } |
||
750 | |||
751 | if (fixed_mode) { |
||
752 | if (mode->hdisplay > fixed_mode->hdisplay) |
||
753 | return MODE_PANEL; |
||
754 | if (mode->vdisplay > fixed_mode->vdisplay) |
||
755 | return MODE_PANEL; |
||
6084 | serge | 756 | if (fixed_mode->clock > max_dotclk) |
757 | return MODE_CLOCK_HIGH; |
||
4560 | Serge | 758 | } |
759 | |||
6084 | serge | 760 | return MODE_OK; |
4560 | Serge | 761 | } |
762 | |||
763 | /* return txclkesc cycles in terms of divider and duration in us */ |
||
764 | static u16 txclkesc(u32 divider, unsigned int us) |
||
765 | { |
||
766 | switch (divider) { |
||
767 | case ESCAPE_CLOCK_DIVIDER_1: |
||
768 | default: |
||
769 | return 20 * us; |
||
770 | case ESCAPE_CLOCK_DIVIDER_2: |
||
771 | return 10 * us; |
||
772 | case ESCAPE_CLOCK_DIVIDER_4: |
||
773 | return 5 * us; |
||
774 | } |
||
775 | } |
||
776 | |||
777 | /* return pixels in terms of txbyteclkhs */ |
||
5354 | serge | 778 | static u16 txbyteclkhs(u16 pixels, int bpp, int lane_count, |
779 | u16 burst_mode_ratio) |
||
4560 | Serge | 780 | { |
5354 | serge | 781 | return DIV_ROUND_UP(DIV_ROUND_UP(pixels * bpp * burst_mode_ratio, |
782 | 8 * 100), lane_count); |
||
4560 | Serge | 783 | } |
784 | |||
785 | static void set_dsi_timings(struct drm_encoder *encoder, |
||
6084 | serge | 786 | const struct drm_display_mode *adjusted_mode) |
4560 | Serge | 787 | { |
788 | struct drm_device *dev = encoder->dev; |
||
789 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
790 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
||
791 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
||
6084 | serge | 792 | enum port port; |
793 | unsigned int bpp = intel_crtc->config->pipe_bpp; |
||
4560 | Serge | 794 | unsigned int lane_count = intel_dsi->lane_count; |
795 | |||
796 | u16 hactive, hfp, hsync, hbp, vfp, vsync, vbp; |
||
797 | |||
6084 | serge | 798 | hactive = adjusted_mode->crtc_hdisplay; |
799 | hfp = adjusted_mode->crtc_hsync_start - adjusted_mode->crtc_hdisplay; |
||
800 | hsync = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; |
||
801 | hbp = adjusted_mode->crtc_htotal - adjusted_mode->crtc_hsync_end; |
||
4560 | Serge | 802 | |
6084 | serge | 803 | if (intel_dsi->dual_link) { |
804 | hactive /= 2; |
||
805 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) |
||
806 | hactive += intel_dsi->pixel_overlap; |
||
807 | hfp /= 2; |
||
808 | hsync /= 2; |
||
809 | hbp /= 2; |
||
810 | } |
||
4560 | Serge | 811 | |
6084 | serge | 812 | vfp = adjusted_mode->crtc_vsync_start - adjusted_mode->crtc_vdisplay; |
813 | vsync = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; |
||
814 | vbp = adjusted_mode->crtc_vtotal - adjusted_mode->crtc_vsync_end; |
||
815 | |||
4560 | Serge | 816 | /* horizontal values are in terms of high speed byte clock */ |
5354 | serge | 817 | hactive = txbyteclkhs(hactive, bpp, lane_count, |
818 | intel_dsi->burst_mode_ratio); |
||
819 | hfp = txbyteclkhs(hfp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
||
820 | hsync = txbyteclkhs(hsync, bpp, lane_count, |
||
821 | intel_dsi->burst_mode_ratio); |
||
822 | hbp = txbyteclkhs(hbp, bpp, lane_count, intel_dsi->burst_mode_ratio); |
||
4560 | Serge | 823 | |
6084 | serge | 824 | for_each_dsi_port(port, intel_dsi->ports) { |
825 | if (IS_BROXTON(dev)) { |
||
826 | /* |
||
827 | * Program hdisplay and vdisplay on MIPI transcoder. |
||
828 | * This is different from calculated hactive and |
||
829 | * vactive, as they are calculated per channel basis, |
||
830 | * whereas these values should be based on resolution. |
||
831 | */ |
||
832 | I915_WRITE(BXT_MIPI_TRANS_HACTIVE(port), |
||
833 | adjusted_mode->crtc_hdisplay); |
||
834 | I915_WRITE(BXT_MIPI_TRANS_VACTIVE(port), |
||
835 | adjusted_mode->crtc_vdisplay); |
||
836 | I915_WRITE(BXT_MIPI_TRANS_VTOTAL(port), |
||
837 | adjusted_mode->crtc_vtotal); |
||
838 | } |
||
4560 | Serge | 839 | |
6084 | serge | 840 | I915_WRITE(MIPI_HACTIVE_AREA_COUNT(port), hactive); |
841 | I915_WRITE(MIPI_HFP_COUNT(port), hfp); |
||
4560 | Serge | 842 | |
6084 | serge | 843 | /* meaningful for video mode non-burst sync pulse mode only, |
844 | * can be zero for non-burst sync events and burst modes */ |
||
845 | I915_WRITE(MIPI_HSYNC_PADDING_COUNT(port), hsync); |
||
846 | I915_WRITE(MIPI_HBP_COUNT(port), hbp); |
||
847 | |||
848 | /* vertical values are in terms of lines */ |
||
849 | I915_WRITE(MIPI_VFP_COUNT(port), vfp); |
||
850 | I915_WRITE(MIPI_VSYNC_PADDING_COUNT(port), vsync); |
||
851 | I915_WRITE(MIPI_VBP_COUNT(port), vbp); |
||
852 | } |
||
4560 | Serge | 853 | } |
854 | |||
5060 | serge | 855 | static void intel_dsi_prepare(struct intel_encoder *intel_encoder) |
4560 | Serge | 856 | { |
857 | struct drm_encoder *encoder = &intel_encoder->base; |
||
858 | struct drm_device *dev = encoder->dev; |
||
859 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
860 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); |
||
861 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
||
6084 | serge | 862 | const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode; |
863 | enum port port; |
||
864 | unsigned int bpp = intel_crtc->config->pipe_bpp; |
||
4560 | Serge | 865 | u32 val, tmp; |
6084 | serge | 866 | u16 mode_hdisplay; |
4560 | Serge | 867 | |
6084 | serge | 868 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(intel_crtc->pipe)); |
4560 | Serge | 869 | |
6084 | serge | 870 | mode_hdisplay = adjusted_mode->crtc_hdisplay; |
4560 | Serge | 871 | |
6084 | serge | 872 | if (intel_dsi->dual_link) { |
873 | mode_hdisplay /= 2; |
||
874 | if (intel_dsi->dual_link == DSI_DUAL_LINK_FRONT_BACK) |
||
875 | mode_hdisplay += intel_dsi->pixel_overlap; |
||
876 | } |
||
4560 | Serge | 877 | |
6084 | serge | 878 | for_each_dsi_port(port, intel_dsi->ports) { |
6937 | serge | 879 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
6084 | serge | 880 | /* |
881 | * escape clock divider, 20MHz, shared for A and C. |
||
882 | * device ready must be off when doing this! txclkesc? |
||
883 | */ |
||
884 | tmp = I915_READ(MIPI_CTRL(PORT_A)); |
||
885 | tmp &= ~ESCAPE_CLOCK_DIVIDER_MASK; |
||
886 | I915_WRITE(MIPI_CTRL(PORT_A), tmp | |
||
887 | ESCAPE_CLOCK_DIVIDER_1); |
||
4560 | Serge | 888 | |
6084 | serge | 889 | /* read request priority is per pipe */ |
890 | tmp = I915_READ(MIPI_CTRL(port)); |
||
891 | tmp &= ~READ_REQUEST_PRIORITY_MASK; |
||
892 | I915_WRITE(MIPI_CTRL(port), tmp | |
||
893 | READ_REQUEST_PRIORITY_HIGH); |
||
894 | } else if (IS_BROXTON(dev)) { |
||
6937 | serge | 895 | enum pipe pipe = intel_crtc->pipe; |
896 | |||
6084 | serge | 897 | tmp = I915_READ(MIPI_CTRL(port)); |
898 | tmp &= ~BXT_PIPE_SELECT_MASK; |
||
4560 | Serge | 899 | |
6937 | serge | 900 | tmp |= BXT_PIPE_SELECT(pipe); |
6084 | serge | 901 | I915_WRITE(MIPI_CTRL(port), tmp); |
902 | } |
||
903 | |||
904 | /* XXX: why here, why like this? handling in irq handler?! */ |
||
905 | I915_WRITE(MIPI_INTR_STAT(port), 0xffffffff); |
||
906 | I915_WRITE(MIPI_INTR_EN(port), 0xffffffff); |
||
907 | |||
908 | I915_WRITE(MIPI_DPHY_PARAM(port), intel_dsi->dphy_reg); |
||
909 | |||
910 | I915_WRITE(MIPI_DPI_RESOLUTION(port), |
||
911 | adjusted_mode->crtc_vdisplay << VERTICAL_ADDRESS_SHIFT | |
||
912 | mode_hdisplay << HORIZONTAL_ADDRESS_SHIFT); |
||
913 | } |
||
914 | |||
4560 | Serge | 915 | set_dsi_timings(encoder, adjusted_mode); |
916 | |||
917 | val = intel_dsi->lane_count << DATA_LANES_PRG_REG_SHIFT; |
||
918 | if (is_cmd_mode(intel_dsi)) { |
||
919 | val |= intel_dsi->channel << CMD_MODE_CHANNEL_NUMBER_SHIFT; |
||
920 | val |= CMD_MODE_DATA_WIDTH_8_BIT; /* XXX */ |
||
921 | } else { |
||
922 | val |= intel_dsi->channel << VID_MODE_CHANNEL_NUMBER_SHIFT; |
||
923 | |||
924 | /* XXX: cross-check bpp vs. pixel format? */ |
||
925 | val |= intel_dsi->pixel_format; |
||
926 | } |
||
927 | |||
6084 | serge | 928 | tmp = 0; |
929 | if (intel_dsi->eotp_pkt == 0) |
||
930 | tmp |= EOT_DISABLE; |
||
931 | if (intel_dsi->clock_stop) |
||
932 | tmp |= CLOCKSTOP; |
||
4560 | Serge | 933 | |
6084 | serge | 934 | for_each_dsi_port(port, intel_dsi->ports) { |
935 | I915_WRITE(MIPI_DSI_FUNC_PRG(port), val); |
||
4560 | Serge | 936 | |
6084 | serge | 937 | /* timeouts for recovery. one frame IIUC. if counter expires, |
938 | * EOT and stop state. */ |
||
4560 | Serge | 939 | |
6084 | serge | 940 | /* |
941 | * In burst mode, value greater than one DPI line Time in byte |
||
942 | * clock (txbyteclkhs) To timeout this timer 1+ of the above |
||
943 | * said value is recommended. |
||
944 | * |
||
945 | * In non-burst mode, Value greater than one DPI frame time in |
||
946 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above |
||
947 | * said value is recommended. |
||
948 | * |
||
949 | * In DBI only mode, value greater than one DBI frame time in |
||
950 | * byte clock(txbyteclkhs) To timeout this timer 1+ of the above |
||
951 | * said value is recommended. |
||
952 | */ |
||
4560 | Serge | 953 | |
6084 | serge | 954 | if (is_vid_mode(intel_dsi) && |
955 | intel_dsi->video_mode_format == VIDEO_MODE_BURST) { |
||
956 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), |
||
957 | txbyteclkhs(adjusted_mode->crtc_htotal, bpp, |
||
958 | intel_dsi->lane_count, |
||
959 | intel_dsi->burst_mode_ratio) + 1); |
||
960 | } else { |
||
961 | I915_WRITE(MIPI_HS_TX_TIMEOUT(port), |
||
962 | txbyteclkhs(adjusted_mode->crtc_vtotal * |
||
963 | adjusted_mode->crtc_htotal, |
||
964 | bpp, intel_dsi->lane_count, |
||
965 | intel_dsi->burst_mode_ratio) + 1); |
||
966 | } |
||
967 | I915_WRITE(MIPI_LP_RX_TIMEOUT(port), intel_dsi->lp_rx_timeout); |
||
968 | I915_WRITE(MIPI_TURN_AROUND_TIMEOUT(port), |
||
969 | intel_dsi->turn_arnd_val); |
||
970 | I915_WRITE(MIPI_DEVICE_RESET_TIMER(port), |
||
971 | intel_dsi->rst_timer_val); |
||
4560 | Serge | 972 | |
6084 | serge | 973 | /* dphy stuff */ |
5060 | serge | 974 | |
6084 | serge | 975 | /* in terms of low power clock */ |
976 | I915_WRITE(MIPI_INIT_COUNT(port), |
||
977 | txclkesc(intel_dsi->escape_clk_div, 100)); |
||
5060 | serge | 978 | |
6084 | serge | 979 | if (IS_BROXTON(dev) && (!intel_dsi->dual_link)) { |
980 | /* |
||
981 | * BXT spec says write MIPI_INIT_COUNT for |
||
982 | * both the ports, even if only one is |
||
983 | * getting used. So write the other port |
||
984 | * if not in dual link mode. |
||
985 | */ |
||
986 | I915_WRITE(MIPI_INIT_COUNT(port == |
||
987 | PORT_A ? PORT_C : PORT_A), |
||
988 | intel_dsi->init_count); |
||
989 | } |
||
4560 | Serge | 990 | |
6084 | serge | 991 | /* recovery disables */ |
992 | I915_WRITE(MIPI_EOT_DISABLE(port), tmp); |
||
5060 | serge | 993 | |
6084 | serge | 994 | /* in terms of low power clock */ |
995 | I915_WRITE(MIPI_INIT_COUNT(port), intel_dsi->init_count); |
||
996 | |||
997 | /* in terms of txbyteclkhs. actual high to low switch + |
||
998 | * MIPI_STOP_STATE_STALL * MIPI_LP_BYTECLK. |
||
999 | * |
||
1000 | * XXX: write MIPI_STOP_STATE_STALL? |
||
1001 | */ |
||
1002 | I915_WRITE(MIPI_HIGH_LOW_SWITCH_COUNT(port), |
||
4560 | Serge | 1003 | intel_dsi->hs_to_lp_count); |
1004 | |||
6084 | serge | 1005 | /* XXX: low power clock equivalence in terms of byte clock. |
1006 | * the number of byte clocks occupied in one low power clock. |
||
1007 | * based on txbyteclkhs and txclkesc. |
||
1008 | * txclkesc time / txbyteclk time * (105 + MIPI_STOP_STATE_STALL |
||
1009 | * ) / 105.??? |
||
1010 | */ |
||
1011 | I915_WRITE(MIPI_LP_BYTECLK(port), intel_dsi->lp_byte_clk); |
||
4560 | Serge | 1012 | |
6084 | serge | 1013 | /* the bw essential for transmitting 16 long packets containing |
1014 | * 252 bytes meant for dcs write memory command is programmed in |
||
1015 | * this register in terms of byte clocks. based on dsi transfer |
||
1016 | * rate and the number of lanes configured the time taken to |
||
1017 | * transmit 16 long packets in a dsi stream varies. */ |
||
1018 | I915_WRITE(MIPI_DBI_BW_CTRL(port), intel_dsi->bw_timer); |
||
4560 | Serge | 1019 | |
6084 | serge | 1020 | I915_WRITE(MIPI_CLK_LANE_SWITCH_TIME_CNT(port), |
1021 | intel_dsi->clk_lp_to_hs_count << LP_HS_SSW_CNT_SHIFT | |
||
1022 | intel_dsi->clk_hs_to_lp_count << HS_LP_PWR_SW_CNT_SHIFT); |
||
4560 | Serge | 1023 | |
6084 | serge | 1024 | if (is_vid_mode(intel_dsi)) |
1025 | /* Some panels might have resolution which is not a |
||
1026 | * multiple of 64 like 1366 x 768. Enable RANDOM |
||
1027 | * resolution support for such panels by default */ |
||
1028 | I915_WRITE(MIPI_VIDEO_MODE_FORMAT(port), |
||
4560 | Serge | 1029 | intel_dsi->video_frmt_cfg_bits | |
5060 | serge | 1030 | intel_dsi->video_mode_format | |
1031 | IP_TG_CONFIG | |
||
1032 | RANDOM_DPI_DISPLAY_RESOLUTION); |
||
6084 | serge | 1033 | } |
4560 | Serge | 1034 | } |
1035 | |||
1036 | static enum drm_connector_status |
||
1037 | intel_dsi_detect(struct drm_connector *connector, bool force) |
||
1038 | { |
||
6084 | serge | 1039 | return connector_status_connected; |
4560 | Serge | 1040 | } |
1041 | |||
1042 | static int intel_dsi_get_modes(struct drm_connector *connector) |
||
1043 | { |
||
1044 | struct intel_connector *intel_connector = to_intel_connector(connector); |
||
1045 | struct drm_display_mode *mode; |
||
1046 | |||
1047 | DRM_DEBUG_KMS("\n"); |
||
1048 | |||
1049 | if (!intel_connector->panel.fixed_mode) { |
||
1050 | DRM_DEBUG_KMS("no fixed mode\n"); |
||
1051 | return 0; |
||
1052 | } |
||
1053 | |||
1054 | mode = drm_mode_duplicate(connector->dev, |
||
1055 | intel_connector->panel.fixed_mode); |
||
1056 | if (!mode) { |
||
1057 | DRM_DEBUG_KMS("drm_mode_duplicate failed\n"); |
||
1058 | return 0; |
||
1059 | } |
||
1060 | |||
1061 | drm_mode_probed_add(connector, mode); |
||
1062 | return 1; |
||
1063 | } |
||
1064 | |||
6084 | serge | 1065 | static void intel_dsi_connector_destroy(struct drm_connector *connector) |
4560 | Serge | 1066 | { |
1067 | struct intel_connector *intel_connector = to_intel_connector(connector); |
||
1068 | |||
1069 | DRM_DEBUG_KMS("\n"); |
||
1070 | intel_panel_fini(&intel_connector->panel); |
||
1071 | drm_connector_cleanup(connector); |
||
1072 | kfree(connector); |
||
1073 | } |
||
1074 | |||
6084 | serge | 1075 | static void intel_dsi_encoder_destroy(struct drm_encoder *encoder) |
1076 | { |
||
1077 | struct intel_dsi *intel_dsi = enc_to_intel_dsi(encoder); |
||
1078 | |||
1079 | if (intel_dsi->panel) { |
||
1080 | drm_panel_detach(intel_dsi->panel); |
||
1081 | /* XXX: Logically this call belongs in the panel driver. */ |
||
1082 | drm_panel_remove(intel_dsi->panel); |
||
1083 | } |
||
1084 | |||
1085 | /* dispose of the gpios */ |
||
1086 | if (intel_dsi->gpio_panel) |
||
1087 | gpiod_put(intel_dsi->gpio_panel); |
||
1088 | |||
1089 | intel_encoder_destroy(encoder); |
||
1090 | } |
||
1091 | |||
4560 | Serge | 1092 | static const struct drm_encoder_funcs intel_dsi_funcs = { |
6084 | serge | 1093 | .destroy = intel_dsi_encoder_destroy, |
4560 | Serge | 1094 | }; |
1095 | |||
1096 | static const struct drm_connector_helper_funcs intel_dsi_connector_helper_funcs = { |
||
1097 | .get_modes = intel_dsi_get_modes, |
||
1098 | .mode_valid = intel_dsi_mode_valid, |
||
1099 | .best_encoder = intel_best_encoder, |
||
1100 | }; |
||
1101 | |||
1102 | static const struct drm_connector_funcs intel_dsi_connector_funcs = { |
||
6084 | serge | 1103 | .dpms = drm_atomic_helper_connector_dpms, |
4560 | Serge | 1104 | .detect = intel_dsi_detect, |
6084 | serge | 1105 | .destroy = intel_dsi_connector_destroy, |
4560 | Serge | 1106 | .fill_modes = drm_helper_probe_single_connector_modes, |
6084 | serge | 1107 | .atomic_get_property = intel_connector_atomic_get_property, |
1108 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
||
1109 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
||
4560 | Serge | 1110 | }; |
1111 | |||
5060 | serge | 1112 | void intel_dsi_init(struct drm_device *dev) |
4560 | Serge | 1113 | { |
1114 | struct intel_dsi *intel_dsi; |
||
1115 | struct intel_encoder *intel_encoder; |
||
1116 | struct drm_encoder *encoder; |
||
1117 | struct intel_connector *intel_connector; |
||
1118 | struct drm_connector *connector; |
||
6084 | serge | 1119 | struct drm_display_mode *scan, *fixed_mode = NULL; |
5060 | serge | 1120 | struct drm_i915_private *dev_priv = dev->dev_private; |
6084 | serge | 1121 | enum port port; |
4560 | Serge | 1122 | unsigned int i; |
1123 | |||
1124 | DRM_DEBUG_KMS("\n"); |
||
1125 | |||
5060 | serge | 1126 | /* There is no detection method for MIPI so rely on VBT */ |
1127 | if (!dev_priv->vbt.has_mipi) |
||
1128 | return; |
||
1129 | |||
6937 | serge | 1130 | if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) { |
5060 | serge | 1131 | dev_priv->mipi_mmio_base = VLV_MIPI_BASE; |
1132 | } else { |
||
1133 | DRM_ERROR("Unsupported Mipi device to reg base"); |
||
1134 | return; |
||
1135 | } |
||
1136 | |||
4560 | Serge | 1137 | intel_dsi = kzalloc(sizeof(*intel_dsi), GFP_KERNEL); |
1138 | if (!intel_dsi) |
||
5060 | serge | 1139 | return; |
4560 | Serge | 1140 | |
6084 | serge | 1141 | intel_connector = intel_connector_alloc(); |
4560 | Serge | 1142 | if (!intel_connector) { |
1143 | kfree(intel_dsi); |
||
5060 | serge | 1144 | return; |
4560 | Serge | 1145 | } |
1146 | |||
1147 | intel_encoder = &intel_dsi->base; |
||
1148 | encoder = &intel_encoder->base; |
||
1149 | intel_dsi->attached_connector = intel_connector; |
||
1150 | |||
1151 | connector = &intel_connector->base; |
||
1152 | |||
6937 | serge | 1153 | drm_encoder_init(dev, encoder, &intel_dsi_funcs, DRM_MODE_ENCODER_DSI, |
1154 | NULL); |
||
4560 | Serge | 1155 | |
1156 | intel_encoder->compute_config = intel_dsi_compute_config; |
||
1157 | intel_encoder->pre_enable = intel_dsi_pre_enable; |
||
5060 | serge | 1158 | intel_encoder->enable = intel_dsi_enable_nop; |
1159 | intel_encoder->disable = intel_dsi_pre_disable; |
||
4560 | Serge | 1160 | intel_encoder->post_disable = intel_dsi_post_disable; |
1161 | intel_encoder->get_hw_state = intel_dsi_get_hw_state; |
||
1162 | intel_encoder->get_config = intel_dsi_get_config; |
||
1163 | |||
1164 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
||
5060 | serge | 1165 | intel_connector->unregister = intel_connector_unregister; |
4560 | Serge | 1166 | |
6084 | serge | 1167 | /* Pipe A maps to MIPI DSI port A, pipe B maps to MIPI DSI port C */ |
1168 | if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIA) { |
||
1169 | intel_encoder->crtc_mask = (1 << PIPE_A); |
||
1170 | intel_dsi->ports = (1 << PORT_A); |
||
1171 | } else if (dev_priv->vbt.dsi.port == DVO_PORT_MIPIC) { |
||
1172 | intel_encoder->crtc_mask = (1 << PIPE_B); |
||
1173 | intel_dsi->ports = (1 << PORT_C); |
||
1174 | } |
||
4560 | Serge | 1175 | |
6084 | serge | 1176 | if (dev_priv->vbt.dsi.config->dual_link) |
1177 | intel_dsi->ports = ((1 << PORT_A) | (1 << PORT_C)); |
||
1178 | |||
1179 | /* Create a DSI host (and a device) for each port. */ |
||
1180 | for_each_dsi_port(port, intel_dsi->ports) { |
||
1181 | struct intel_dsi_host *host; |
||
1182 | |||
1183 | host = intel_dsi_host_init(intel_dsi, port); |
||
1184 | if (!host) |
||
1185 | goto err; |
||
1186 | |||
1187 | intel_dsi->dsi_hosts[port] = host; |
||
1188 | } |
||
1189 | |||
1190 | for (i = 0; i < ARRAY_SIZE(intel_dsi_drivers); i++) { |
||
1191 | intel_dsi->panel = intel_dsi_drivers[i].init(intel_dsi, |
||
1192 | intel_dsi_drivers[i].panel_id); |
||
1193 | if (intel_dsi->panel) |
||
4560 | Serge | 1194 | break; |
1195 | } |
||
1196 | |||
6084 | serge | 1197 | if (!intel_dsi->panel) { |
4560 | Serge | 1198 | DRM_DEBUG_KMS("no device found\n"); |
1199 | goto err; |
||
1200 | } |
||
1201 | |||
6084 | serge | 1202 | /* |
1203 | * In case of BYT with CRC PMIC, we need to use GPIO for |
||
1204 | * Panel control. |
||
1205 | */ |
||
1206 | if (dev_priv->vbt.dsi.config->pwm_blc == PPS_BLC_PMIC) { |
||
1207 | intel_dsi->gpio_panel = |
||
1208 | gpiod_get(dev->dev, "panel", GPIOD_OUT_HIGH); |
||
1209 | |||
1210 | if (IS_ERR(intel_dsi->gpio_panel)) { |
||
1211 | DRM_ERROR("Failed to own gpio for panel control\n"); |
||
1212 | intel_dsi->gpio_panel = NULL; |
||
1213 | } |
||
1214 | } |
||
1215 | |||
4560 | Serge | 1216 | intel_encoder->type = INTEL_OUTPUT_DSI; |
5060 | serge | 1217 | intel_encoder->cloneable = 0; |
4560 | Serge | 1218 | drm_connector_init(dev, connector, &intel_dsi_connector_funcs, |
1219 | DRM_MODE_CONNECTOR_DSI); |
||
1220 | |||
1221 | drm_connector_helper_add(connector, &intel_dsi_connector_helper_funcs); |
||
1222 | |||
1223 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; /*XXX*/ |
||
1224 | connector->interlace_allowed = false; |
||
1225 | connector->doublescan_allowed = false; |
||
1226 | |||
1227 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
||
1228 | |||
5060 | serge | 1229 | drm_connector_register(connector); |
4560 | Serge | 1230 | |
6084 | serge | 1231 | drm_panel_attach(intel_dsi->panel, connector); |
1232 | |||
1233 | mutex_lock(&dev->mode_config.mutex); |
||
1234 | drm_panel_get_modes(intel_dsi->panel); |
||
1235 | list_for_each_entry(scan, &connector->probed_modes, head) { |
||
1236 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
||
1237 | fixed_mode = drm_mode_duplicate(dev, scan); |
||
1238 | break; |
||
1239 | } |
||
1240 | } |
||
1241 | mutex_unlock(&dev->mode_config.mutex); |
||
1242 | |||
4560 | Serge | 1243 | if (!fixed_mode) { |
1244 | DRM_DEBUG_KMS("no fixed mode\n"); |
||
1245 | goto err; |
||
1246 | } |
||
1247 | |||
5060 | serge | 1248 | intel_panel_init(&intel_connector->panel, fixed_mode, NULL); |
6084 | serge | 1249 | intel_panel_setup_backlight(connector, INVALID_PIPE); |
4560 | Serge | 1250 | |
5060 | serge | 1251 | return; |
4560 | Serge | 1252 | |
1253 | err: |
||
1254 | drm_encoder_cleanup(&intel_encoder->base); |
||
1255 | kfree(intel_dsi); |
||
1256 | kfree(intel_connector); |
||
1257 | }>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |