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Rev | Author | Line No. | Line |
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2327 | Serge | 1 | /* |
2 | * Copyright © 2008 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Keith Packard |
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25 | * |
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26 | */ |
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27 | |||
28 | #include |
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2330 | Serge | 29 | #include |
3031 | serge | 30 | #include |
31 | #include |
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32 | #include |
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33 | #include |
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34 | #include |
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2327 | Serge | 35 | #include "intel_drv.h" |
3031 | serge | 36 | #include |
2327 | Serge | 37 | #include "i915_drv.h" |
38 | |||
39 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
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40 | |||
41 | /** |
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42 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
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43 | * @intel_dp: DP struct |
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44 | * |
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45 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
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46 | * will return true, and false otherwise. |
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47 | */ |
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48 | static bool is_edp(struct intel_dp *intel_dp) |
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49 | { |
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3243 | Serge | 50 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
51 | |||
52 | return intel_dig_port->base.type == INTEL_OUTPUT_EDP; |
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2327 | Serge | 53 | } |
54 | |||
55 | /** |
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56 | * is_pch_edp - is the port on the PCH and attached to an eDP panel? |
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57 | * @intel_dp: DP struct |
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58 | * |
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59 | * Returns true if the given DP struct corresponds to a PCH DP port attached |
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60 | * to an eDP panel, false otherwise. Helpful for determining whether we |
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61 | * may need FDI resources for a given DP output or not. |
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62 | */ |
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63 | static bool is_pch_edp(struct intel_dp *intel_dp) |
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64 | { |
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65 | return intel_dp->is_pch_edp; |
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66 | } |
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67 | |||
2342 | Serge | 68 | /** |
69 | * is_cpu_edp - is the port on the CPU and attached to an eDP panel? |
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70 | * @intel_dp: DP struct |
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71 | * |
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72 | * Returns true if the given DP struct corresponds to a CPU eDP port. |
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73 | */ |
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74 | static bool is_cpu_edp(struct intel_dp *intel_dp) |
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75 | { |
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76 | return is_edp(intel_dp) && !is_pch_edp(intel_dp); |
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77 | } |
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78 | |||
3243 | Serge | 79 | static struct drm_device *intel_dp_to_dev(struct intel_dp *intel_dp) |
2327 | Serge | 80 | { |
3243 | Serge | 81 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
82 | |||
83 | return intel_dig_port->base.base.dev; |
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2327 | Serge | 84 | } |
85 | |||
2330 | Serge | 86 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
87 | { |
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3243 | Serge | 88 | return enc_to_intel_dp(&intel_attached_encoder(connector)->base); |
2330 | Serge | 89 | } |
2327 | Serge | 90 | |
91 | /** |
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92 | * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? |
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93 | * @encoder: DRM encoder |
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94 | * |
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95 | * Return true if @encoder corresponds to a PCH attached eDP panel. Needed |
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96 | * by intel_display.c. |
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97 | */ |
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98 | bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) |
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99 | { |
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100 | struct intel_dp *intel_dp; |
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101 | |||
102 | if (!encoder) |
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103 | return false; |
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104 | |||
105 | intel_dp = enc_to_intel_dp(encoder); |
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106 | |||
107 | return is_pch_edp(intel_dp); |
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108 | } |
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109 | |||
2330 | Serge | 110 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
111 | |||
2327 | Serge | 112 | void |
2342 | Serge | 113 | intel_edp_link_config(struct intel_encoder *intel_encoder, |
2327 | Serge | 114 | int *lane_num, int *link_bw) |
115 | { |
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3243 | Serge | 116 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
2327 | Serge | 117 | |
118 | *lane_num = intel_dp->lane_count; |
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3243 | Serge | 119 | *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); |
2327 | Serge | 120 | } |
121 | |||
3031 | serge | 122 | int |
123 | intel_edp_target_clock(struct intel_encoder *intel_encoder, |
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124 | struct drm_display_mode *mode) |
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125 | { |
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3243 | Serge | 126 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
127 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
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3031 | serge | 128 | |
3243 | Serge | 129 | if (intel_connector->panel.fixed_mode) |
130 | return intel_connector->panel.fixed_mode->clock; |
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3031 | serge | 131 | else |
132 | return mode->clock; |
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133 | } |
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134 | |||
2330 | Serge | 135 | static int |
136 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
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137 | { |
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138 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
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2327 | Serge | 139 | |
2330 | Serge | 140 | switch (max_link_bw) { |
141 | case DP_LINK_BW_1_62: |
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142 | case DP_LINK_BW_2_7: |
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143 | break; |
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144 | default: |
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145 | max_link_bw = DP_LINK_BW_1_62; |
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146 | break; |
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147 | } |
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148 | return max_link_bw; |
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149 | } |
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2327 | Serge | 150 | |
2342 | Serge | 151 | /* |
152 | * The units on the numbers in the next two are... bizarre. Examples will |
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153 | * make it clearer; this one parallels an example in the eDP spec. |
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154 | * |
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155 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: |
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156 | * |
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157 | * 270000 * 1 * 8 / 10 == 216000 |
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158 | * |
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159 | * The actual data capacity of that configuration is 2.16Gbit/s, so the |
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160 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - |
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161 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be |
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162 | * 119000. At 18bpp that's 2142000 kilobits per second. |
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163 | * |
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164 | * Thus the strange-looking division by 10 in intel_dp_link_required, to |
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165 | * get the result in decakilobits instead of kilobits. |
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166 | */ |
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167 | |||
2330 | Serge | 168 | static int |
2351 | Serge | 169 | intel_dp_link_required(int pixel_clock, int bpp) |
2330 | Serge | 170 | { |
2342 | Serge | 171 | return (pixel_clock * bpp + 9) / 10; |
2330 | Serge | 172 | } |
2327 | Serge | 173 | |
2330 | Serge | 174 | static int |
175 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
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176 | { |
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177 | return (max_link_clock * max_lanes * 8) / 10; |
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178 | } |
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2327 | Serge | 179 | |
3031 | serge | 180 | static bool |
181 | intel_dp_adjust_dithering(struct intel_dp *intel_dp, |
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182 | struct drm_display_mode *mode, |
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183 | bool adjust_mode) |
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184 | { |
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3480 | Serge | 185 | int max_link_clock = |
186 | drm_dp_bw_code_to_link_rate(intel_dp_max_link_bw(intel_dp)); |
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3243 | Serge | 187 | int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); |
3031 | serge | 188 | int max_rate, mode_rate; |
189 | |||
190 | mode_rate = intel_dp_link_required(mode->clock, 24); |
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191 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
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192 | |||
193 | if (mode_rate > max_rate) { |
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194 | mode_rate = intel_dp_link_required(mode->clock, 18); |
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195 | if (mode_rate > max_rate) |
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196 | return false; |
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197 | |||
198 | if (adjust_mode) |
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199 | mode->private_flags |
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200 | |= INTEL_MODE_DP_FORCE_6BPC; |
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201 | |||
202 | return true; |
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203 | } |
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204 | |||
205 | return true; |
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206 | } |
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207 | |||
2330 | Serge | 208 | static int |
209 | intel_dp_mode_valid(struct drm_connector *connector, |
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210 | struct drm_display_mode *mode) |
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211 | { |
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212 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
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3243 | Serge | 213 | struct intel_connector *intel_connector = to_intel_connector(connector); |
214 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
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2327 | Serge | 215 | |
3243 | Serge | 216 | if (is_edp(intel_dp) && fixed_mode) { |
217 | if (mode->hdisplay > fixed_mode->hdisplay) |
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2330 | Serge | 218 | return MODE_PANEL; |
2327 | Serge | 219 | |
3243 | Serge | 220 | if (mode->vdisplay > fixed_mode->vdisplay) |
2330 | Serge | 221 | return MODE_PANEL; |
222 | } |
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2327 | Serge | 223 | |
3031 | serge | 224 | if (!intel_dp_adjust_dithering(intel_dp, mode, false)) |
2330 | Serge | 225 | return MODE_CLOCK_HIGH; |
2327 | Serge | 226 | |
2330 | Serge | 227 | if (mode->clock < 10000) |
228 | return MODE_CLOCK_LOW; |
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229 | |||
3031 | serge | 230 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
231 | return MODE_H_ILLEGAL; |
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232 | |||
2330 | Serge | 233 | return MODE_OK; |
234 | } |
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235 | |||
236 | static uint32_t |
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237 | pack_aux(uint8_t *src, int src_bytes) |
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238 | { |
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239 | int i; |
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240 | uint32_t v = 0; |
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241 | |||
242 | if (src_bytes > 4) |
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243 | src_bytes = 4; |
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244 | for (i = 0; i < src_bytes; i++) |
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245 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
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246 | return v; |
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247 | } |
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248 | |||
249 | static void |
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250 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
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251 | { |
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252 | int i; |
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253 | if (dst_bytes > 4) |
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254 | dst_bytes = 4; |
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255 | for (i = 0; i < dst_bytes; i++) |
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256 | dst[i] = src >> ((3-i) * 8); |
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257 | } |
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258 | |||
259 | /* hrawclock is 1/4 the FSB frequency */ |
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260 | static int |
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261 | intel_hrawclk(struct drm_device *dev) |
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262 | { |
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263 | struct drm_i915_private *dev_priv = dev->dev_private; |
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264 | uint32_t clkcfg; |
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265 | |||
3243 | Serge | 266 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
267 | if (IS_VALLEYVIEW(dev)) |
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268 | return 200; |
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269 | |||
2330 | Serge | 270 | clkcfg = I915_READ(CLKCFG); |
271 | switch (clkcfg & CLKCFG_FSB_MASK) { |
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272 | case CLKCFG_FSB_400: |
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273 | return 100; |
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274 | case CLKCFG_FSB_533: |
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275 | return 133; |
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276 | case CLKCFG_FSB_667: |
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277 | return 166; |
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278 | case CLKCFG_FSB_800: |
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279 | return 200; |
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280 | case CLKCFG_FSB_1067: |
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281 | return 266; |
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282 | case CLKCFG_FSB_1333: |
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283 | return 333; |
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284 | /* these two are just a guess; one of them might be right */ |
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285 | case CLKCFG_FSB_1600: |
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286 | case CLKCFG_FSB_1600_ALT: |
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287 | return 400; |
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288 | default: |
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289 | return 133; |
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290 | } |
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291 | } |
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292 | |||
2342 | Serge | 293 | static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) |
294 | { |
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3243 | Serge | 295 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2342 | Serge | 296 | struct drm_i915_private *dev_priv = dev->dev_private; |
297 | |||
298 | return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; |
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299 | } |
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300 | |||
301 | static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) |
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302 | { |
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3243 | Serge | 303 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2342 | Serge | 304 | struct drm_i915_private *dev_priv = dev->dev_private; |
305 | |||
306 | return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0; |
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307 | } |
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308 | |||
309 | static void |
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310 | intel_dp_check_edp(struct intel_dp *intel_dp) |
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311 | { |
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3243 | Serge | 312 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2342 | Serge | 313 | struct drm_i915_private *dev_priv = dev->dev_private; |
314 | |||
315 | if (!is_edp(intel_dp)) |
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316 | return; |
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317 | if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { |
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318 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
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319 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
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320 | I915_READ(PCH_PP_STATUS), |
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321 | I915_READ(PCH_PP_CONTROL)); |
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322 | } |
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323 | } |
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324 | |||
3480 | Serge | 325 | static uint32_t |
326 | intel_dp_aux_wait_done(struct intel_dp *intel_dp, bool has_aux_irq) |
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327 | { |
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328 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
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329 | struct drm_device *dev = intel_dig_port->base.base.dev; |
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330 | struct drm_i915_private *dev_priv = dev->dev_private; |
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331 | uint32_t ch_ctl = intel_dp->output_reg + 0x10; |
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332 | uint32_t status; |
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333 | bool done; |
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334 | |||
335 | if (IS_HASWELL(dev)) { |
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336 | switch (intel_dig_port->port) { |
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337 | case PORT_A: |
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338 | ch_ctl = DPA_AUX_CH_CTL; |
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339 | break; |
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340 | case PORT_B: |
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341 | ch_ctl = PCH_DPB_AUX_CH_CTL; |
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342 | break; |
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343 | case PORT_C: |
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344 | ch_ctl = PCH_DPC_AUX_CH_CTL; |
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345 | break; |
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346 | case PORT_D: |
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347 | ch_ctl = PCH_DPD_AUX_CH_CTL; |
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348 | break; |
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349 | default: |
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350 | BUG(); |
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351 | } |
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352 | } |
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353 | |||
354 | #define C (((status = I915_READ_NOTRACE(ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
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355 | if (has_aux_irq) |
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356 | done = wait_event_timeout(dev_priv->gmbus_wait_queue, C, |
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357 | msecs_to_jiffies(10)); |
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358 | else |
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359 | done = wait_for_atomic(C, 10) == 0; |
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360 | if (!done) |
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361 | DRM_ERROR("dp aux hw did not signal timeout (has irq: %i)!\n", |
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362 | has_aux_irq); |
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363 | #undef C |
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364 | |||
365 | return status; |
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366 | } |
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367 | |||
2330 | Serge | 368 | static int |
369 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
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370 | uint8_t *send, int send_bytes, |
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371 | uint8_t *recv, int recv_size) |
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372 | { |
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373 | uint32_t output_reg = intel_dp->output_reg; |
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3243 | Serge | 374 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
375 | struct drm_device *dev = intel_dig_port->base.base.dev; |
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2330 | Serge | 376 | struct drm_i915_private *dev_priv = dev->dev_private; |
377 | uint32_t ch_ctl = output_reg + 0x10; |
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378 | uint32_t ch_data = ch_ctl + 4; |
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3480 | Serge | 379 | int i, ret, recv_bytes; |
2330 | Serge | 380 | uint32_t status; |
381 | uint32_t aux_clock_divider; |
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382 | int try, precharge; |
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3480 | Serge | 383 | bool has_aux_irq = INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev); |
2330 | Serge | 384 | |
3480 | Serge | 385 | /* dp aux is extremely sensitive to irq latency, hence request the |
386 | * lowest possible wakeup latency and so prevent the cpu from going into |
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387 | * deep sleep states. |
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388 | */ |
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389 | // pm_qos_update_request(&dev_priv->pm_qos, 0); |
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390 | |||
3243 | Serge | 391 | if (IS_HASWELL(dev)) { |
392 | switch (intel_dig_port->port) { |
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393 | case PORT_A: |
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394 | ch_ctl = DPA_AUX_CH_CTL; |
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395 | ch_data = DPA_AUX_CH_DATA1; |
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396 | break; |
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397 | case PORT_B: |
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398 | ch_ctl = PCH_DPB_AUX_CH_CTL; |
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399 | ch_data = PCH_DPB_AUX_CH_DATA1; |
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400 | break; |
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401 | case PORT_C: |
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402 | ch_ctl = PCH_DPC_AUX_CH_CTL; |
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403 | ch_data = PCH_DPC_AUX_CH_DATA1; |
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404 | break; |
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405 | case PORT_D: |
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406 | ch_ctl = PCH_DPD_AUX_CH_CTL; |
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407 | ch_data = PCH_DPD_AUX_CH_DATA1; |
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408 | break; |
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409 | default: |
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410 | BUG(); |
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411 | } |
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412 | } |
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413 | |||
2342 | Serge | 414 | intel_dp_check_edp(intel_dp); |
2330 | Serge | 415 | /* The clock divider is based off the hrawclk, |
416 | * and would like to run at 2MHz. So, take the |
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417 | * hrawclk value and divide by 2 and use that |
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418 | * |
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419 | * Note that PCH attached eDP panels should use a 125MHz input |
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420 | * clock divider. |
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421 | */ |
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2342 | Serge | 422 | if (is_cpu_edp(intel_dp)) { |
3480 | Serge | 423 | if (HAS_DDI(dev)) |
3243 | Serge | 424 | aux_clock_divider = intel_ddi_get_cdclk_freq(dev_priv) >> 1; |
425 | else if (IS_VALLEYVIEW(dev)) |
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426 | aux_clock_divider = 100; |
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427 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
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2342 | Serge | 428 | aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ |
2330 | Serge | 429 | else |
430 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ |
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431 | } else if (HAS_PCH_SPLIT(dev)) |
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3243 | Serge | 432 | aux_clock_divider = DIV_ROUND_UP(intel_pch_rawclk(dev), 2); |
2330 | Serge | 433 | else |
434 | aux_clock_divider = intel_hrawclk(dev) / 2; |
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435 | |||
436 | if (IS_GEN6(dev)) |
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437 | precharge = 3; |
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438 | else |
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439 | precharge = 5; |
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440 | |||
441 | /* Try to wait for any previous AUX channel activity */ |
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442 | for (try = 0; try < 3; try++) { |
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3480 | Serge | 443 | status = I915_READ_NOTRACE(ch_ctl); |
2330 | Serge | 444 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
445 | break; |
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446 | msleep(1); |
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447 | } |
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448 | |||
449 | if (try == 3) { |
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450 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
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451 | I915_READ(ch_ctl)); |
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3480 | Serge | 452 | ret = -EBUSY; |
453 | goto out; |
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2330 | Serge | 454 | } |
455 | |||
456 | /* Must try at least 3 times according to DP spec */ |
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457 | for (try = 0; try < 5; try++) { |
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458 | /* Load the send data into the aux channel data registers */ |
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459 | for (i = 0; i < send_bytes; i += 4) |
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460 | I915_WRITE(ch_data + i, |
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461 | pack_aux(send + i, send_bytes - i)); |
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462 | |||
463 | /* Send the command and wait for it to complete */ |
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464 | I915_WRITE(ch_ctl, |
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465 | DP_AUX_CH_CTL_SEND_BUSY | |
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3480 | Serge | 466 | (has_aux_irq ? DP_AUX_CH_CTL_INTERRUPT : 0) | |
2330 | Serge | 467 | DP_AUX_CH_CTL_TIME_OUT_400us | |
468 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
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469 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
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470 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | |
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471 | DP_AUX_CH_CTL_DONE | |
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472 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
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473 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
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474 | |||
3480 | Serge | 475 | status = intel_dp_aux_wait_done(intel_dp, has_aux_irq); |
476 | |||
2330 | Serge | 477 | /* Clear done status and any errors */ |
478 | I915_WRITE(ch_ctl, |
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479 | status | |
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480 | DP_AUX_CH_CTL_DONE | |
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481 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
||
482 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
||
3031 | serge | 483 | |
484 | if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | |
||
485 | DP_AUX_CH_CTL_RECEIVE_ERROR)) |
||
486 | continue; |
||
2330 | Serge | 487 | if (status & DP_AUX_CH_CTL_DONE) |
488 | break; |
||
489 | } |
||
490 | |||
491 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
||
492 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
||
3480 | Serge | 493 | ret = -EBUSY; |
494 | goto out; |
||
2330 | Serge | 495 | } |
496 | |||
497 | /* Check for timeout or receive error. |
||
498 | * Timeouts occur when the sink is not connected |
||
499 | */ |
||
500 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
||
501 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
||
3480 | Serge | 502 | ret = -EIO; |
503 | goto out; |
||
2330 | Serge | 504 | } |
505 | |||
506 | /* Timeouts occur when the device isn't connected, so they're |
||
507 | * "normal" -- don't fill the kernel log with these */ |
||
508 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
||
509 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
||
3480 | Serge | 510 | ret = -ETIMEDOUT; |
511 | goto out; |
||
2330 | Serge | 512 | } |
513 | |||
514 | /* Unload any bytes sent back from the other side */ |
||
515 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
||
516 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
||
517 | if (recv_bytes > recv_size) |
||
518 | recv_bytes = recv_size; |
||
519 | |||
520 | for (i = 0; i < recv_bytes; i += 4) |
||
521 | unpack_aux(I915_READ(ch_data + i), |
||
522 | recv + i, recv_bytes - i); |
||
523 | |||
3480 | Serge | 524 | ret = recv_bytes; |
525 | out: |
||
526 | // pm_qos_update_request(&dev_priv->pm_qos, PM_QOS_DEFAULT_VALUE); |
||
527 | |||
528 | return ret; |
||
2330 | Serge | 529 | } |
530 | |||
531 | /* Write data to the aux channel in native mode */ |
||
532 | static int |
||
533 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
||
534 | uint16_t address, uint8_t *send, int send_bytes) |
||
535 | { |
||
536 | int ret; |
||
537 | uint8_t msg[20]; |
||
538 | int msg_bytes; |
||
539 | uint8_t ack; |
||
540 | |||
2342 | Serge | 541 | intel_dp_check_edp(intel_dp); |
2330 | Serge | 542 | if (send_bytes > 16) |
543 | return -1; |
||
544 | msg[0] = AUX_NATIVE_WRITE << 4; |
||
545 | msg[1] = address >> 8; |
||
546 | msg[2] = address & 0xff; |
||
547 | msg[3] = send_bytes - 1; |
||
548 | memcpy(&msg[4], send, send_bytes); |
||
549 | msg_bytes = send_bytes + 4; |
||
550 | for (;;) { |
||
551 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
||
552 | if (ret < 0) |
||
553 | return ret; |
||
554 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) |
||
555 | break; |
||
556 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
||
557 | udelay(100); |
||
558 | else |
||
559 | return -EIO; |
||
560 | } |
||
561 | return send_bytes; |
||
562 | } |
||
563 | |||
564 | /* Write a single byte to the aux channel in native mode */ |
||
565 | static int |
||
566 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
||
567 | uint16_t address, uint8_t byte) |
||
568 | { |
||
569 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
||
570 | } |
||
571 | |||
572 | /* read bytes from a native aux channel */ |
||
573 | static int |
||
574 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
||
575 | uint16_t address, uint8_t *recv, int recv_bytes) |
||
576 | { |
||
577 | uint8_t msg[4]; |
||
578 | int msg_bytes; |
||
579 | uint8_t reply[20]; |
||
580 | int reply_bytes; |
||
581 | uint8_t ack; |
||
582 | int ret; |
||
583 | |||
2342 | Serge | 584 | intel_dp_check_edp(intel_dp); |
2330 | Serge | 585 | msg[0] = AUX_NATIVE_READ << 4; |
586 | msg[1] = address >> 8; |
||
587 | msg[2] = address & 0xff; |
||
588 | msg[3] = recv_bytes - 1; |
||
589 | |||
590 | msg_bytes = 4; |
||
591 | reply_bytes = recv_bytes + 1; |
||
592 | |||
593 | for (;;) { |
||
594 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
||
595 | reply, reply_bytes); |
||
596 | if (ret == 0) |
||
597 | return -EPROTO; |
||
598 | if (ret < 0) |
||
599 | return ret; |
||
600 | ack = reply[0]; |
||
601 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { |
||
602 | memcpy(recv, reply + 1, ret - 1); |
||
603 | return ret - 1; |
||
604 | } |
||
605 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
||
606 | udelay(100); |
||
607 | else |
||
608 | return -EIO; |
||
609 | } |
||
610 | } |
||
611 | |||
612 | static int |
||
613 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
||
614 | uint8_t write_byte, uint8_t *read_byte) |
||
615 | { |
||
616 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
||
617 | struct intel_dp *intel_dp = container_of(adapter, |
||
618 | struct intel_dp, |
||
619 | adapter); |
||
620 | uint16_t address = algo_data->address; |
||
621 | uint8_t msg[5]; |
||
622 | uint8_t reply[2]; |
||
623 | unsigned retry; |
||
624 | int msg_bytes; |
||
625 | int reply_bytes; |
||
626 | int ret; |
||
627 | |||
2342 | Serge | 628 | intel_dp_check_edp(intel_dp); |
2330 | Serge | 629 | /* Set up the command byte */ |
630 | if (mode & MODE_I2C_READ) |
||
631 | msg[0] = AUX_I2C_READ << 4; |
||
632 | else |
||
633 | msg[0] = AUX_I2C_WRITE << 4; |
||
634 | |||
635 | if (!(mode & MODE_I2C_STOP)) |
||
636 | msg[0] |= AUX_I2C_MOT << 4; |
||
637 | |||
638 | msg[1] = address >> 8; |
||
639 | msg[2] = address; |
||
640 | |||
641 | switch (mode) { |
||
642 | case MODE_I2C_WRITE: |
||
643 | msg[3] = 0; |
||
644 | msg[4] = write_byte; |
||
645 | msg_bytes = 5; |
||
646 | reply_bytes = 1; |
||
647 | break; |
||
648 | case MODE_I2C_READ: |
||
649 | msg[3] = 0; |
||
650 | msg_bytes = 4; |
||
651 | reply_bytes = 2; |
||
652 | break; |
||
653 | default: |
||
654 | msg_bytes = 3; |
||
655 | reply_bytes = 1; |
||
656 | break; |
||
657 | } |
||
658 | |||
659 | for (retry = 0; retry < 5; retry++) { |
||
660 | ret = intel_dp_aux_ch(intel_dp, |
||
661 | msg, msg_bytes, |
||
662 | reply, reply_bytes); |
||
663 | if (ret < 0) { |
||
664 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
||
665 | return ret; |
||
666 | } |
||
667 | |||
668 | switch (reply[0] & AUX_NATIVE_REPLY_MASK) { |
||
669 | case AUX_NATIVE_REPLY_ACK: |
||
670 | /* I2C-over-AUX Reply field is only valid |
||
671 | * when paired with AUX ACK. |
||
672 | */ |
||
673 | break; |
||
674 | case AUX_NATIVE_REPLY_NACK: |
||
675 | DRM_DEBUG_KMS("aux_ch native nack\n"); |
||
676 | return -EREMOTEIO; |
||
677 | case AUX_NATIVE_REPLY_DEFER: |
||
678 | udelay(100); |
||
679 | continue; |
||
680 | default: |
||
681 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", |
||
682 | reply[0]); |
||
683 | return -EREMOTEIO; |
||
684 | } |
||
685 | |||
686 | switch (reply[0] & AUX_I2C_REPLY_MASK) { |
||
687 | case AUX_I2C_REPLY_ACK: |
||
688 | if (mode == MODE_I2C_READ) { |
||
689 | *read_byte = reply[1]; |
||
690 | } |
||
691 | return reply_bytes - 1; |
||
692 | case AUX_I2C_REPLY_NACK: |
||
693 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
||
694 | return -EREMOTEIO; |
||
695 | case AUX_I2C_REPLY_DEFER: |
||
696 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
||
697 | udelay(100); |
||
698 | break; |
||
699 | default: |
||
700 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
||
701 | return -EREMOTEIO; |
||
702 | } |
||
703 | } |
||
704 | |||
705 | DRM_ERROR("too many retries, giving up\n"); |
||
706 | return -EREMOTEIO; |
||
707 | } |
||
708 | |||
709 | static int |
||
710 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
||
711 | struct intel_connector *intel_connector, const char *name) |
||
712 | { |
||
2342 | Serge | 713 | int ret; |
714 | |||
2330 | Serge | 715 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
716 | intel_dp->algo.running = false; |
||
717 | intel_dp->algo.address = 0; |
||
718 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; |
||
719 | |||
2342 | Serge | 720 | memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); |
3031 | serge | 721 | intel_dp->adapter.owner = THIS_MODULE; |
2330 | Serge | 722 | intel_dp->adapter.class = I2C_CLASS_DDC; |
2342 | Serge | 723 | strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); |
2330 | Serge | 724 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; |
725 | intel_dp->adapter.algo_data = &intel_dp->algo; |
||
726 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; |
||
727 | |||
2342 | Serge | 728 | ironlake_edp_panel_vdd_on(intel_dp); |
729 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); |
||
730 | ironlake_edp_panel_vdd_off(intel_dp, false); |
||
731 | return ret; |
||
2330 | Serge | 732 | } |
733 | |||
3243 | Serge | 734 | bool |
3031 | serge | 735 | intel_dp_mode_fixup(struct drm_encoder *encoder, |
736 | const struct drm_display_mode *mode, |
||
2330 | Serge | 737 | struct drm_display_mode *adjusted_mode) |
738 | { |
||
739 | struct drm_device *dev = encoder->dev; |
||
740 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
||
3243 | Serge | 741 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
2330 | Serge | 742 | int lane_count, clock; |
3243 | Serge | 743 | int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); |
2330 | Serge | 744 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; |
3031 | serge | 745 | int bpp, mode_rate; |
2330 | Serge | 746 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
747 | |||
3243 | Serge | 748 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
749 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
||
750 | adjusted_mode); |
||
751 | intel_pch_panel_fitting(dev, |
||
752 | intel_connector->panel.fitting_mode, |
||
2330 | Serge | 753 | mode, adjusted_mode); |
754 | } |
||
755 | |||
3031 | serge | 756 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
757 | return false; |
||
758 | |||
759 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
||
760 | "max bw %02x pixel clock %iKHz\n", |
||
761 | max_lane_count, bws[max_clock], adjusted_mode->clock); |
||
762 | |||
763 | if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true)) |
||
764 | return false; |
||
765 | |||
766 | bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24; |
||
3480 | Serge | 767 | |
768 | if (intel_dp->color_range_auto) { |
||
769 | /* |
||
770 | * See: |
||
771 | * CEA-861-E - 5.1 Default Encoding Parameters |
||
772 | * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry |
||
773 | */ |
||
774 | if (bpp != 18 && drm_match_cea_mode(adjusted_mode) > 1) |
||
775 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
||
776 | else |
||
777 | intel_dp->color_range = 0; |
||
778 | } |
||
779 | |||
780 | if (intel_dp->color_range) |
||
781 | adjusted_mode->private_flags |= INTEL_MODE_LIMITED_COLOR_RANGE; |
||
782 | |||
3031 | serge | 783 | mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp); |
784 | |||
785 | for (clock = 0; clock <= max_clock; clock++) { |
||
2330 | Serge | 786 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
3480 | Serge | 787 | int link_bw_clock = |
788 | drm_dp_bw_code_to_link_rate(bws[clock]); |
||
789 | int link_avail = intel_dp_max_data_rate(link_bw_clock, |
||
790 | lane_count); |
||
2330 | Serge | 791 | |
3031 | serge | 792 | if (mode_rate <= link_avail) { |
2330 | Serge | 793 | intel_dp->link_bw = bws[clock]; |
794 | intel_dp->lane_count = lane_count; |
||
3480 | Serge | 795 | adjusted_mode->clock = link_bw_clock; |
3031 | serge | 796 | DRM_DEBUG_KMS("DP link bw %02x lane " |
797 | "count %d clock %d bpp %d\n", |
||
2330 | Serge | 798 | intel_dp->link_bw, intel_dp->lane_count, |
3031 | serge | 799 | adjusted_mode->clock, bpp); |
800 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
||
801 | mode_rate, link_avail); |
||
2330 | Serge | 802 | return true; |
803 | } |
||
804 | } |
||
805 | } |
||
806 | |||
807 | return false; |
||
808 | } |
||
809 | |||
2327 | Serge | 810 | void |
811 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, |
||
812 | struct drm_display_mode *adjusted_mode) |
||
813 | { |
||
814 | struct drm_device *dev = crtc->dev; |
||
3243 | Serge | 815 | struct intel_encoder *intel_encoder; |
816 | struct intel_dp *intel_dp; |
||
2327 | Serge | 817 | struct drm_i915_private *dev_priv = dev->dev_private; |
818 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
||
819 | int lane_count = 4; |
||
3480 | Serge | 820 | struct intel_link_m_n m_n; |
2327 | Serge | 821 | int pipe = intel_crtc->pipe; |
3243 | Serge | 822 | enum transcoder cpu_transcoder = intel_crtc->cpu_transcoder; |
3480 | Serge | 823 | int target_clock; |
2327 | Serge | 824 | |
825 | /* |
||
826 | * Find the lane count in the intel_encoder private |
||
827 | */ |
||
3243 | Serge | 828 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
829 | intel_dp = enc_to_intel_dp(&intel_encoder->base); |
||
2327 | Serge | 830 | |
3243 | Serge | 831 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
832 | intel_encoder->type == INTEL_OUTPUT_EDP) |
||
2342 | Serge | 833 | { |
2327 | Serge | 834 | lane_count = intel_dp->lane_count; |
835 | break; |
||
836 | } |
||
837 | } |
||
838 | |||
3480 | Serge | 839 | target_clock = mode->clock; |
840 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
||
841 | if (intel_encoder->type == INTEL_OUTPUT_EDP) { |
||
842 | target_clock = intel_edp_target_clock(intel_encoder, |
||
843 | mode); |
||
844 | break; |
||
845 | } |
||
846 | } |
||
847 | |||
2327 | Serge | 848 | /* |
849 | * Compute the GMCH and Link ratios. The '3' here is |
||
850 | * the number of bytes_per_pixel post-LUT, which we always |
||
851 | * set up for 8-bits of R/G/B, or 3 bytes total. |
||
852 | */ |
||
3480 | Serge | 853 | intel_link_compute_m_n(intel_crtc->bpp, lane_count, |
854 | target_clock, adjusted_mode->clock, &m_n); |
||
2327 | Serge | 855 | |
3243 | Serge | 856 | if (IS_HASWELL(dev)) { |
857 | I915_WRITE(PIPE_DATA_M1(cpu_transcoder), |
||
858 | TU_SIZE(m_n.tu) | m_n.gmch_m); |
||
859 | I915_WRITE(PIPE_DATA_N1(cpu_transcoder), m_n.gmch_n); |
||
860 | I915_WRITE(PIPE_LINK_M1(cpu_transcoder), m_n.link_m); |
||
861 | I915_WRITE(PIPE_LINK_N1(cpu_transcoder), m_n.link_n); |
||
862 | } else if (HAS_PCH_SPLIT(dev)) { |
||
863 | I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
||
2327 | Serge | 864 | I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); |
865 | I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); |
||
866 | I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); |
||
3243 | Serge | 867 | } else if (IS_VALLEYVIEW(dev)) { |
868 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
||
869 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); |
||
870 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); |
||
871 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); |
||
2327 | Serge | 872 | } else { |
873 | I915_WRITE(PIPE_GMCH_DATA_M(pipe), |
||
3243 | Serge | 874 | TU_SIZE(m_n.tu) | m_n.gmch_m); |
2327 | Serge | 875 | I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); |
876 | I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); |
||
877 | I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); |
||
878 | } |
||
879 | } |
||
880 | |||
3243 | Serge | 881 | void intel_dp_init_link_config(struct intel_dp *intel_dp) |
882 | { |
||
883 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
||
884 | intel_dp->link_configuration[0] = intel_dp->link_bw; |
||
885 | intel_dp->link_configuration[1] = intel_dp->lane_count; |
||
886 | intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; |
||
887 | /* |
||
888 | * Check for DPCD version > 1.1 and enhanced framing support |
||
889 | */ |
||
890 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
||
891 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { |
||
892 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
||
893 | } |
||
894 | } |
||
895 | |||
3480 | Serge | 896 | static void ironlake_set_pll_edp(struct drm_crtc *crtc, int clock) |
897 | { |
||
898 | struct drm_device *dev = crtc->dev; |
||
899 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
900 | u32 dpa_ctl; |
||
901 | |||
902 | DRM_DEBUG_KMS("eDP PLL enable for clock %d\n", clock); |
||
903 | dpa_ctl = I915_READ(DP_A); |
||
904 | dpa_ctl &= ~DP_PLL_FREQ_MASK; |
||
905 | |||
906 | if (clock < 200000) { |
||
907 | /* For a long time we've carried around a ILK-DevA w/a for the |
||
908 | * 160MHz clock. If we're really unlucky, it's still required. |
||
909 | */ |
||
910 | DRM_DEBUG_KMS("160MHz cpu eDP clock, might need ilk devA w/a\n"); |
||
911 | dpa_ctl |= DP_PLL_FREQ_160MHZ; |
||
912 | } else { |
||
913 | dpa_ctl |= DP_PLL_FREQ_270MHZ; |
||
914 | } |
||
915 | |||
916 | I915_WRITE(DP_A, dpa_ctl); |
||
917 | |||
918 | POSTING_READ(DP_A); |
||
919 | udelay(500); |
||
920 | } |
||
921 | |||
2330 | Serge | 922 | static void |
923 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
||
924 | struct drm_display_mode *adjusted_mode) |
||
925 | { |
||
926 | struct drm_device *dev = encoder->dev; |
||
2342 | Serge | 927 | struct drm_i915_private *dev_priv = dev->dev_private; |
2330 | Serge | 928 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
3243 | Serge | 929 | struct drm_crtc *crtc = encoder->crtc; |
2330 | Serge | 930 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2327 | Serge | 931 | |
2342 | Serge | 932 | /* |
933 | * There are four kinds of DP registers: |
||
934 | * |
||
935 | * IBX PCH |
||
936 | * SNB CPU |
||
937 | * IVB CPU |
||
938 | * CPT PCH |
||
939 | * |
||
940 | * IBX PCH and CPU are the same for almost everything, |
||
941 | * except that the CPU DP PLL is configured in this |
||
942 | * register |
||
943 | * |
||
944 | * CPT PCH is quite different, having many bits moved |
||
945 | * to the TRANS_DP_CTL register instead. That |
||
946 | * configuration happens (oddly) in ironlake_pch_enable |
||
947 | */ |
||
2327 | Serge | 948 | |
2342 | Serge | 949 | /* Preserve the BIOS-computed detected bit. This is |
950 | * supposed to be read-only. |
||
951 | */ |
||
952 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
||
2327 | Serge | 953 | |
2342 | Serge | 954 | /* Handle DP bits in common between all three register formats */ |
955 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
||
956 | |||
2330 | Serge | 957 | switch (intel_dp->lane_count) { |
958 | case 1: |
||
959 | intel_dp->DP |= DP_PORT_WIDTH_1; |
||
960 | break; |
||
961 | case 2: |
||
962 | intel_dp->DP |= DP_PORT_WIDTH_2; |
||
963 | break; |
||
964 | case 4: |
||
965 | intel_dp->DP |= DP_PORT_WIDTH_4; |
||
966 | break; |
||
967 | } |
||
2342 | Serge | 968 | if (intel_dp->has_audio) { |
969 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
||
970 | pipe_name(intel_crtc->pipe)); |
||
2330 | Serge | 971 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
2342 | Serge | 972 | intel_write_eld(encoder, adjusted_mode); |
973 | } |
||
2327 | Serge | 974 | |
3243 | Serge | 975 | intel_dp_init_link_config(intel_dp); |
976 | |||
2342 | Serge | 977 | /* Split out the IBX/CPU vs CPT settings */ |
978 | |||
3243 | Serge | 979 | if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
2342 | Serge | 980 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
981 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
||
982 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
||
983 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
||
984 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
||
985 | |||
986 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) |
||
987 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
||
988 | |||
989 | intel_dp->DP |= intel_crtc->pipe << 29; |
||
990 | |||
991 | /* don't miss out required setting for eDP */ |
||
992 | if (adjusted_mode->clock < 200000) |
||
993 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
||
994 | else |
||
995 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
||
996 | } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { |
||
3480 | Serge | 997 | if (!HAS_PCH_SPLIT(dev)) |
2342 | Serge | 998 | intel_dp->DP |= intel_dp->color_range; |
999 | |||
1000 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
||
1001 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
||
1002 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
||
1003 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
||
1004 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
||
1005 | |||
1006 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) |
||
1007 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
||
1008 | |||
1009 | if (intel_crtc->pipe == 1) |
||
2330 | Serge | 1010 | intel_dp->DP |= DP_PIPEB_SELECT; |
2327 | Serge | 1011 | |
2342 | Serge | 1012 | if (is_cpu_edp(intel_dp)) { |
2330 | Serge | 1013 | /* don't miss out required setting for eDP */ |
1014 | if (adjusted_mode->clock < 200000) |
||
1015 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
||
1016 | else |
||
1017 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
||
1018 | } |
||
2342 | Serge | 1019 | } else { |
1020 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
||
1021 | } |
||
3480 | Serge | 1022 | |
1023 | if (is_cpu_edp(intel_dp)) |
||
1024 | ironlake_set_pll_edp(crtc, adjusted_mode->clock); |
||
2330 | Serge | 1025 | } |
2327 | Serge | 1026 | |
2342 | Serge | 1027 | #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
1028 | #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
||
1029 | |||
1030 | #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
||
1031 | #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
||
1032 | |||
1033 | #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
||
1034 | #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
||
1035 | |||
1036 | static void ironlake_wait_panel_status(struct intel_dp *intel_dp, |
||
1037 | u32 mask, |
||
1038 | u32 value) |
||
1039 | { |
||
3243 | Serge | 1040 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2342 | Serge | 1041 | struct drm_i915_private *dev_priv = dev->dev_private; |
1042 | |||
1043 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
||
1044 | mask, value, |
||
1045 | I915_READ(PCH_PP_STATUS), |
||
1046 | I915_READ(PCH_PP_CONTROL)); |
||
1047 | |||
1048 | if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) { |
||
1049 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
||
1050 | I915_READ(PCH_PP_STATUS), |
||
1051 | I915_READ(PCH_PP_CONTROL)); |
||
1052 | } |
||
1053 | } |
||
1054 | |||
1055 | static void ironlake_wait_panel_on(struct intel_dp *intel_dp) |
||
1056 | { |
||
1057 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
||
1058 | ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
||
1059 | } |
||
1060 | |||
1061 | static void ironlake_wait_panel_off(struct intel_dp *intel_dp) |
||
1062 | { |
||
1063 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
||
1064 | ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
||
1065 | } |
||
1066 | |||
1067 | static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp) |
||
1068 | { |
||
1069 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
||
1070 | ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
||
1071 | } |
||
1072 | |||
1073 | |||
1074 | /* Read the current pp_control value, unlocking the register if it |
||
1075 | * is locked |
||
1076 | */ |
||
1077 | |||
1078 | static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv) |
||
1079 | { |
||
1080 | u32 control = I915_READ(PCH_PP_CONTROL); |
||
1081 | |||
1082 | control &= ~PANEL_UNLOCK_MASK; |
||
1083 | control |= PANEL_UNLOCK_REGS; |
||
1084 | return control; |
||
1085 | } |
||
1086 | |||
3243 | Serge | 1087 | void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
2330 | Serge | 1088 | { |
3243 | Serge | 1089 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2330 | Serge | 1090 | struct drm_i915_private *dev_priv = dev->dev_private; |
1091 | u32 pp; |
||
2327 | Serge | 1092 | |
2342 | Serge | 1093 | if (!is_edp(intel_dp)) |
1094 | return; |
||
1095 | DRM_DEBUG_KMS("Turn eDP VDD on\n"); |
||
2327 | Serge | 1096 | |
2342 | Serge | 1097 | WARN(intel_dp->want_panel_vdd, |
1098 | "eDP VDD already requested on\n"); |
||
1099 | |||
1100 | intel_dp->want_panel_vdd = true; |
||
1101 | |||
1102 | if (ironlake_edp_have_panel_vdd(intel_dp)) { |
||
1103 | DRM_DEBUG_KMS("eDP VDD already on\n"); |
||
1104 | return; |
||
1105 | } |
||
1106 | |||
1107 | if (!ironlake_edp_have_panel_power(intel_dp)) |
||
1108 | ironlake_wait_panel_power_cycle(intel_dp); |
||
1109 | |||
1110 | pp = ironlake_get_pp_control(dev_priv); |
||
2330 | Serge | 1111 | pp |= EDP_FORCE_VDD; |
1112 | I915_WRITE(PCH_PP_CONTROL, pp); |
||
1113 | POSTING_READ(PCH_PP_CONTROL); |
||
2342 | Serge | 1114 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", |
1115 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); |
||
1116 | |||
1117 | /* |
||
1118 | * If the panel wasn't on, delay before accessing aux channel |
||
1119 | */ |
||
1120 | if (!ironlake_edp_have_panel_power(intel_dp)) { |
||
1121 | DRM_DEBUG_KMS("eDP was not running\n"); |
||
1122 | msleep(intel_dp->panel_power_up_delay); |
||
1123 | } |
||
2330 | Serge | 1124 | } |
2327 | Serge | 1125 | |
2342 | Serge | 1126 | static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) |
2330 | Serge | 1127 | { |
3243 | Serge | 1128 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2330 | Serge | 1129 | struct drm_i915_private *dev_priv = dev->dev_private; |
1130 | u32 pp; |
||
2327 | Serge | 1131 | |
3480 | Serge | 1132 | WARN_ON(!mutex_is_locked(&dev->mode_config.mutex)); |
1133 | |||
2342 | Serge | 1134 | if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { |
1135 | pp = ironlake_get_pp_control(dev_priv); |
||
2330 | Serge | 1136 | pp &= ~EDP_FORCE_VDD; |
1137 | I915_WRITE(PCH_PP_CONTROL, pp); |
||
1138 | POSTING_READ(PCH_PP_CONTROL); |
||
2327 | Serge | 1139 | |
2330 | Serge | 1140 | /* Make sure sequencer is idle before allowing subsequent activity */ |
2342 | Serge | 1141 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", |
1142 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); |
||
1143 | |||
1144 | msleep(intel_dp->panel_power_down_delay); |
||
1145 | } |
||
2330 | Serge | 1146 | } |
2327 | Serge | 1147 | |
3243 | Serge | 1148 | static void ironlake_panel_vdd_work(struct work_struct *__work) |
1149 | { |
||
1150 | // struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
||
1151 | // struct intel_dp, panel_vdd_work); |
||
1152 | // struct drm_device *dev = intel_dp_to_dev(intel_dp); |
||
1153 | // |
||
1154 | // mutex_lock(&dev->mode_config.mutex); |
||
1155 | // ironlake_panel_vdd_off_sync(intel_dp); |
||
1156 | // mutex_unlock(&dev->mode_config.mutex); |
||
1157 | } |
||
2342 | Serge | 1158 | |
3243 | Serge | 1159 | void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
2330 | Serge | 1160 | { |
2342 | Serge | 1161 | if (!is_edp(intel_dp)) |
1162 | return; |
||
1163 | |||
1164 | DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd); |
||
1165 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); |
||
1166 | |||
1167 | intel_dp->want_panel_vdd = false; |
||
1168 | |||
1169 | if (sync) { |
||
1170 | ironlake_panel_vdd_off_sync(intel_dp); |
||
1171 | } else { |
||
1172 | /* |
||
1173 | * Queue the timer to fire a long |
||
1174 | * time from now (relative to the power down delay) |
||
1175 | * to keep the panel power up across a sequence of operations |
||
1176 | */ |
||
1177 | // schedule_delayed_work(&intel_dp->panel_vdd_work, |
||
1178 | // msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); |
||
1179 | } |
||
1180 | } |
||
1181 | |||
3243 | Serge | 1182 | void ironlake_edp_panel_on(struct intel_dp *intel_dp) |
2342 | Serge | 1183 | { |
3243 | Serge | 1184 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2330 | Serge | 1185 | struct drm_i915_private *dev_priv = dev->dev_private; |
2342 | Serge | 1186 | u32 pp; |
2327 | Serge | 1187 | |
2342 | Serge | 1188 | if (!is_edp(intel_dp)) |
1189 | return; |
||
2327 | Serge | 1190 | |
2342 | Serge | 1191 | DRM_DEBUG_KMS("Turn eDP power on\n"); |
2327 | Serge | 1192 | |
2342 | Serge | 1193 | if (ironlake_edp_have_panel_power(intel_dp)) { |
1194 | DRM_DEBUG_KMS("eDP power already on\n"); |
||
1195 | return; |
||
1196 | } |
||
1197 | |||
1198 | ironlake_wait_panel_power_cycle(intel_dp); |
||
1199 | |||
1200 | pp = ironlake_get_pp_control(dev_priv); |
||
1201 | if (IS_GEN5(dev)) { |
||
2330 | Serge | 1202 | /* ILK workaround: disable reset around power sequence */ |
1203 | pp &= ~PANEL_POWER_RESET; |
||
1204 | I915_WRITE(PCH_PP_CONTROL, pp); |
||
1205 | POSTING_READ(PCH_PP_CONTROL); |
||
2342 | Serge | 1206 | } |
2327 | Serge | 1207 | |
2342 | Serge | 1208 | pp |= POWER_TARGET_ON; |
1209 | if (!IS_GEN5(dev)) |
||
1210 | pp |= PANEL_POWER_RESET; |
||
1211 | |||
2330 | Serge | 1212 | I915_WRITE(PCH_PP_CONTROL, pp); |
1213 | POSTING_READ(PCH_PP_CONTROL); |
||
2327 | Serge | 1214 | |
2342 | Serge | 1215 | ironlake_wait_panel_on(intel_dp); |
2327 | Serge | 1216 | |
2342 | Serge | 1217 | if (IS_GEN5(dev)) { |
2330 | Serge | 1218 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
1219 | I915_WRITE(PCH_PP_CONTROL, pp); |
||
1220 | POSTING_READ(PCH_PP_CONTROL); |
||
2342 | Serge | 1221 | } |
2330 | Serge | 1222 | } |
2327 | Serge | 1223 | |
3243 | Serge | 1224 | void ironlake_edp_panel_off(struct intel_dp *intel_dp) |
2330 | Serge | 1225 | { |
3243 | Serge | 1226 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2330 | Serge | 1227 | struct drm_i915_private *dev_priv = dev->dev_private; |
2342 | Serge | 1228 | u32 pp; |
2327 | Serge | 1229 | |
2342 | Serge | 1230 | if (!is_edp(intel_dp)) |
1231 | return; |
||
2327 | Serge | 1232 | |
2342 | Serge | 1233 | DRM_DEBUG_KMS("Turn eDP power off\n"); |
2327 | Serge | 1234 | |
3031 | serge | 1235 | WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); |
2342 | Serge | 1236 | |
1237 | pp = ironlake_get_pp_control(dev_priv); |
||
3031 | serge | 1238 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
1239 | * panels get very unhappy and cease to work. */ |
||
2342 | Serge | 1240 | pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE); |
2330 | Serge | 1241 | I915_WRITE(PCH_PP_CONTROL, pp); |
1242 | POSTING_READ(PCH_PP_CONTROL); |
||
2327 | Serge | 1243 | |
3031 | serge | 1244 | intel_dp->want_panel_vdd = false; |
1245 | |||
2342 | Serge | 1246 | ironlake_wait_panel_off(intel_dp); |
2330 | Serge | 1247 | } |
2327 | Serge | 1248 | |
3243 | Serge | 1249 | void ironlake_edp_backlight_on(struct intel_dp *intel_dp) |
2330 | Serge | 1250 | { |
3243 | Serge | 1251 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1252 | struct drm_device *dev = intel_dig_port->base.base.dev; |
||
2330 | Serge | 1253 | struct drm_i915_private *dev_priv = dev->dev_private; |
3243 | Serge | 1254 | int pipe = to_intel_crtc(intel_dig_port->base.base.crtc)->pipe; |
2330 | Serge | 1255 | u32 pp; |
2327 | Serge | 1256 | |
2342 | Serge | 1257 | if (!is_edp(intel_dp)) |
1258 | return; |
||
1259 | |||
2330 | Serge | 1260 | DRM_DEBUG_KMS("\n"); |
1261 | /* |
||
1262 | * If we enable the backlight right away following a panel power |
||
1263 | * on, we may see slight flicker as the panel syncs with the eDP |
||
1264 | * link. So delay a bit to make sure the image is solid before |
||
1265 | * allowing it to appear. |
||
1266 | */ |
||
2342 | Serge | 1267 | msleep(intel_dp->backlight_on_delay); |
1268 | pp = ironlake_get_pp_control(dev_priv); |
||
2330 | Serge | 1269 | pp |= EDP_BLC_ENABLE; |
1270 | I915_WRITE(PCH_PP_CONTROL, pp); |
||
2342 | Serge | 1271 | POSTING_READ(PCH_PP_CONTROL); |
3243 | Serge | 1272 | |
1273 | intel_panel_enable_backlight(dev, pipe); |
||
2330 | Serge | 1274 | } |
2327 | Serge | 1275 | |
3243 | Serge | 1276 | void ironlake_edp_backlight_off(struct intel_dp *intel_dp) |
2330 | Serge | 1277 | { |
3243 | Serge | 1278 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2330 | Serge | 1279 | struct drm_i915_private *dev_priv = dev->dev_private; |
1280 | u32 pp; |
||
2327 | Serge | 1281 | |
2342 | Serge | 1282 | if (!is_edp(intel_dp)) |
1283 | return; |
||
1284 | |||
3243 | Serge | 1285 | intel_panel_disable_backlight(dev); |
1286 | |||
2330 | Serge | 1287 | DRM_DEBUG_KMS("\n"); |
2342 | Serge | 1288 | pp = ironlake_get_pp_control(dev_priv); |
2330 | Serge | 1289 | pp &= ~EDP_BLC_ENABLE; |
1290 | I915_WRITE(PCH_PP_CONTROL, pp); |
||
2342 | Serge | 1291 | POSTING_READ(PCH_PP_CONTROL); |
1292 | msleep(intel_dp->backlight_off_delay); |
||
2330 | Serge | 1293 | } |
2327 | Serge | 1294 | |
3031 | serge | 1295 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
2330 | Serge | 1296 | { |
3243 | Serge | 1297 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1298 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
||
1299 | struct drm_device *dev = crtc->dev; |
||
2330 | Serge | 1300 | struct drm_i915_private *dev_priv = dev->dev_private; |
1301 | u32 dpa_ctl; |
||
2327 | Serge | 1302 | |
3031 | serge | 1303 | assert_pipe_disabled(dev_priv, |
1304 | to_intel_crtc(crtc)->pipe); |
||
1305 | |||
2330 | Serge | 1306 | DRM_DEBUG_KMS("\n"); |
1307 | dpa_ctl = I915_READ(DP_A); |
||
3031 | serge | 1308 | WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); |
1309 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
||
1310 | |||
1311 | /* We don't adjust intel_dp->DP while tearing down the link, to |
||
1312 | * facilitate link retraining (e.g. after hotplug). Hence clear all |
||
1313 | * enable bits here to ensure that we don't enable too much. */ |
||
1314 | intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
||
1315 | intel_dp->DP |= DP_PLL_ENABLE; |
||
1316 | I915_WRITE(DP_A, intel_dp->DP); |
||
2330 | Serge | 1317 | POSTING_READ(DP_A); |
1318 | udelay(200); |
||
1319 | } |
||
2327 | Serge | 1320 | |
3031 | serge | 1321 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
2330 | Serge | 1322 | { |
3243 | Serge | 1323 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1324 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
||
1325 | struct drm_device *dev = crtc->dev; |
||
2330 | Serge | 1326 | struct drm_i915_private *dev_priv = dev->dev_private; |
1327 | u32 dpa_ctl; |
||
2327 | Serge | 1328 | |
3031 | serge | 1329 | assert_pipe_disabled(dev_priv, |
1330 | to_intel_crtc(crtc)->pipe); |
||
1331 | |||
2330 | Serge | 1332 | dpa_ctl = I915_READ(DP_A); |
3031 | serge | 1333 | WARN((dpa_ctl & DP_PLL_ENABLE) == 0, |
1334 | "dp pll off, should be on\n"); |
||
1335 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
||
1336 | |||
1337 | /* We can't rely on the value tracked for the DP register in |
||
1338 | * intel_dp->DP because link_down must not change that (otherwise link |
||
1339 | * re-training will fail. */ |
||
2330 | Serge | 1340 | dpa_ctl &= ~DP_PLL_ENABLE; |
1341 | I915_WRITE(DP_A, dpa_ctl); |
||
1342 | POSTING_READ(DP_A); |
||
1343 | udelay(200); |
||
1344 | } |
||
2327 | Serge | 1345 | |
2330 | Serge | 1346 | /* If the sink supports it, try to set the power state appropriately */ |
3243 | Serge | 1347 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
2330 | Serge | 1348 | { |
1349 | int ret, i; |
||
2327 | Serge | 1350 | |
2330 | Serge | 1351 | /* Should have a valid DPCD by this point */ |
1352 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
||
1353 | return; |
||
2327 | Serge | 1354 | |
2330 | Serge | 1355 | if (mode != DRM_MODE_DPMS_ON) { |
1356 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, |
||
1357 | DP_SET_POWER_D3); |
||
1358 | if (ret != 1) |
||
1359 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); |
||
1360 | } else { |
||
1361 | /* |
||
1362 | * When turning on, we need to retry for 1ms to give the sink |
||
1363 | * time to wake up. |
||
1364 | */ |
||
1365 | for (i = 0; i < 3; i++) { |
||
1366 | ret = intel_dp_aux_native_write_1(intel_dp, |
||
1367 | DP_SET_POWER, |
||
1368 | DP_SET_POWER_D0); |
||
1369 | if (ret == 1) |
||
1370 | break; |
||
1371 | msleep(1); |
||
1372 | } |
||
1373 | } |
||
1374 | } |
||
2327 | Serge | 1375 | |
3031 | serge | 1376 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
1377 | enum pipe *pipe) |
||
2330 | Serge | 1378 | { |
3031 | serge | 1379 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1380 | struct drm_device *dev = encoder->base.dev; |
||
1381 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
1382 | u32 tmp = I915_READ(intel_dp->output_reg); |
||
2327 | Serge | 1383 | |
3031 | serge | 1384 | if (!(tmp & DP_PORT_EN)) |
1385 | return false; |
||
2342 | Serge | 1386 | |
3031 | serge | 1387 | if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) { |
1388 | *pipe = PORT_TO_PIPE_CPT(tmp); |
||
1389 | } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { |
||
1390 | *pipe = PORT_TO_PIPE(tmp); |
||
1391 | } else { |
||
1392 | u32 trans_sel; |
||
1393 | u32 trans_dp; |
||
1394 | int i; |
||
2327 | Serge | 1395 | |
3031 | serge | 1396 | switch (intel_dp->output_reg) { |
1397 | case PCH_DP_B: |
||
1398 | trans_sel = TRANS_DP_PORT_SEL_B; |
||
1399 | break; |
||
1400 | case PCH_DP_C: |
||
1401 | trans_sel = TRANS_DP_PORT_SEL_C; |
||
1402 | break; |
||
1403 | case PCH_DP_D: |
||
1404 | trans_sel = TRANS_DP_PORT_SEL_D; |
||
1405 | break; |
||
1406 | default: |
||
1407 | return true; |
||
1408 | } |
||
1409 | |||
1410 | for_each_pipe(i) { |
||
1411 | trans_dp = I915_READ(TRANS_DP_CTL(i)); |
||
1412 | if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { |
||
1413 | *pipe = i; |
||
1414 | return true; |
||
1415 | } |
||
1416 | } |
||
3243 | Serge | 1417 | |
1418 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", |
||
1419 | intel_dp->output_reg); |
||
3031 | serge | 1420 | } |
1421 | |||
1422 | return true; |
||
2330 | Serge | 1423 | } |
2327 | Serge | 1424 | |
3031 | serge | 1425 | static void intel_disable_dp(struct intel_encoder *encoder) |
2330 | Serge | 1426 | { |
3031 | serge | 1427 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
2327 | Serge | 1428 | |
3031 | serge | 1429 | /* Make sure the panel is off before trying to change the mode. But also |
1430 | * ensure that we have vdd while we switch off the panel. */ |
||
2330 | Serge | 1431 | ironlake_edp_panel_vdd_on(intel_dp); |
3031 | serge | 1432 | ironlake_edp_backlight_off(intel_dp); |
2342 | Serge | 1433 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
3031 | serge | 1434 | ironlake_edp_panel_off(intel_dp); |
2330 | Serge | 1435 | |
3031 | serge | 1436 | /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ |
1437 | if (!is_cpu_edp(intel_dp)) |
||
1438 | intel_dp_link_down(intel_dp); |
||
1439 | } |
||
2330 | Serge | 1440 | |
3031 | serge | 1441 | static void intel_post_disable_dp(struct intel_encoder *encoder) |
1442 | { |
||
1443 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
||
1444 | |||
1445 | if (is_cpu_edp(intel_dp)) { |
||
1446 | intel_dp_link_down(intel_dp); |
||
1447 | ironlake_edp_pll_off(intel_dp); |
||
1448 | } |
||
2330 | Serge | 1449 | } |
1450 | |||
3031 | serge | 1451 | static void intel_enable_dp(struct intel_encoder *encoder) |
2330 | Serge | 1452 | { |
3031 | serge | 1453 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
1454 | struct drm_device *dev = encoder->base.dev; |
||
2330 | Serge | 1455 | struct drm_i915_private *dev_priv = dev->dev_private; |
1456 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
||
1457 | |||
3031 | serge | 1458 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
1459 | return; |
||
2342 | Serge | 1460 | |
1461 | ironlake_edp_panel_vdd_on(intel_dp); |
||
3031 | serge | 1462 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
2330 | Serge | 1463 | intel_dp_start_link_train(intel_dp); |
1464 | ironlake_edp_panel_on(intel_dp); |
||
2342 | Serge | 1465 | ironlake_edp_panel_vdd_off(intel_dp, true); |
2330 | Serge | 1466 | intel_dp_complete_link_train(intel_dp); |
2342 | Serge | 1467 | ironlake_edp_backlight_on(intel_dp); |
2330 | Serge | 1468 | } |
1469 | |||
3031 | serge | 1470 | static void intel_pre_enable_dp(struct intel_encoder *encoder) |
1471 | { |
||
1472 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
||
1473 | |||
1474 | if (is_cpu_edp(intel_dp)) |
||
1475 | ironlake_edp_pll_on(intel_dp); |
||
1476 | } |
||
1477 | |||
2330 | Serge | 1478 | /* |
1479 | * Native read with retry for link status and receiver capability reads for |
||
1480 | * cases where the sink may still be asleep. |
||
1481 | */ |
||
1482 | static bool |
||
1483 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
||
1484 | uint8_t *recv, int recv_bytes) |
||
1485 | { |
||
1486 | int ret, i; |
||
1487 | |||
1488 | /* |
||
1489 | * Sinks are *supposed* to come up within 1ms from an off state, |
||
1490 | * but we're also supposed to retry 3 times per the spec. |
||
1491 | */ |
||
1492 | for (i = 0; i < 3; i++) { |
||
1493 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
||
1494 | recv_bytes); |
||
1495 | if (ret == recv_bytes) |
||
1496 | return true; |
||
1497 | msleep(1); |
||
1498 | } |
||
1499 | |||
1500 | return false; |
||
1501 | } |
||
1502 | |||
1503 | /* |
||
1504 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
||
1505 | * link status information |
||
1506 | */ |
||
1507 | static bool |
||
2342 | Serge | 1508 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
2330 | Serge | 1509 | { |
1510 | return intel_dp_aux_native_read_retry(intel_dp, |
||
1511 | DP_LANE0_1_STATUS, |
||
2342 | Serge | 1512 | link_status, |
2330 | Serge | 1513 | DP_LINK_STATUS_SIZE); |
1514 | } |
||
1515 | |||
1516 | #if 0 |
||
1517 | static char *voltage_names[] = { |
||
1518 | "0.4V", "0.6V", "0.8V", "1.2V" |
||
1519 | }; |
||
1520 | static char *pre_emph_names[] = { |
||
1521 | "0dB", "3.5dB", "6dB", "9.5dB" |
||
1522 | }; |
||
1523 | static char *link_train_names[] = { |
||
1524 | "pattern 1", "pattern 2", "idle", "off" |
||
1525 | }; |
||
1526 | #endif |
||
1527 | |||
1528 | /* |
||
1529 | * These are source-specific values; current Intel hardware supports |
||
1530 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB |
||
1531 | */ |
||
1532 | |||
1533 | static uint8_t |
||
2342 | Serge | 1534 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
2330 | Serge | 1535 | { |
3243 | Serge | 1536 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2342 | Serge | 1537 | |
1538 | if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) |
||
1539 | return DP_TRAIN_VOLTAGE_SWING_800; |
||
1540 | else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
||
1541 | return DP_TRAIN_VOLTAGE_SWING_1200; |
||
1542 | else |
||
1543 | return DP_TRAIN_VOLTAGE_SWING_800; |
||
1544 | } |
||
1545 | |||
1546 | static uint8_t |
||
1547 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
||
1548 | { |
||
3243 | Serge | 1549 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2342 | Serge | 1550 | |
3243 | Serge | 1551 | if (IS_HASWELL(dev)) { |
2342 | Serge | 1552 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
1553 | case DP_TRAIN_VOLTAGE_SWING_400: |
||
3243 | Serge | 1554 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
1555 | case DP_TRAIN_VOLTAGE_SWING_600: |
||
2342 | Serge | 1556 | return DP_TRAIN_PRE_EMPHASIS_6; |
3243 | Serge | 1557 | case DP_TRAIN_VOLTAGE_SWING_800: |
1558 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
||
1559 | case DP_TRAIN_VOLTAGE_SWING_1200: |
||
1560 | default: |
||
1561 | return DP_TRAIN_PRE_EMPHASIS_0; |
||
1562 | } |
||
1563 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { |
||
1564 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
||
1565 | case DP_TRAIN_VOLTAGE_SWING_400: |
||
1566 | return DP_TRAIN_PRE_EMPHASIS_6; |
||
2342 | Serge | 1567 | case DP_TRAIN_VOLTAGE_SWING_600: |
1568 | case DP_TRAIN_VOLTAGE_SWING_800: |
||
1569 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
||
1570 | default: |
||
1571 | return DP_TRAIN_PRE_EMPHASIS_0; |
||
1572 | } |
||
1573 | } else { |
||
2330 | Serge | 1574 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
1575 | case DP_TRAIN_VOLTAGE_SWING_400: |
||
1576 | return DP_TRAIN_PRE_EMPHASIS_6; |
||
1577 | case DP_TRAIN_VOLTAGE_SWING_600: |
||
1578 | return DP_TRAIN_PRE_EMPHASIS_6; |
||
1579 | case DP_TRAIN_VOLTAGE_SWING_800: |
||
1580 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
||
1581 | case DP_TRAIN_VOLTAGE_SWING_1200: |
||
1582 | default: |
||
1583 | return DP_TRAIN_PRE_EMPHASIS_0; |
||
1584 | } |
||
2342 | Serge | 1585 | } |
2330 | Serge | 1586 | } |
1587 | |||
1588 | static void |
||
2342 | Serge | 1589 | intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
2330 | Serge | 1590 | { |
1591 | uint8_t v = 0; |
||
1592 | uint8_t p = 0; |
||
1593 | int lane; |
||
2342 | Serge | 1594 | uint8_t voltage_max; |
1595 | uint8_t preemph_max; |
||
2330 | Serge | 1596 | |
1597 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
||
3243 | Serge | 1598 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
1599 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); |
||
2330 | Serge | 1600 | |
1601 | if (this_v > v) |
||
1602 | v = this_v; |
||
1603 | if (this_p > p) |
||
1604 | p = this_p; |
||
1605 | } |
||
1606 | |||
2342 | Serge | 1607 | voltage_max = intel_dp_voltage_max(intel_dp); |
1608 | if (v >= voltage_max) |
||
1609 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; |
||
2330 | Serge | 1610 | |
2342 | Serge | 1611 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
1612 | if (p >= preemph_max) |
||
1613 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
||
2330 | Serge | 1614 | |
1615 | for (lane = 0; lane < 4; lane++) |
||
1616 | intel_dp->train_set[lane] = v | p; |
||
1617 | } |
||
1618 | |||
1619 | static uint32_t |
||
3480 | Serge | 1620 | intel_gen4_signal_levels(uint8_t train_set) |
2330 | Serge | 1621 | { |
1622 | uint32_t signal_levels = 0; |
||
1623 | |||
1624 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
||
1625 | case DP_TRAIN_VOLTAGE_SWING_400: |
||
1626 | default: |
||
1627 | signal_levels |= DP_VOLTAGE_0_4; |
||
1628 | break; |
||
1629 | case DP_TRAIN_VOLTAGE_SWING_600: |
||
1630 | signal_levels |= DP_VOLTAGE_0_6; |
||
1631 | break; |
||
1632 | case DP_TRAIN_VOLTAGE_SWING_800: |
||
1633 | signal_levels |= DP_VOLTAGE_0_8; |
||
1634 | break; |
||
1635 | case DP_TRAIN_VOLTAGE_SWING_1200: |
||
1636 | signal_levels |= DP_VOLTAGE_1_2; |
||
1637 | break; |
||
1638 | } |
||
1639 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
||
1640 | case DP_TRAIN_PRE_EMPHASIS_0: |
||
1641 | default: |
||
1642 | signal_levels |= DP_PRE_EMPHASIS_0; |
||
1643 | break; |
||
1644 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
||
1645 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
||
1646 | break; |
||
1647 | case DP_TRAIN_PRE_EMPHASIS_6: |
||
1648 | signal_levels |= DP_PRE_EMPHASIS_6; |
||
1649 | break; |
||
1650 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
||
1651 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
||
1652 | break; |
||
1653 | } |
||
1654 | return signal_levels; |
||
1655 | } |
||
1656 | |||
1657 | /* Gen6's DP voltage swing and pre-emphasis control */ |
||
1658 | static uint32_t |
||
1659 | intel_gen6_edp_signal_levels(uint8_t train_set) |
||
1660 | { |
||
1661 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
||
1662 | DP_TRAIN_PRE_EMPHASIS_MASK); |
||
1663 | switch (signal_levels) { |
||
1664 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
||
1665 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
||
1666 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
||
1667 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
1668 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
||
1669 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
||
1670 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
||
1671 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
||
1672 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
1673 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
1674 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
||
1675 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
||
1676 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
||
1677 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
||
1678 | default: |
||
1679 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
||
1680 | "0x%x\n", signal_levels); |
||
1681 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
||
1682 | } |
||
1683 | } |
||
1684 | |||
2342 | Serge | 1685 | /* Gen7's DP voltage swing and pre-emphasis control */ |
1686 | static uint32_t |
||
1687 | intel_gen7_edp_signal_levels(uint8_t train_set) |
||
1688 | { |
||
1689 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
||
1690 | DP_TRAIN_PRE_EMPHASIS_MASK); |
||
1691 | switch (signal_levels) { |
||
1692 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
||
1693 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
||
1694 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
1695 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
||
1696 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
||
1697 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
||
1698 | |||
1699 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
||
1700 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
||
1701 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
1702 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
||
1703 | |||
1704 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
||
1705 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
||
1706 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
1707 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
||
1708 | |||
1709 | default: |
||
1710 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
||
1711 | "0x%x\n", signal_levels); |
||
1712 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
||
1713 | } |
||
1714 | } |
||
1715 | |||
3243 | Serge | 1716 | /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ |
1717 | static uint32_t |
||
3480 | Serge | 1718 | intel_hsw_signal_levels(uint8_t train_set) |
2330 | Serge | 1719 | { |
3243 | Serge | 1720 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
1721 | DP_TRAIN_PRE_EMPHASIS_MASK); |
||
1722 | switch (signal_levels) { |
||
1723 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
||
1724 | return DDI_BUF_EMP_400MV_0DB_HSW; |
||
1725 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
1726 | return DDI_BUF_EMP_400MV_3_5DB_HSW; |
||
1727 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
||
1728 | return DDI_BUF_EMP_400MV_6DB_HSW; |
||
1729 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: |
||
1730 | return DDI_BUF_EMP_400MV_9_5DB_HSW; |
||
2330 | Serge | 1731 | |
3243 | Serge | 1732 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
1733 | return DDI_BUF_EMP_600MV_0DB_HSW; |
||
1734 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
1735 | return DDI_BUF_EMP_600MV_3_5DB_HSW; |
||
1736 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
||
1737 | return DDI_BUF_EMP_600MV_6DB_HSW; |
||
2330 | Serge | 1738 | |
3243 | Serge | 1739 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
1740 | return DDI_BUF_EMP_800MV_0DB_HSW; |
||
1741 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
||
1742 | return DDI_BUF_EMP_800MV_3_5DB_HSW; |
||
1743 | default: |
||
1744 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
||
1745 | "0x%x\n", signal_levels); |
||
1746 | return DDI_BUF_EMP_400MV_0DB_HSW; |
||
2330 | Serge | 1747 | } |
1748 | } |
||
1749 | |||
3480 | Serge | 1750 | /* Properly updates "DP" with the correct signal levels. */ |
1751 | static void |
||
1752 | intel_dp_set_signal_levels(struct intel_dp *intel_dp, uint32_t *DP) |
||
1753 | { |
||
1754 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
||
1755 | struct drm_device *dev = intel_dig_port->base.base.dev; |
||
1756 | uint32_t signal_levels, mask; |
||
1757 | uint8_t train_set = intel_dp->train_set[0]; |
||
1758 | |||
1759 | if (IS_HASWELL(dev)) { |
||
1760 | signal_levels = intel_hsw_signal_levels(train_set); |
||
1761 | mask = DDI_BUF_EMP_MASK; |
||
1762 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { |
||
1763 | signal_levels = intel_gen7_edp_signal_levels(train_set); |
||
1764 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; |
||
1765 | } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { |
||
1766 | signal_levels = intel_gen6_edp_signal_levels(train_set); |
||
1767 | mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; |
||
1768 | } else { |
||
1769 | signal_levels = intel_gen4_signal_levels(train_set); |
||
1770 | mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; |
||
1771 | } |
||
1772 | |||
1773 | DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); |
||
1774 | |||
1775 | *DP = (*DP & ~mask) | signal_levels; |
||
1776 | } |
||
1777 | |||
2330 | Serge | 1778 | static bool |
1779 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
||
1780 | uint32_t dp_reg_value, |
||
1781 | uint8_t dp_train_pat) |
||
1782 | { |
||
3243 | Serge | 1783 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
1784 | struct drm_device *dev = intel_dig_port->base.base.dev; |
||
2330 | Serge | 1785 | struct drm_i915_private *dev_priv = dev->dev_private; |
3243 | Serge | 1786 | enum port port = intel_dig_port->port; |
2330 | Serge | 1787 | int ret; |
3243 | Serge | 1788 | uint32_t temp; |
2330 | Serge | 1789 | |
3243 | Serge | 1790 | if (IS_HASWELL(dev)) { |
1791 | temp = I915_READ(DP_TP_CTL(port)); |
||
1792 | |||
1793 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
||
1794 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
||
1795 | else |
||
1796 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
||
1797 | |||
1798 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
||
1799 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
||
1800 | case DP_TRAINING_PATTERN_DISABLE: |
||
3480 | Serge | 1801 | |
1802 | if (port != PORT_A) { |
||
3243 | Serge | 1803 | temp |= DP_TP_CTL_LINK_TRAIN_IDLE; |
1804 | I915_WRITE(DP_TP_CTL(port), temp); |
||
1805 | |||
1806 | if (wait_for((I915_READ(DP_TP_STATUS(port)) & |
||
1807 | DP_TP_STATUS_IDLE_DONE), 1)) |
||
1808 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
||
1809 | |||
1810 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
||
3480 | Serge | 1811 | } |
1812 | |||
3243 | Serge | 1813 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
1814 | |||
1815 | break; |
||
1816 | case DP_TRAINING_PATTERN_1: |
||
1817 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
||
1818 | break; |
||
1819 | case DP_TRAINING_PATTERN_2: |
||
1820 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
||
1821 | break; |
||
1822 | case DP_TRAINING_PATTERN_3: |
||
1823 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
||
1824 | break; |
||
1825 | } |
||
1826 | I915_WRITE(DP_TP_CTL(port), temp); |
||
1827 | |||
1828 | } else if (HAS_PCH_CPT(dev) && |
||
1829 | (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { |
||
3031 | serge | 1830 | dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT; |
1831 | |||
1832 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
||
1833 | case DP_TRAINING_PATTERN_DISABLE: |
||
1834 | dp_reg_value |= DP_LINK_TRAIN_OFF_CPT; |
||
1835 | break; |
||
1836 | case DP_TRAINING_PATTERN_1: |
||
1837 | dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT; |
||
1838 | break; |
||
1839 | case DP_TRAINING_PATTERN_2: |
||
1840 | dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT; |
||
1841 | break; |
||
1842 | case DP_TRAINING_PATTERN_3: |
||
1843 | DRM_ERROR("DP training pattern 3 not supported\n"); |
||
1844 | dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT; |
||
1845 | break; |
||
1846 | } |
||
1847 | |||
1848 | } else { |
||
1849 | dp_reg_value &= ~DP_LINK_TRAIN_MASK; |
||
1850 | |||
1851 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
||
1852 | case DP_TRAINING_PATTERN_DISABLE: |
||
1853 | dp_reg_value |= DP_LINK_TRAIN_OFF; |
||
1854 | break; |
||
1855 | case DP_TRAINING_PATTERN_1: |
||
1856 | dp_reg_value |= DP_LINK_TRAIN_PAT_1; |
||
1857 | break; |
||
1858 | case DP_TRAINING_PATTERN_2: |
||
1859 | dp_reg_value |= DP_LINK_TRAIN_PAT_2; |
||
1860 | break; |
||
1861 | case DP_TRAINING_PATTERN_3: |
||
1862 | DRM_ERROR("DP training pattern 3 not supported\n"); |
||
1863 | dp_reg_value |= DP_LINK_TRAIN_PAT_2; |
||
1864 | break; |
||
1865 | } |
||
1866 | } |
||
1867 | |||
2330 | Serge | 1868 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
1869 | POSTING_READ(intel_dp->output_reg); |
||
1870 | |||
1871 | intel_dp_aux_native_write_1(intel_dp, |
||
1872 | DP_TRAINING_PATTERN_SET, |
||
1873 | dp_train_pat); |
||
1874 | |||
3031 | serge | 1875 | if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) != |
1876 | DP_TRAINING_PATTERN_DISABLE) { |
||
2330 | Serge | 1877 | ret = intel_dp_aux_native_write(intel_dp, |
1878 | DP_TRAINING_LANE0_SET, |
||
2342 | Serge | 1879 | intel_dp->train_set, |
1880 | intel_dp->lane_count); |
||
1881 | if (ret != intel_dp->lane_count) |
||
2330 | Serge | 1882 | return false; |
3031 | serge | 1883 | } |
2330 | Serge | 1884 | |
1885 | return true; |
||
1886 | } |
||
1887 | |||
1888 | /* Enable corresponding port and start training pattern 1 */ |
||
3243 | Serge | 1889 | void |
2330 | Serge | 1890 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
1891 | { |
||
3243 | Serge | 1892 | struct drm_encoder *encoder = &dp_to_dig_port(intel_dp)->base.base; |
1893 | struct drm_device *dev = encoder->dev; |
||
2330 | Serge | 1894 | int i; |
1895 | uint8_t voltage; |
||
1896 | bool clock_recovery = false; |
||
2342 | Serge | 1897 | int voltage_tries, loop_tries; |
2330 | Serge | 1898 | uint32_t DP = intel_dp->DP; |
1899 | |||
3480 | Serge | 1900 | if (HAS_DDI(dev)) |
3243 | Serge | 1901 | intel_ddi_prepare_link_retrain(encoder); |
1902 | |||
2330 | Serge | 1903 | /* Write the link configuration data */ |
1904 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, |
||
1905 | intel_dp->link_configuration, |
||
1906 | DP_LINK_CONFIGURATION_SIZE); |
||
1907 | |||
1908 | DP |= DP_PORT_EN; |
||
2342 | Serge | 1909 | |
2330 | Serge | 1910 | memset(intel_dp->train_set, 0, 4); |
1911 | voltage = 0xff; |
||
2342 | Serge | 1912 | voltage_tries = 0; |
1913 | loop_tries = 0; |
||
2330 | Serge | 1914 | clock_recovery = false; |
1915 | for (;;) { |
||
1916 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
||
2342 | Serge | 1917 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
1918 | |||
3480 | Serge | 1919 | intel_dp_set_signal_levels(intel_dp, &DP); |
2330 | Serge | 1920 | |
3243 | Serge | 1921 | /* Set training pattern 1 */ |
3031 | serge | 1922 | if (!intel_dp_set_link_train(intel_dp, DP, |
2330 | Serge | 1923 | DP_TRAINING_PATTERN_1 | |
1924 | DP_LINK_SCRAMBLING_DISABLE)) |
||
1925 | break; |
||
1926 | |||
3243 | Serge | 1927 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
2342 | Serge | 1928 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
1929 | DRM_ERROR("failed to get link status\n"); |
||
2330 | Serge | 1930 | break; |
2342 | Serge | 1931 | } |
2330 | Serge | 1932 | |
3243 | Serge | 1933 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
2342 | Serge | 1934 | DRM_DEBUG_KMS("clock recovery OK\n"); |
2330 | Serge | 1935 | clock_recovery = true; |
1936 | break; |
||
1937 | } |
||
1938 | |||
1939 | /* Check to see if we've tried the max voltage */ |
||
1940 | for (i = 0; i < intel_dp->lane_count; i++) |
||
1941 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
||
1942 | break; |
||
3480 | Serge | 1943 | if (i == intel_dp->lane_count) { |
2342 | Serge | 1944 | ++loop_tries; |
1945 | if (loop_tries == 5) { |
||
1946 | DRM_DEBUG_KMS("too many full retries, give up\n"); |
||
2330 | Serge | 1947 | break; |
2342 | Serge | 1948 | } |
1949 | memset(intel_dp->train_set, 0, 4); |
||
1950 | voltage_tries = 0; |
||
1951 | continue; |
||
1952 | } |
||
2330 | Serge | 1953 | |
1954 | /* Check to see if we've tried the same voltage 5 times */ |
||
1955 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { |
||
2342 | Serge | 1956 | ++voltage_tries; |
1957 | if (voltage_tries == 5) { |
||
1958 | DRM_DEBUG_KMS("too many voltage retries, give up\n"); |
||
2330 | Serge | 1959 | break; |
2342 | Serge | 1960 | } |
2330 | Serge | 1961 | } else |
2342 | Serge | 1962 | voltage_tries = 0; |
2330 | Serge | 1963 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
1964 | |||
1965 | /* Compute new intel_dp->train_set as requested by target */ |
||
2342 | Serge | 1966 | intel_get_adjust_train(intel_dp, link_status); |
2330 | Serge | 1967 | } |
1968 | |||
1969 | intel_dp->DP = DP; |
||
1970 | } |
||
1971 | |||
3243 | Serge | 1972 | void |
2330 | Serge | 1973 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
1974 | { |
||
1975 | bool channel_eq = false; |
||
1976 | int tries, cr_tries; |
||
1977 | uint32_t DP = intel_dp->DP; |
||
1978 | |||
1979 | /* channel equalization */ |
||
1980 | tries = 0; |
||
1981 | cr_tries = 0; |
||
1982 | channel_eq = false; |
||
1983 | for (;;) { |
||
2342 | Serge | 1984 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
2330 | Serge | 1985 | |
1986 | if (cr_tries > 5) { |
||
1987 | DRM_ERROR("failed to train DP, aborting\n"); |
||
1988 | intel_dp_link_down(intel_dp); |
||
1989 | break; |
||
1990 | } |
||
1991 | |||
3480 | Serge | 1992 | intel_dp_set_signal_levels(intel_dp, &DP); |
2330 | Serge | 1993 | |
1994 | /* channel eq pattern */ |
||
3031 | serge | 1995 | if (!intel_dp_set_link_train(intel_dp, DP, |
2330 | Serge | 1996 | DP_TRAINING_PATTERN_2 | |
1997 | DP_LINK_SCRAMBLING_DISABLE)) |
||
1998 | break; |
||
1999 | |||
3243 | Serge | 2000 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
2342 | Serge | 2001 | if (!intel_dp_get_link_status(intel_dp, link_status)) |
2330 | Serge | 2002 | break; |
2003 | |||
2004 | /* Make sure clock is still ok */ |
||
3243 | Serge | 2005 | if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
2330 | Serge | 2006 | intel_dp_start_link_train(intel_dp); |
2007 | cr_tries++; |
||
2008 | continue; |
||
2009 | } |
||
2010 | |||
3243 | Serge | 2011 | if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
2330 | Serge | 2012 | channel_eq = true; |
2013 | break; |
||
2014 | } |
||
2015 | |||
2016 | /* Try 5 times, then try clock recovery if that fails */ |
||
2017 | if (tries > 5) { |
||
2018 | intel_dp_link_down(intel_dp); |
||
2019 | intel_dp_start_link_train(intel_dp); |
||
2020 | tries = 0; |
||
2021 | cr_tries++; |
||
2022 | continue; |
||
2023 | } |
||
2024 | |||
2025 | /* Compute new intel_dp->train_set as requested by target */ |
||
2342 | Serge | 2026 | intel_get_adjust_train(intel_dp, link_status); |
2330 | Serge | 2027 | ++tries; |
2028 | } |
||
2029 | |||
3243 | Serge | 2030 | if (channel_eq) |
2031 | DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n"); |
||
2032 | |||
3031 | serge | 2033 | intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE); |
2330 | Serge | 2034 | } |
2035 | |||
2036 | static void |
||
2037 | intel_dp_link_down(struct intel_dp *intel_dp) |
||
2038 | { |
||
3243 | Serge | 2039 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2040 | struct drm_device *dev = intel_dig_port->base.base.dev; |
||
2330 | Serge | 2041 | struct drm_i915_private *dev_priv = dev->dev_private; |
3480 | Serge | 2042 | struct intel_crtc *intel_crtc = |
2043 | to_intel_crtc(intel_dig_port->base.base.crtc); |
||
2330 | Serge | 2044 | uint32_t DP = intel_dp->DP; |
2045 | |||
3243 | Serge | 2046 | /* |
2047 | * DDI code has a strict mode set sequence and we should try to respect |
||
2048 | * it, otherwise we might hang the machine in many different ways. So we |
||
2049 | * really should be disabling the port only on a complete crtc_disable |
||
2050 | * sequence. This function is just called under two conditions on DDI |
||
2051 | * code: |
||
2052 | * - Link train failed while doing crtc_enable, and on this case we |
||
2053 | * really should respect the mode set sequence and wait for a |
||
2054 | * crtc_disable. |
||
2055 | * - Someone turned the monitor off and intel_dp_check_link_status |
||
2056 | * called us. We don't need to disable the whole port on this case, so |
||
2057 | * when someone turns the monitor on again, |
||
2058 | * intel_ddi_prepare_link_retrain will take care of redoing the link |
||
2059 | * train. |
||
2060 | */ |
||
3480 | Serge | 2061 | if (HAS_DDI(dev)) |
3243 | Serge | 2062 | return; |
2063 | |||
3031 | serge | 2064 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
2330 | Serge | 2065 | return; |
2066 | |||
2067 | DRM_DEBUG_KMS("\n"); |
||
2068 | |||
2342 | Serge | 2069 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { |
2330 | Serge | 2070 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
2071 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
||
2072 | } else { |
||
2073 | DP &= ~DP_LINK_TRAIN_MASK; |
||
2074 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
||
2075 | } |
||
2076 | POSTING_READ(intel_dp->output_reg); |
||
2077 | |||
3480 | Serge | 2078 | /* We don't really know why we're doing this */ |
2079 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
||
2330 | Serge | 2080 | |
3031 | serge | 2081 | if (HAS_PCH_IBX(dev) && |
2330 | Serge | 2082 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
3243 | Serge | 2083 | struct drm_crtc *crtc = intel_dig_port->base.base.crtc; |
2330 | Serge | 2084 | |
2085 | /* Hardware workaround: leaving our transcoder select |
||
2086 | * set to transcoder B while it's off will prevent the |
||
2087 | * corresponding HDMI output on transcoder A. |
||
2088 | * |
||
2089 | * Combine this with another hardware workaround: |
||
2090 | * transcoder select bit can only be cleared while the |
||
2091 | * port is enabled. |
||
2092 | */ |
||
2093 | DP &= ~DP_PIPEB_SELECT; |
||
2094 | I915_WRITE(intel_dp->output_reg, DP); |
||
2095 | |||
2096 | /* Changes to enable or select take place the vblank |
||
2097 | * after being written. |
||
2098 | */ |
||
3480 | Serge | 2099 | if (WARN_ON(crtc == NULL)) { |
2100 | /* We should never try to disable a port without a crtc |
||
2101 | * attached. For paranoia keep the code around for a |
||
2102 | * bit. */ |
||
2330 | Serge | 2103 | POSTING_READ(intel_dp->output_reg); |
2104 | msleep(50); |
||
2105 | } else |
||
3480 | Serge | 2106 | intel_wait_for_vblank(dev, intel_crtc->pipe); |
2330 | Serge | 2107 | } |
2108 | |||
2342 | Serge | 2109 | DP &= ~DP_AUDIO_OUTPUT_ENABLE; |
2330 | Serge | 2110 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
2111 | POSTING_READ(intel_dp->output_reg); |
||
2342 | Serge | 2112 | msleep(intel_dp->panel_power_down_delay); |
2330 | Serge | 2113 | } |
2114 | |||
2115 | static bool |
||
2116 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
||
2117 | { |
||
3480 | Serge | 2118 | char dpcd_hex_dump[sizeof(intel_dp->dpcd) * 3]; |
2119 | |||
2330 | Serge | 2120 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
3031 | serge | 2121 | sizeof(intel_dp->dpcd)) == 0) |
2122 | return false; /* aux transfer failed */ |
||
2123 | |||
3480 | Serge | 2124 | hex_dump_to_buffer(intel_dp->dpcd, sizeof(intel_dp->dpcd), |
2125 | 32, 1, dpcd_hex_dump, sizeof(dpcd_hex_dump), false); |
||
2126 | DRM_DEBUG_KMS("DPCD: %s\n", dpcd_hex_dump); |
||
2127 | |||
3031 | serge | 2128 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
2129 | return false; /* DPCD not present */ |
||
2130 | |||
2131 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
||
2132 | DP_DWN_STRM_PORT_PRESENT)) |
||
2133 | return true; /* native DP sink */ |
||
2134 | |||
2135 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
||
2136 | return true; /* no per-port downstream info */ |
||
2137 | |||
2138 | if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0, |
||
2139 | intel_dp->downstream_ports, |
||
2140 | DP_MAX_DOWNSTREAM_PORTS) == 0) |
||
2141 | return false; /* downstream port status fetch failed */ |
||
2142 | |||
2330 | Serge | 2143 | return true; |
3031 | serge | 2144 | } |
2330 | Serge | 2145 | |
3031 | serge | 2146 | static void |
2147 | intel_dp_probe_oui(struct intel_dp *intel_dp) |
||
2148 | { |
||
2149 | u8 buf[3]; |
||
2150 | |||
2151 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
||
2152 | return; |
||
2153 | |||
2154 | ironlake_edp_panel_vdd_on(intel_dp); |
||
2155 | |||
2156 | if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3)) |
||
2157 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
||
2158 | buf[0], buf[1], buf[2]); |
||
2159 | |||
2160 | if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3)) |
||
2161 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
||
2162 | buf[0], buf[1], buf[2]); |
||
2163 | |||
2164 | ironlake_edp_panel_vdd_off(intel_dp, false); |
||
2330 | Serge | 2165 | } |
2166 | |||
2342 | Serge | 2167 | static bool |
2168 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
||
2169 | { |
||
2170 | int ret; |
||
2171 | |||
2172 | ret = intel_dp_aux_native_read_retry(intel_dp, |
||
2173 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
||
2174 | sink_irq_vector, 1); |
||
2175 | if (!ret) |
||
2176 | return false; |
||
2177 | |||
2178 | return true; |
||
2179 | } |
||
2180 | |||
2181 | static void |
||
2182 | intel_dp_handle_test_request(struct intel_dp *intel_dp) |
||
2183 | { |
||
2184 | /* NAK by default */ |
||
3243 | Serge | 2185 | intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK); |
2342 | Serge | 2186 | } |
2187 | |||
2330 | Serge | 2188 | /* |
2189 | * According to DP spec |
||
2190 | * 5.1.2: |
||
2191 | * 1. Read DPCD |
||
2192 | * 2. Configure link according to Receiver Capabilities |
||
2193 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
||
2194 | * 4. Check link status on receipt of hot-plug interrupt |
||
2195 | */ |
||
2196 | |||
3243 | Serge | 2197 | void |
2330 | Serge | 2198 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
2199 | { |
||
3243 | Serge | 2200 | struct intel_encoder *intel_encoder = &dp_to_dig_port(intel_dp)->base; |
2342 | Serge | 2201 | u8 sink_irq_vector; |
2202 | u8 link_status[DP_LINK_STATUS_SIZE]; |
||
2203 | |||
3243 | Serge | 2204 | if (!intel_encoder->connectors_active) |
2330 | Serge | 2205 | return; |
2206 | |||
3243 | Serge | 2207 | if (WARN_ON(!intel_encoder->base.crtc)) |
2330 | Serge | 2208 | return; |
2209 | |||
2210 | /* Try to read receiver status if the link appears to be up */ |
||
2342 | Serge | 2211 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
2330 | Serge | 2212 | intel_dp_link_down(intel_dp); |
2213 | return; |
||
2214 | } |
||
2215 | |||
2216 | /* Now read the DPCD to see if it's actually running */ |
||
2217 | if (!intel_dp_get_dpcd(intel_dp)) { |
||
2218 | intel_dp_link_down(intel_dp); |
||
2219 | return; |
||
2220 | } |
||
2221 | |||
2342 | Serge | 2222 | /* Try to read the source of the interrupt */ |
2223 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
||
2224 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
||
2225 | /* Clear interrupt source */ |
||
2226 | intel_dp_aux_native_write_1(intel_dp, |
||
2227 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
||
2228 | sink_irq_vector); |
||
2229 | |||
2230 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
||
2231 | intel_dp_handle_test_request(intel_dp); |
||
2232 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
||
2233 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
||
2234 | } |
||
2235 | |||
3243 | Serge | 2236 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
2330 | Serge | 2237 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
3243 | Serge | 2238 | drm_get_encoder_name(&intel_encoder->base)); |
2330 | Serge | 2239 | intel_dp_start_link_train(intel_dp); |
2240 | intel_dp_complete_link_train(intel_dp); |
||
2241 | } |
||
2242 | } |
||
2243 | |||
3031 | serge | 2244 | /* XXX this is probably wrong for multiple downstream ports */ |
2330 | Serge | 2245 | static enum drm_connector_status |
2246 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
||
2247 | { |
||
3031 | serge | 2248 | uint8_t *dpcd = intel_dp->dpcd; |
2249 | bool hpd; |
||
2250 | uint8_t type; |
||
2251 | |||
2252 | if (!intel_dp_get_dpcd(intel_dp)) |
||
2253 | return connector_status_disconnected; |
||
2254 | |||
2255 | /* if there's no downstream port, we're done */ |
||
2256 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) |
||
2330 | Serge | 2257 | return connector_status_connected; |
3031 | serge | 2258 | |
2259 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
||
2260 | hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD); |
||
2261 | if (hpd) { |
||
2262 | uint8_t reg; |
||
2263 | if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT, |
||
2264 | ®, 1)) |
||
2265 | return connector_status_unknown; |
||
2266 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
||
2267 | : connector_status_disconnected; |
||
2268 | } |
||
2269 | |||
2270 | /* If no HPD, poke DDC gently */ |
||
2271 | if (drm_probe_ddc(&intel_dp->adapter)) |
||
2272 | return connector_status_connected; |
||
2273 | |||
2274 | /* Well we tried, say unknown for unreliable port types */ |
||
2275 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
||
2276 | if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID) |
||
2277 | return connector_status_unknown; |
||
2278 | |||
2279 | /* Anything else is out of spec, warn and ignore */ |
||
2280 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
||
2330 | Serge | 2281 | return connector_status_disconnected; |
2282 | } |
||
2283 | |||
2284 | static enum drm_connector_status |
||
2285 | ironlake_dp_detect(struct intel_dp *intel_dp) |
||
2286 | { |
||
3243 | Serge | 2287 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
3480 | Serge | 2288 | struct drm_i915_private *dev_priv = dev->dev_private; |
2289 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
||
2330 | Serge | 2290 | enum drm_connector_status status; |
2291 | |||
2292 | /* Can't disconnect eDP, but you can close the lid... */ |
||
2293 | if (is_edp(intel_dp)) { |
||
3243 | Serge | 2294 | status = intel_panel_detect(dev); |
2330 | Serge | 2295 | if (status == connector_status_unknown) |
2296 | status = connector_status_connected; |
||
2297 | return status; |
||
2298 | } |
||
2299 | |||
3480 | Serge | 2300 | if (!ibx_digital_port_connected(dev_priv, intel_dig_port)) |
2301 | return connector_status_disconnected; |
||
2302 | |||
2330 | Serge | 2303 | return intel_dp_detect_dpcd(intel_dp); |
2304 | } |
||
2305 | |||
2306 | static enum drm_connector_status |
||
2307 | g4x_dp_detect(struct intel_dp *intel_dp) |
||
2308 | { |
||
3243 | Serge | 2309 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2330 | Serge | 2310 | struct drm_i915_private *dev_priv = dev->dev_private; |
3480 | Serge | 2311 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
3031 | serge | 2312 | uint32_t bit; |
2330 | Serge | 2313 | |
3480 | Serge | 2314 | switch (intel_dig_port->port) { |
2315 | case PORT_B: |
||
2316 | bit = PORTB_HOTPLUG_LIVE_STATUS; |
||
2330 | Serge | 2317 | break; |
3480 | Serge | 2318 | case PORT_C: |
2319 | bit = PORTC_HOTPLUG_LIVE_STATUS; |
||
2330 | Serge | 2320 | break; |
3480 | Serge | 2321 | case PORT_D: |
2322 | bit = PORTD_HOTPLUG_LIVE_STATUS; |
||
2330 | Serge | 2323 | break; |
2324 | default: |
||
2325 | return connector_status_unknown; |
||
2326 | } |
||
2327 | |||
3031 | serge | 2328 | if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) |
2330 | Serge | 2329 | return connector_status_disconnected; |
2330 | |||
2331 | return intel_dp_detect_dpcd(intel_dp); |
||
2332 | } |
||
2333 | |||
2342 | Serge | 2334 | static struct edid * |
2335 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) |
||
2336 | { |
||
3243 | Serge | 2337 | struct intel_connector *intel_connector = to_intel_connector(connector); |
2338 | |||
2339 | /* use cached edid if we have one */ |
||
2340 | if (intel_connector->edid) { |
||
2342 | Serge | 2341 | struct edid *edid; |
3031 | serge | 2342 | int size; |
2342 | Serge | 2343 | |
3243 | Serge | 2344 | /* invalid edid */ |
2345 | if (IS_ERR(intel_connector->edid)) |
||
3031 | serge | 2346 | return NULL; |
2347 | |||
3243 | Serge | 2348 | size = (intel_connector->edid->extensions + 1) * EDID_LENGTH; |
3031 | serge | 2349 | edid = kmalloc(size, GFP_KERNEL); |
2350 | if (!edid) |
||
2351 | return NULL; |
||
2352 | |||
3243 | Serge | 2353 | memcpy(edid, intel_connector->edid, size); |
3031 | serge | 2354 | return edid; |
2355 | } |
||
2356 | |||
3243 | Serge | 2357 | return drm_get_edid(connector, adapter); |
2342 | Serge | 2358 | } |
2359 | |||
2360 | static int |
||
2361 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) |
||
2362 | { |
||
3243 | Serge | 2363 | struct intel_connector *intel_connector = to_intel_connector(connector); |
2342 | Serge | 2364 | |
3243 | Serge | 2365 | /* use cached edid if we have one */ |
2366 | if (intel_connector->edid) { |
||
2367 | /* invalid edid */ |
||
2368 | if (IS_ERR(intel_connector->edid)) |
||
2369 | return 0; |
||
2370 | |||
2371 | return intel_connector_update_modes(connector, |
||
2372 | intel_connector->edid); |
||
3031 | serge | 2373 | } |
2374 | |||
3243 | Serge | 2375 | return intel_ddc_get_modes(connector, adapter); |
2342 | Serge | 2376 | } |
2377 | |||
2330 | Serge | 2378 | static enum drm_connector_status |
2379 | intel_dp_detect(struct drm_connector *connector, bool force) |
||
2380 | { |
||
2381 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
||
3243 | Serge | 2382 | struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); |
2383 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
||
2384 | struct drm_device *dev = connector->dev; |
||
2330 | Serge | 2385 | enum drm_connector_status status; |
2386 | struct edid *edid = NULL; |
||
2387 | |||
2388 | intel_dp->has_audio = false; |
||
2389 | |||
2390 | if (HAS_PCH_SPLIT(dev)) |
||
2391 | status = ironlake_dp_detect(intel_dp); |
||
2392 | else |
||
2393 | status = g4x_dp_detect(intel_dp); |
||
2394 | |||
2395 | if (status != connector_status_connected) |
||
2396 | return status; |
||
3031 | serge | 2397 | |
2398 | intel_dp_probe_oui(intel_dp); |
||
2399 | |||
3243 | Serge | 2400 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { |
2401 | intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); |
||
2330 | Serge | 2402 | } else { |
3031 | serge | 2403 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
2330 | Serge | 2404 | if (edid) { |
2405 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
||
2406 | kfree(edid); |
||
2407 | } |
||
2408 | } |
||
3243 | Serge | 2409 | |
2410 | if (intel_encoder->type != INTEL_OUTPUT_EDP) |
||
2411 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
||
2330 | Serge | 2412 | return connector_status_connected; |
2413 | } |
||
2414 | |||
2415 | static int intel_dp_get_modes(struct drm_connector *connector) |
||
2416 | { |
||
2417 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
||
3243 | Serge | 2418 | struct intel_connector *intel_connector = to_intel_connector(connector); |
2419 | struct drm_device *dev = connector->dev; |
||
2330 | Serge | 2420 | int ret; |
2421 | |||
2422 | /* We should parse the EDID data and find out if it has an audio sink |
||
2423 | */ |
||
2424 | |||
2342 | Serge | 2425 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); |
3243 | Serge | 2426 | if (ret) |
2330 | Serge | 2427 | return ret; |
2428 | |||
3243 | Serge | 2429 | /* if eDP has no EDID, fall back to fixed mode */ |
2430 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
||
2330 | Serge | 2431 | struct drm_display_mode *mode; |
3243 | Serge | 2432 | mode = drm_mode_duplicate(dev, |
2433 | intel_connector->panel.fixed_mode); |
||
2434 | if (mode) { |
||
2330 | Serge | 2435 | drm_mode_probed_add(connector, mode); |
2436 | return 1; |
||
2437 | } |
||
2438 | } |
||
2439 | return 0; |
||
2440 | } |
||
2441 | |||
3243 | Serge | 2442 | static bool |
2443 | intel_dp_detect_audio(struct drm_connector *connector) |
||
2444 | { |
||
2445 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
||
2446 | struct edid *edid; |
||
2447 | bool has_audio = false; |
||
2330 | Serge | 2448 | |
3243 | Serge | 2449 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
2450 | if (edid) { |
||
2451 | has_audio = drm_detect_monitor_audio(edid); |
||
2452 | kfree(edid); |
||
2453 | } |
||
2330 | Serge | 2454 | |
3243 | Serge | 2455 | return has_audio; |
2456 | } |
||
2330 | Serge | 2457 | |
2458 | static int |
||
2459 | intel_dp_set_property(struct drm_connector *connector, |
||
2460 | struct drm_property *property, |
||
2461 | uint64_t val) |
||
2462 | { |
||
2463 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
||
3243 | Serge | 2464 | struct intel_connector *intel_connector = to_intel_connector(connector); |
2465 | struct intel_encoder *intel_encoder = intel_attached_encoder(connector); |
||
2466 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
||
2330 | Serge | 2467 | int ret; |
2468 | |||
3243 | Serge | 2469 | ret = drm_object_property_set_value(&connector->base, property, val); |
2330 | Serge | 2470 | if (ret) |
2471 | return ret; |
||
3480 | Serge | 2472 | |
2330 | Serge | 2473 | if (property == dev_priv->force_audio_property) { |
2474 | int i = val; |
||
2475 | bool has_audio; |
||
2476 | |||
2477 | if (i == intel_dp->force_audio) |
||
2478 | return 0; |
||
2479 | |||
2480 | intel_dp->force_audio = i; |
||
2481 | |||
3031 | serge | 2482 | if (i == HDMI_AUDIO_AUTO) |
2330 | Serge | 2483 | has_audio = intel_dp_detect_audio(connector); |
2484 | else |
||
3031 | serge | 2485 | has_audio = (i == HDMI_AUDIO_ON); |
2330 | Serge | 2486 | |
2487 | if (has_audio == intel_dp->has_audio) |
||
2488 | return 0; |
||
2489 | |||
2490 | intel_dp->has_audio = has_audio; |
||
2491 | goto done; |
||
2492 | } |
||
2493 | |||
2494 | if (property == dev_priv->broadcast_rgb_property) { |
||
3480 | Serge | 2495 | switch (val) { |
2496 | case INTEL_BROADCAST_RGB_AUTO: |
||
2497 | intel_dp->color_range_auto = true; |
||
2498 | break; |
||
2499 | case INTEL_BROADCAST_RGB_FULL: |
||
2500 | intel_dp->color_range_auto = false; |
||
2501 | intel_dp->color_range = 0; |
||
2502 | break; |
||
2503 | case INTEL_BROADCAST_RGB_LIMITED: |
||
2504 | intel_dp->color_range_auto = false; |
||
2505 | intel_dp->color_range = DP_COLOR_RANGE_16_235; |
||
2506 | break; |
||
2507 | default: |
||
2508 | return -EINVAL; |
||
2509 | } |
||
2330 | Serge | 2510 | goto done; |
2511 | } |
||
2512 | |||
3243 | Serge | 2513 | if (is_edp(intel_dp) && |
2514 | property == connector->dev->mode_config.scaling_mode_property) { |
||
2515 | if (val == DRM_MODE_SCALE_NONE) { |
||
2516 | DRM_DEBUG_KMS("no scaling not supported\n"); |
||
2517 | return -EINVAL; |
||
2518 | } |
||
2519 | |||
2520 | if (intel_connector->panel.fitting_mode == val) { |
||
2521 | /* the eDP scaling property is not changed */ |
||
2522 | return 0; |
||
2523 | } |
||
2524 | intel_connector->panel.fitting_mode = val; |
||
2525 | |||
2526 | goto done; |
||
2527 | } |
||
2528 | |||
2330 | Serge | 2529 | return -EINVAL; |
2530 | |||
2531 | done: |
||
3480 | Serge | 2532 | if (intel_encoder->base.crtc) |
2533 | intel_crtc_restore_mode(intel_encoder->base.crtc); |
||
2330 | Serge | 2534 | |
2535 | return 0; |
||
2536 | } |
||
2537 | |||
2538 | static void |
||
2342 | Serge | 2539 | intel_dp_destroy(struct drm_connector *connector) |
2330 | Serge | 2540 | { |
2541 | struct drm_device *dev = connector->dev; |
||
3031 | serge | 2542 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
3243 | Serge | 2543 | struct intel_connector *intel_connector = to_intel_connector(connector); |
2330 | Serge | 2544 | |
3243 | Serge | 2545 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
2546 | kfree(intel_connector->edid); |
||
2547 | |||
2548 | if (is_edp(intel_dp)) { |
||
2330 | Serge | 2549 | intel_panel_destroy_backlight(dev); |
3243 | Serge | 2550 | intel_panel_fini(&intel_connector->panel); |
2551 | } |
||
2330 | Serge | 2552 | |
2553 | drm_sysfs_connector_remove(connector); |
||
2554 | drm_connector_cleanup(connector); |
||
2555 | kfree(connector); |
||
2556 | } |
||
2557 | |||
3243 | Serge | 2558 | void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
2330 | Serge | 2559 | { |
3243 | Serge | 2560 | struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); |
2561 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
||
3480 | Serge | 2562 | struct drm_device *dev = intel_dp_to_dev(intel_dp); |
2330 | Serge | 2563 | |
3243 | Serge | 2564 | i2c_del_adapter(&intel_dp->adapter); |
2330 | Serge | 2565 | drm_encoder_cleanup(encoder); |
2342 | Serge | 2566 | if (is_edp(intel_dp)) { |
2567 | // cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
||
3480 | Serge | 2568 | mutex_lock(&dev->mode_config.mutex); |
2342 | Serge | 2569 | ironlake_panel_vdd_off_sync(intel_dp); |
3480 | Serge | 2570 | mutex_unlock(&dev->mode_config.mutex); |
2342 | Serge | 2571 | } |
3243 | Serge | 2572 | kfree(intel_dig_port); |
2330 | Serge | 2573 | } |
2574 | |||
2575 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
||
2576 | .mode_fixup = intel_dp_mode_fixup, |
||
2577 | .mode_set = intel_dp_mode_set, |
||
2578 | }; |
||
2579 | |||
2580 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
||
3031 | serge | 2581 | .dpms = intel_connector_dpms, |
2330 | Serge | 2582 | .detect = intel_dp_detect, |
2583 | .fill_modes = drm_helper_probe_single_connector_modes, |
||
2584 | .set_property = intel_dp_set_property, |
||
2585 | .destroy = intel_dp_destroy, |
||
2586 | }; |
||
2587 | |||
2588 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
||
2589 | .get_modes = intel_dp_get_modes, |
||
2590 | .mode_valid = intel_dp_mode_valid, |
||
2591 | .best_encoder = intel_best_encoder, |
||
2592 | }; |
||
2593 | |||
2594 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
||
2595 | .destroy = intel_dp_encoder_destroy, |
||
2596 | }; |
||
2597 | |||
2598 | static void |
||
2599 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
||
2600 | { |
||
3243 | Serge | 2601 | struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); |
2330 | Serge | 2602 | |
2603 | intel_dp_check_link_status(intel_dp); |
||
2604 | } |
||
2605 | |||
2327 | Serge | 2606 | /* Return which DP Port should be selected for Transcoder DP control */ |
2607 | int |
||
2342 | Serge | 2608 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
2327 | Serge | 2609 | { |
2610 | struct drm_device *dev = crtc->dev; |
||
3243 | Serge | 2611 | struct intel_encoder *intel_encoder; |
2612 | struct intel_dp *intel_dp; |
||
2327 | Serge | 2613 | |
3243 | Serge | 2614 | for_each_encoder_on_crtc(dev, crtc, intel_encoder) { |
2615 | intel_dp = enc_to_intel_dp(&intel_encoder->base); |
||
2327 | Serge | 2616 | |
3243 | Serge | 2617 | if (intel_encoder->type == INTEL_OUTPUT_DISPLAYPORT || |
2618 | intel_encoder->type == INTEL_OUTPUT_EDP) |
||
2327 | Serge | 2619 | return intel_dp->output_reg; |
2620 | } |
||
2621 | |||
2622 | return -1; |
||
2623 | } |
||
2330 | Serge | 2624 | |
2625 | /* check the VBT to see whether the eDP is on DP-D port */ |
||
2626 | bool intel_dpd_is_edp(struct drm_device *dev) |
||
2627 | { |
||
2628 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2629 | struct child_device_config *p_child; |
||
2630 | int i; |
||
2631 | |||
2632 | if (!dev_priv->child_dev_num) |
||
2633 | return false; |
||
2634 | |||
2635 | for (i = 0; i < dev_priv->child_dev_num; i++) { |
||
2636 | p_child = dev_priv->child_dev + i; |
||
2637 | |||
2638 | if (p_child->dvo_port == PORT_IDPD && |
||
2639 | p_child->device_type == DEVICE_TYPE_eDP) |
||
2640 | return true; |
||
2641 | } |
||
2642 | return false; |
||
2643 | } |
||
2644 | |||
2645 | static void |
||
2646 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
||
2647 | { |
||
3243 | Serge | 2648 | struct intel_connector *intel_connector = to_intel_connector(connector); |
2649 | |||
2330 | Serge | 2650 | intel_attach_force_audio_property(connector); |
2651 | intel_attach_broadcast_rgb_property(connector); |
||
3480 | Serge | 2652 | intel_dp->color_range_auto = true; |
3243 | Serge | 2653 | |
2654 | if (is_edp(intel_dp)) { |
||
2655 | drm_mode_create_scaling_mode_property(connector->dev); |
||
2656 | drm_object_attach_property( |
||
2657 | &connector->base, |
||
2658 | connector->dev->mode_config.scaling_mode_property, |
||
2659 | DRM_MODE_SCALE_ASPECT); |
||
2660 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
||
2661 | } |
||
2330 | Serge | 2662 | } |
2663 | |||
3243 | Serge | 2664 | static void |
2665 | intel_dp_init_panel_power_sequencer(struct drm_device *dev, |
||
2666 | struct intel_dp *intel_dp, |
||
2667 | struct edp_power_seq *out) |
||
2668 | { |
||
2669 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2670 | struct edp_power_seq cur, vbt, spec, final; |
||
2671 | u32 pp_on, pp_off, pp_div, pp; |
||
2672 | |||
2673 | /* Workaround: Need to write PP_CONTROL with the unlock key as |
||
2674 | * the very first thing. */ |
||
2675 | pp = ironlake_get_pp_control(dev_priv); |
||
2676 | I915_WRITE(PCH_PP_CONTROL, pp); |
||
2677 | |||
2678 | pp_on = I915_READ(PCH_PP_ON_DELAYS); |
||
2679 | pp_off = I915_READ(PCH_PP_OFF_DELAYS); |
||
2680 | pp_div = I915_READ(PCH_PP_DIVISOR); |
||
2681 | |||
2682 | /* Pull timing values out of registers */ |
||
2683 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
||
2684 | PANEL_POWER_UP_DELAY_SHIFT; |
||
2685 | |||
2686 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
||
2687 | PANEL_LIGHT_ON_DELAY_SHIFT; |
||
2688 | |||
2689 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
||
2690 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
||
2691 | |||
2692 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
||
2693 | PANEL_POWER_DOWN_DELAY_SHIFT; |
||
2694 | |||
2695 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
||
2696 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
||
2697 | |||
2698 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
||
2699 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
||
2700 | |||
2701 | vbt = dev_priv->edp.pps; |
||
2702 | |||
2703 | /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of |
||
2704 | * our hw here, which are all in 100usec. */ |
||
2705 | spec.t1_t3 = 210 * 10; |
||
2706 | spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ |
||
2707 | spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ |
||
2708 | spec.t10 = 500 * 10; |
||
2709 | /* This one is special and actually in units of 100ms, but zero |
||
2710 | * based in the hw (so we need to add 100 ms). But the sw vbt |
||
2711 | * table multiplies it with 1000 to make it in units of 100usec, |
||
2712 | * too. */ |
||
2713 | spec.t11_t12 = (510 + 100) * 10; |
||
2714 | |||
2715 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
||
2716 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
||
2717 | |||
2718 | /* Use the max of the register settings and vbt. If both are |
||
2719 | * unset, fall back to the spec limits. */ |
||
2720 | #define assign_final(field) final.field = (max(cur.field, vbt.field) == 0 ? \ |
||
2721 | spec.field : \ |
||
2722 | max(cur.field, vbt.field)) |
||
2723 | assign_final(t1_t3); |
||
2724 | assign_final(t8); |
||
2725 | assign_final(t9); |
||
2726 | assign_final(t10); |
||
2727 | assign_final(t11_t12); |
||
2728 | #undef assign_final |
||
2729 | |||
2730 | #define get_delay(field) (DIV_ROUND_UP(final.field, 10)) |
||
2731 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
||
2732 | intel_dp->backlight_on_delay = get_delay(t8); |
||
2733 | intel_dp->backlight_off_delay = get_delay(t9); |
||
2734 | intel_dp->panel_power_down_delay = get_delay(t10); |
||
2735 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
||
2736 | #undef get_delay |
||
2737 | |||
2738 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
||
2739 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
||
2740 | intel_dp->panel_power_cycle_delay); |
||
2741 | |||
2742 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
||
2743 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
||
2744 | |||
2745 | if (out) |
||
2746 | *out = final; |
||
2747 | } |
||
2748 | |||
2749 | static void |
||
2750 | intel_dp_init_panel_power_sequencer_registers(struct drm_device *dev, |
||
2751 | struct intel_dp *intel_dp, |
||
2752 | struct edp_power_seq *seq) |
||
2753 | { |
||
2754 | struct drm_i915_private *dev_priv = dev->dev_private; |
||
2755 | u32 pp_on, pp_off, pp_div; |
||
2756 | |||
2757 | /* And finally store the new values in the power sequencer. */ |
||
2758 | pp_on = (seq->t1_t3 << PANEL_POWER_UP_DELAY_SHIFT) | |
||
2759 | (seq->t8 << PANEL_LIGHT_ON_DELAY_SHIFT); |
||
2760 | pp_off = (seq->t9 << PANEL_LIGHT_OFF_DELAY_SHIFT) | |
||
2761 | (seq->t10 << PANEL_POWER_DOWN_DELAY_SHIFT); |
||
2762 | /* Compute the divisor for the pp clock, simply match the Bspec |
||
2763 | * formula. */ |
||
2764 | pp_div = ((100 * intel_pch_rawclk(dev))/2 - 1) |
||
2765 | << PP_REFERENCE_DIVIDER_SHIFT; |
||
2766 | pp_div |= (DIV_ROUND_UP(seq->t11_t12, 1000) |
||
2767 | << PANEL_POWER_CYCLE_DELAY_SHIFT); |
||
2768 | |||
2769 | /* Haswell doesn't have any port selection bits for the panel |
||
2770 | * power sequencer any more. */ |
||
2771 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) { |
||
2772 | if (is_cpu_edp(intel_dp)) |
||
2773 | pp_on |= PANEL_POWER_PORT_DP_A; |
||
2774 | else |
||
2775 | pp_on |= PANEL_POWER_PORT_DP_D; |
||
2776 | } |
||
2777 | |||
2778 | I915_WRITE(PCH_PP_ON_DELAYS, pp_on); |
||
2779 | I915_WRITE(PCH_PP_OFF_DELAYS, pp_off); |
||
2780 | I915_WRITE(PCH_PP_DIVISOR, pp_div); |
||
2781 | |||
2782 | DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", |
||
2783 | I915_READ(PCH_PP_ON_DELAYS), |
||
2784 | I915_READ(PCH_PP_OFF_DELAYS), |
||
2785 | I915_READ(PCH_PP_DIVISOR)); |
||
2786 | } |
||
2787 | |||
2330 | Serge | 2788 | void |
3243 | Serge | 2789 | intel_dp_init_connector(struct intel_digital_port *intel_dig_port, |
2790 | struct intel_connector *intel_connector) |
||
2330 | Serge | 2791 | { |
3243 | Serge | 2792 | struct drm_connector *connector = &intel_connector->base; |
2793 | struct intel_dp *intel_dp = &intel_dig_port->dp; |
||
2794 | struct intel_encoder *intel_encoder = &intel_dig_port->base; |
||
2795 | struct drm_device *dev = intel_encoder->base.dev; |
||
2330 | Serge | 2796 | struct drm_i915_private *dev_priv = dev->dev_private; |
3243 | Serge | 2797 | struct drm_display_mode *fixed_mode = NULL; |
2798 | struct edp_power_seq power_seq = { 0 }; |
||
2799 | enum port port = intel_dig_port->port; |
||
2330 | Serge | 2800 | const char *name = NULL; |
2801 | int type; |
||
2802 | |||
3031 | serge | 2803 | /* Preserve the current hw state. */ |
2804 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
||
3243 | Serge | 2805 | intel_dp->attached_connector = intel_connector; |
2330 | Serge | 2806 | |
3243 | Serge | 2807 | if (HAS_PCH_SPLIT(dev) && port == PORT_D) |
2330 | Serge | 2808 | if (intel_dpd_is_edp(dev)) |
2809 | intel_dp->is_pch_edp = true; |
||
2810 | |||
3243 | Serge | 2811 | /* |
2812 | * FIXME : We need to initialize built-in panels before external panels. |
||
2813 | * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup |
||
2814 | */ |
||
2815 | if (IS_VALLEYVIEW(dev) && port == PORT_C) { |
||
2330 | Serge | 2816 | type = DRM_MODE_CONNECTOR_eDP; |
2817 | intel_encoder->type = INTEL_OUTPUT_EDP; |
||
3243 | Serge | 2818 | } else if (port == PORT_A || is_pch_edp(intel_dp)) { |
2819 | type = DRM_MODE_CONNECTOR_eDP; |
||
2820 | intel_encoder->type = INTEL_OUTPUT_EDP; |
||
2330 | Serge | 2821 | } else { |
3243 | Serge | 2822 | /* The intel_encoder->type value may be INTEL_OUTPUT_UNKNOWN for |
2823 | * DDI or INTEL_OUTPUT_DISPLAYPORT for the older gens, so don't |
||
2824 | * rewrite it. |
||
2825 | */ |
||
2330 | Serge | 2826 | type = DRM_MODE_CONNECTOR_DisplayPort; |
2827 | } |
||
2828 | |||
2829 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
||
2830 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
||
2831 | |||
2832 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
||
2833 | connector->interlace_allowed = true; |
||
2834 | connector->doublescan_allowed = 0; |
||
2835 | |||
3243 | Serge | 2836 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
2837 | ironlake_panel_vdd_work); |
||
2330 | Serge | 2838 | |
2839 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
||
2840 | drm_sysfs_connector_add(connector); |
||
2841 | |||
3480 | Serge | 2842 | if (HAS_DDI(dev)) |
3243 | Serge | 2843 | intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; |
2844 | else |
||
3031 | serge | 2845 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
2846 | |||
3243 | Serge | 2847 | |
2330 | Serge | 2848 | /* Set up the DDC bus. */ |
3031 | serge | 2849 | switch (port) { |
2850 | case PORT_A: |
||
2330 | Serge | 2851 | name = "DPDDC-A"; |
2852 | break; |
||
3031 | serge | 2853 | case PORT_B: |
3480 | Serge | 2854 | dev_priv->hotplug_supported_mask |= PORTB_HOTPLUG_INT_STATUS; |
2330 | Serge | 2855 | name = "DPDDC-B"; |
2856 | break; |
||
3031 | serge | 2857 | case PORT_C: |
3480 | Serge | 2858 | dev_priv->hotplug_supported_mask |= PORTC_HOTPLUG_INT_STATUS; |
2330 | Serge | 2859 | name = "DPDDC-C"; |
2860 | break; |
||
3031 | serge | 2861 | case PORT_D: |
3480 | Serge | 2862 | dev_priv->hotplug_supported_mask |= PORTD_HOTPLUG_INT_STATUS; |
2330 | Serge | 2863 | name = "DPDDC-D"; |
2864 | break; |
||
3031 | serge | 2865 | default: |
2866 | WARN(1, "Invalid port %c\n", port_name(port)); |
||
2867 | break; |
||
2330 | Serge | 2868 | } |
2869 | |||
3243 | Serge | 2870 | if (is_edp(intel_dp)) |
2871 | intel_dp_init_panel_power_sequencer(dev, intel_dp, &power_seq); |
||
2330 | Serge | 2872 | |
3031 | serge | 2873 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
2874 | |||
3243 | Serge | 2875 | /* Cache DPCD and EDID for edp. */ |
3031 | serge | 2876 | if (is_edp(intel_dp)) { |
2877 | bool ret; |
||
3243 | Serge | 2878 | struct drm_display_mode *scan; |
3031 | serge | 2879 | struct edid *edid; |
2880 | |||
2330 | Serge | 2881 | ironlake_edp_panel_vdd_on(intel_dp); |
2882 | ret = intel_dp_get_dpcd(intel_dp); |
||
2342 | Serge | 2883 | ironlake_edp_panel_vdd_off(intel_dp, false); |
2884 | |||
2330 | Serge | 2885 | if (ret) { |
2886 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
||
2887 | dev_priv->no_aux_handshake = |
||
2888 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
||
2889 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
||
2890 | } else { |
||
2891 | /* if this fails, presume the device is a ghost */ |
||
2892 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
||
3243 | Serge | 2893 | intel_dp_encoder_destroy(&intel_encoder->base); |
2894 | intel_dp_destroy(connector); |
||
2330 | Serge | 2895 | return; |
2896 | } |
||
3031 | serge | 2897 | |
3243 | Serge | 2898 | /* We now know it's not a ghost, init power sequence regs. */ |
2899 | intel_dp_init_panel_power_sequencer_registers(dev, intel_dp, |
||
2900 | &power_seq); |
||
2901 | |||
3031 | serge | 2902 | ironlake_edp_panel_vdd_on(intel_dp); |
2903 | edid = drm_get_edid(connector, &intel_dp->adapter); |
||
2904 | if (edid) { |
||
3243 | Serge | 2905 | if (drm_add_edid_modes(connector, edid)) { |
2906 | drm_mode_connector_update_edid_property(connector, edid); |
||
3031 | serge | 2907 | drm_edid_to_eld(connector, edid); |
3243 | Serge | 2908 | } else { |
2909 | kfree(edid); |
||
2910 | edid = ERR_PTR(-EINVAL); |
||
2911 | } |
||
2912 | } else { |
||
2913 | edid = ERR_PTR(-ENOENT); |
||
3031 | serge | 2914 | } |
3243 | Serge | 2915 | intel_connector->edid = edid; |
2916 | |||
2917 | /* prefer fixed mode from EDID if available */ |
||
2918 | list_for_each_entry(scan, &connector->probed_modes, head) { |
||
2919 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
||
2920 | fixed_mode = drm_mode_duplicate(dev, scan); |
||
2921 | break; |
||
2922 | } |
||
2923 | } |
||
2924 | |||
2925 | /* fallback to VBT if available for eDP */ |
||
2926 | if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) { |
||
2927 | fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
||
2928 | if (fixed_mode) |
||
2929 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
||
2930 | } |
||
2931 | |||
3031 | serge | 2932 | ironlake_edp_panel_vdd_off(intel_dp, false); |
2330 | Serge | 2933 | } |
2934 | |||
2935 | if (is_edp(intel_dp)) { |
||
3243 | Serge | 2936 | intel_panel_init(&intel_connector->panel, fixed_mode); |
2937 | intel_panel_setup_backlight(connector); |
||
2330 | Serge | 2938 | } |
2939 | |||
2940 | intel_dp_add_properties(intel_dp, connector); |
||
2941 | |||
2942 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
||
2943 | * 0xd. Failure to do so will result in spurious interrupts being |
||
2944 | * generated on the port when a cable is not attached. |
||
2945 | */ |
||
2946 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
||
2947 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
||
2948 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
||
2949 | } |
||
2950 | } |
||
3243 | Serge | 2951 | |
2952 | void |
||
2953 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) |
||
2954 | { |
||
2955 | struct intel_digital_port *intel_dig_port; |
||
2956 | struct intel_encoder *intel_encoder; |
||
2957 | struct drm_encoder *encoder; |
||
2958 | struct intel_connector *intel_connector; |
||
2959 | |||
2960 | intel_dig_port = kzalloc(sizeof(struct intel_digital_port), GFP_KERNEL); |
||
2961 | if (!intel_dig_port) |
||
2962 | return; |
||
2963 | |||
2964 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
||
2965 | if (!intel_connector) { |
||
2966 | kfree(intel_dig_port); |
||
2967 | return; |
||
2968 | } |
||
2969 | |||
2970 | intel_encoder = &intel_dig_port->base; |
||
2971 | encoder = &intel_encoder->base; |
||
2972 | |||
2973 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
||
2974 | DRM_MODE_ENCODER_TMDS); |
||
2975 | drm_encoder_helper_add(&intel_encoder->base, &intel_dp_helper_funcs); |
||
2976 | |||
2977 | intel_encoder->enable = intel_enable_dp; |
||
2978 | intel_encoder->pre_enable = intel_pre_enable_dp; |
||
2979 | intel_encoder->disable = intel_disable_dp; |
||
2980 | intel_encoder->post_disable = intel_post_disable_dp; |
||
2981 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
||
2982 | |||
2983 | intel_dig_port->port = port; |
||
2984 | intel_dig_port->dp.output_reg = output_reg; |
||
2985 | |||
2986 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
||
2987 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
||
2988 | intel_encoder->cloneable = false; |
||
2989 | intel_encoder->hot_plug = intel_dp_hot_plug; |
||
2990 | |||
2991 | intel_dp_init_connector(intel_dig_port, intel_connector); |
||
2992 | }><>><>><>><>><>><>><>><>><>>>>>>>>>>><>>=>=><=>=>=>>>><>><>><>>><>>><>>><>><>><>>>>>><>>> |