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5060 | serge | 1 | /* |
2 | * Copyright © 2014 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Mika Kuoppala |
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25 | * |
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26 | */ |
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27 | |||
28 | #include "i915_drv.h" |
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29 | #include "intel_renderstate.h" |
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30 | |||
31 | struct render_state { |
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32 | const struct intel_renderstate_rodata *rodata; |
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33 | struct drm_i915_gem_object *obj; |
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34 | u64 ggtt_offset; |
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35 | int gen; |
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36 | }; |
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37 | |||
38 | static const struct intel_renderstate_rodata * |
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39 | render_state_get_rodata(struct drm_device *dev, const int gen) |
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40 | { |
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41 | switch (gen) { |
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42 | case 6: |
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43 | return &gen6_null_state; |
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44 | case 7: |
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45 | return &gen7_null_state; |
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46 | case 8: |
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47 | return &gen8_null_state; |
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48 | } |
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49 | |||
50 | return NULL; |
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51 | } |
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52 | |||
53 | static int render_state_init(struct render_state *so, struct drm_device *dev) |
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54 | { |
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55 | int ret; |
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56 | |||
57 | so->gen = INTEL_INFO(dev)->gen; |
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58 | so->rodata = render_state_get_rodata(dev, so->gen); |
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59 | if (so->rodata == NULL) |
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60 | return 0; |
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61 | |||
62 | if (so->rodata->batch_items * 4 > 4096) |
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63 | return -EINVAL; |
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64 | |||
65 | so->obj = i915_gem_alloc_object(dev, 4096); |
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66 | if (so->obj == NULL) |
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67 | return -ENOMEM; |
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68 | |||
69 | ret = i915_gem_obj_ggtt_pin(so->obj, 4096, 0); |
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70 | if (ret) |
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71 | goto free_gem; |
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72 | |||
73 | so->ggtt_offset = i915_gem_obj_ggtt_offset(so->obj); |
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74 | return 0; |
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75 | |||
76 | free_gem: |
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77 | drm_gem_object_unreference(&so->obj->base); |
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78 | return ret; |
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79 | } |
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80 | |||
81 | static int render_state_setup(struct render_state *so) |
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82 | { |
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83 | const struct intel_renderstate_rodata *rodata = so->rodata; |
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84 | unsigned int i = 0, reloc_index = 0; |
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85 | struct page *page; |
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86 | u32 *d; |
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87 | int ret; |
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88 | |||
89 | ret = i915_gem_object_set_to_cpu_domain(so->obj, true); |
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90 | if (ret) |
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91 | return ret; |
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92 | |||
93 | page = sg_page(so->obj->pages->sgl); |
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94 | d = kmap(page); |
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95 | |||
96 | while (i < rodata->batch_items) { |
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97 | u32 s = rodata->batch[i]; |
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98 | |||
99 | if (i * 4 == rodata->reloc[reloc_index]) { |
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100 | u64 r = s + so->ggtt_offset; |
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101 | s = lower_32_bits(r); |
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102 | if (so->gen >= 8) { |
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103 | if (i + 1 >= rodata->batch_items || |
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104 | rodata->batch[i + 1] != 0) |
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105 | return -EINVAL; |
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106 | |||
107 | d[i++] = s; |
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108 | s = upper_32_bits(r); |
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109 | } |
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110 | |||
111 | reloc_index++; |
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112 | } |
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113 | |||
114 | d[i++] = s; |
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115 | } |
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116 | FreeKernelSpace(d); |
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117 | |||
118 | ret = i915_gem_object_set_to_gtt_domain(so->obj, false); |
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119 | if (ret) |
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120 | return ret; |
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121 | |||
122 | if (rodata->reloc[reloc_index] != -1) { |
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123 | DRM_ERROR("only %d relocs resolved\n", reloc_index); |
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124 | return -EINVAL; |
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125 | } |
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126 | |||
127 | return 0; |
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128 | } |
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129 | |||
130 | static void render_state_fini(struct render_state *so) |
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131 | { |
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132 | i915_gem_object_ggtt_unpin(so->obj); |
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133 | drm_gem_object_unreference(&so->obj->base); |
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134 | } |
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135 | |||
136 | int i915_gem_render_state_init(struct intel_engine_cs *ring) |
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137 | { |
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138 | struct render_state so; |
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139 | int ret; |
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140 | |||
141 | if (WARN_ON(ring->id != RCS)) |
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142 | return -ENOENT; |
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143 | |||
144 | ret = render_state_init(&so, ring->dev); |
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145 | if (ret) |
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146 | return ret; |
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147 | |||
148 | if (so.rodata == NULL) |
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149 | return 0; |
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150 | |||
151 | ret = render_state_setup(&so); |
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152 | if (ret) |
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153 | goto out; |
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154 | |||
155 | ret = ring->dispatch_execbuffer(ring, |
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156 | so.ggtt_offset, |
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157 | so.rodata->batch_items * 4, |
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158 | I915_DISPATCH_SECURE); |
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159 | if (ret) |
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160 | goto out; |
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161 | |||
162 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), ring); |
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163 | |||
164 | ret = __i915_add_request(ring, NULL, so.obj, NULL); |
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165 | /* __i915_add_request moves object to inactive if it fails */ |
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166 | out: |
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167 | render_state_fini(&so); |
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168 | return ret; |
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169 | }> |