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2326 | Serge | 1 | /* |
2 | * Copyright © 2008 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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21 | * IN THE SOFTWARE. |
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22 | * |
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23 | * Authors: |
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24 | * Eric Anholt |
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25 | * |
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26 | */ |
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27 | |||
28 | #include "drmP.h" |
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29 | #include "drm.h" |
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2330 | Serge | 30 | #include "i915_drm.h" |
2326 | Serge | 31 | #include "i915_drv.h" |
32 | //#include "i915_trace.h" |
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33 | #include "intel_drv.h" |
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34 | //#include |
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2330 | Serge | 35 | #include |
2326 | Serge | 36 | //#include |
37 | #include |
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38 | |||
39 | #define I915_EXEC_CONSTANTS_MASK (3<<6) |
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40 | #define I915_EXEC_CONSTANTS_REL_GENERAL (0<<6) /* default */ |
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41 | #define I915_EXEC_CONSTANTS_ABSOLUTE (1<<6) |
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42 | #define I915_EXEC_CONSTANTS_REL_SURFACE (2<<6) /* gen4/5 only */ |
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43 | |||
44 | |||
45 | /** |
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46 | * i915_gem_clear_fence_reg - clear out fence register info |
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47 | * @obj: object to clear |
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48 | * |
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49 | * Zeroes out the fence register itself and clears out the associated |
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50 | * data structures in dev_priv and obj. |
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51 | */ |
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52 | static void |
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53 | i915_gem_clear_fence_reg(struct drm_device *dev, |
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54 | struct drm_i915_fence_reg *reg) |
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55 | { |
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56 | drm_i915_private_t *dev_priv = dev->dev_private; |
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57 | uint32_t fence_reg = reg - dev_priv->fence_regs; |
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58 | |||
59 | switch (INTEL_INFO(dev)->gen) { |
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60 | case 7: |
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61 | case 6: |
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62 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + fence_reg*8, 0); |
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63 | break; |
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64 | case 5: |
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65 | case 4: |
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66 | I915_WRITE64(FENCE_REG_965_0 + fence_reg*8, 0); |
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67 | break; |
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68 | case 3: |
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69 | if (fence_reg >= 8) |
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70 | fence_reg = FENCE_REG_945_8 + (fence_reg - 8) * 4; |
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71 | else |
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72 | case 2: |
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73 | fence_reg = FENCE_REG_830_0 + fence_reg * 4; |
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74 | |||
75 | I915_WRITE(fence_reg, 0); |
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76 | break; |
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77 | } |
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78 | |||
79 | list_del_init(®->lru_list); |
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80 | reg->obj = NULL; |
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81 | reg->setup_seqno = 0; |
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82 | } |
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83 | |||
84 | |||
85 | static void |
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86 | init_ring_lists(struct intel_ring_buffer *ring) |
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87 | { |
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88 | INIT_LIST_HEAD(&ring->active_list); |
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89 | INIT_LIST_HEAD(&ring->request_list); |
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90 | INIT_LIST_HEAD(&ring->gpu_write_list); |
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91 | } |
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92 | |||
93 | |||
94 | void |
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95 | i915_gem_load(struct drm_device *dev) |
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96 | { |
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97 | int i; |
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98 | drm_i915_private_t *dev_priv = dev->dev_private; |
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99 | |||
100 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
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101 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
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102 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
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103 | INIT_LIST_HEAD(&dev_priv->mm.pinned_list); |
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104 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
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105 | INIT_LIST_HEAD(&dev_priv->mm.deferred_free_list); |
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106 | INIT_LIST_HEAD(&dev_priv->mm.gtt_list); |
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107 | for (i = 0; i < I915_NUM_RINGS; i++) |
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108 | init_ring_lists(&dev_priv->ring[i]); |
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109 | for (i = 0; i < 16; i++) |
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110 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
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111 | // INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
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112 | // i915_gem_retire_work_handler); |
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113 | // init_completion(&dev_priv->error_completion); |
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114 | |||
115 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
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116 | if (IS_GEN3(dev)) { |
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117 | u32 tmp = I915_READ(MI_ARB_STATE); |
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118 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { |
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119 | /* arb state is a masked write, so set bit + bit in mask */ |
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120 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); |
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121 | I915_WRITE(MI_ARB_STATE, tmp); |
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122 | } |
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123 | } |
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124 | |||
125 | dev_priv->relative_constants_mode = I915_EXEC_CONSTANTS_REL_GENERAL; |
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126 | |||
127 | if (INTEL_INFO(dev)->gen >= 4 || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
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128 | dev_priv->num_fence_regs = 16; |
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129 | else |
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130 | dev_priv->num_fence_regs = 8; |
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131 | |||
132 | /* Initialize fence registers to zero */ |
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133 | for (i = 0; i < dev_priv->num_fence_regs; i++) { |
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134 | i915_gem_clear_fence_reg(dev, &dev_priv->fence_regs[i]); |
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135 | } |
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136 | |||
137 | i915_gem_detect_bit_6_swizzle(dev); |
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138 | // init_waitqueue_head(&dev_priv->pending_flip_queue); |
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139 | |||
140 | dev_priv->mm.interruptible = true; |
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141 | |||
142 | // dev_priv->mm.inactive_shrinker.shrink = i915_gem_inactive_shrink; |
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143 | // dev_priv->mm.inactive_shrinker.seeks = DEFAULT_SEEKS; |
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144 | // register_shrinker(&dev_priv->mm.inactive_shrinker); |
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145 | }>><>>>6)><6)>6) |
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146 | |||
147 | |||
148 |