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#include 

#include 

//#include "xf86.h"

#include "uxa/intel.h"

#include "i830_reg.h"

#include "i965_reg.h"

#include "brw_defines.h"

#include "brw_structs.h"

#include 

#include 

#define PictOpSrc               1

#define PictOpDst               2

#define PictOpOver              3

#define PictOpOverReverse       4

#define PictOpIn                5

#define PictOpInReverse         6

#define PictOpOut               7

#define PictOpOutReverse        8

#define PictOpAtop              9

#define PictOpAtopReverse       10

#define PictOpXor               11

#define PictOpAdd               12

#define PictOpSaturate          13

#define PictOpMaximum           13

__LOCK_INIT_RECURSIVE(, __uxa_lock);

{

    struct list     entry;

    uint32_t        width;

    uint32_t        height;

    void           *data;

    uint32_t        pitch;

    drm_intel_bo   *bo;

    uint32_t        bo_size;

    uint32_t        flags;

}surface_t;

{

    return 0;

};

{

	intel_screen_private *intel = intel_get_screen_private();

		intel->vertex_flush(intel);

}

{

	struct intel_screen_private *intel = intel_get_screen_private();

	drm_intel_bo *bo;

    surface_t    *sf;

    unsigned int size;

    list_for_each_entry(sf, &sf_list, entry)

    {

        if (sf->bo->handle == handle)

        {

            bitmap->handle = (uint32_t)sf;

            break;

        }

    }

    __lock_release_recursive(__uxa_lock);

        return 0;

    if(sf == NULL)

        goto err_1;

    sf->height  = bitmap->height;

    sf->data    = NULL;

    sf->pitch   = bitmap->pitch;

    sf->bo      = bo;

    sf->bo_size = size;

    sf->flags   = bitmap->flags;

};

{

    sna_bitmap_from_handle(bitmap, handle);

};

                  int w, int h, int src_x, int src_y)

{

//    DBG("%s\n", __FUNCTION__);

    struct intel_pixmap privSrc;

    struct _Picture pictSrc, pictDst;

	struct intel_screen_private *intel = intel_get_screen_private();

    get_proc_info(proc_info);

    winx = *(uint32_t*)(proc_info+34);

    winy = *(uint32_t*)(proc_info+38);

    memset(&pixMask, 0, sizeof(pixMask));

    memset(&privSrc, 0, sizeof(pixSrc));

    memset(&pictDst, 0, sizeof(pictDst));

    pixSrc.drawable.width        = sf->width;

    pixSrc.drawable.height       = sf->height;

    pixSrc.devKind               = sf->pitch;

    pixSrc.private               = &privSrc;

    privSrc.bo = sf->bo;

    privSrc.stride = sf->pitch;

    privSrc.tiling = I915_TILING_X;

    pictSrc.filter     = PictFilterNearest;

    pictSrc.repeatType = RepeatNone;

    pictDst.filter = PictFilterNearest;

    pictDst.repeatType = RepeatNone;

                           &pixSrc, NULL, &fb_pixmap);

                    dst_x+winx, dst_y+winy, w, h);

};

{

    struct drm_i915_fb_info fb;

    static struct intel_pixmap ipix;

    int ret;

	if( ret != 0 )

	    return ret;

    if(intel->front_buffer == NULL)

        return -1;

    list_init(&ipix.batch);

    ipix.stride = fb.pitch;

    ipix.tiling = fb.tiling;

    ipix.pinned = PIN_SCANOUT;

    printf("size %d, offset %d handle %d\n",ipix.bo->size, ipix.bo->offset, ipix.bo->handle);

    fb_pixmap.drawable.width  = fb.width;

    fb_pixmap.drawable.height = fb.height;

    fb_pixmap.devKind = fb.pitch;

    fb_pixmap.private = &ipix;

}

{

    struct drm_i915_fb_info fb;

    struct intel_pixmap *ipix;

    size_t size;

    int ret;

	if( ret != 0 )

	    return ret;

    ipix->stride = fb.pitch;

    ipix->tiling = fb.tiling;

    fb_pixmap.drawable.height = fb.height;

    fb_pixmap.devKind = fb.pitch;

};

{

    static struct pci_device device;

	struct intel_screen_private *intel = intel_get_screen_private();

    int caps = 0;

        goto done;

    io.io_code  = SRV_GET_PCI_INFO;

    io.input    = &device;

    io.inp_size = sizeof(device);

    io.output   = NULL;

    io.out_size = 0;

        goto err1;

    if (intel == NULL)

        goto err1;

    memset(intel, 0, sizeof(*intel));

  	intel->info = intel_detect_chipset(intel->PciInfo);

    intel->scrn = service;

    if(intel->bufmgr == NULL)

    {

		printf("Memory manager initialization failed\n");

		goto err1;

    };

		intel->wa_scratch_bo =

			drm_intel_bo_alloc(intel->bufmgr, "wa scratch",

					   4096, 4096);

	}

        goto err1;

		gen4_render_state_init();

		printf("Hardware acceleration initialization failed\n");

		goto err1;

	}

//    caps = sna_device->render.caps;

    __lock_release_recursive(__uxa_lock);

    return caps;

}

gen6_context_switch(intel_screen_private *intel,

		    int new_mode)

{

	intel_batch_submit(intel->scrn);

}

gen5_context_switch(intel_screen_private *intel,

		    int new_mode)

{

	/* Ironlake has a limitation that a 3D or Media command can't

	 * be the first command after a BLT, unless it's

	 * non-pipelined.  Instead of trying to track it and emit a

	 * command at the right time, we just emit a dummy

	 * non-pipelined 3D instruction after each blit.

	 */

		OUT_BATCH(MI_FLUSH |

			  MI_STATE_INSTRUCTION_CACHE_FLUSH |

			  MI_INHIBIT_RENDER_CACHE_FLUSH);

	} else {

		OUT_BATCH(CMD_POLY_STIPPLE_OFFSET << 16);

		OUT_BATCH(0);

	}

}

gen4_context_switch(intel_screen_private *intel,

		    int new_mode)

{

	if (new_mode == I915_EXEC_BLT) {

		OUT_BATCH(MI_FLUSH |

			  MI_STATE_INSTRUCTION_CACHE_FLUSH |

			  MI_INHIBIT_RENDER_CACHE_FLUSH);

	}

}

intel_limits_init(intel_screen_private *intel)

{

	/* Limits are described in the BLT engine chapter under Graphics Data Size

	 * Limitations, and the descriptions of SURFACE_STATE, 3DSTATE_BUFFER_INFO,

	 * 3DSTATE_DRAWING_RECTANGLE, 3DSTATE_MAP_INFO, and 3DSTATE_MAP_INFO.

	 *

	 * i845 through i965 limits 2D rendering to 65536 lines and pitch of 32768.

	 *

	 * i965 limits 3D surface to (2*element size)-aligned offset if un-tiled.

	 * i965 limits 3D surface to 4kB-aligned offset if tiled.

	 * i965 limits 3D surfaces to w,h of ?,8192.

	 * i965 limits 3D surface to pitch of 1B - 128kB.

	 * i965 limits 3D surface pitch alignment to 1 or 2 times the element size.

	 * i965 limits 3D surface pitch alignment to 512B if tiled.

	 * i965 limits 3D destination drawing rect to w,h of 8192,8192.

	 *

	 * i915 limits 3D textures to 4B-aligned offset if un-tiled.

	 * i915 limits 3D textures to ~4kB-aligned offset if tiled.

	 * i915 limits 3D textures to width,height of 2048,2048.

	 * i915 limits 3D textures to pitch of 16B - 8kB, in dwords.

	 * i915 limits 3D destination to ~4kB-aligned offset if tiled.

	 * i915 limits 3D destination to pitch of 16B - 8kB, in dwords, if un-tiled.

	 * i915 limits 3D destination to pitch 64B-aligned if used with depth.

	 * i915 limits 3D destination to pitch of 512B - 8kB, in tiles, if tiled.

	 * i915 limits 3D destination to POT aligned pitch if tiled.

	 * i915 limits 3D destination drawing rect to w,h of 2048,2048.

	 *

	 * i845 limits 3D textures to 4B-aligned offset if un-tiled.

	 * i845 limits 3D textures to ~4kB-aligned offset if tiled.

	 * i845 limits 3D textures to width,height of 2048,2048.

	 * i845 limits 3D textures to pitch of 4B - 8kB, in dwords.

	 * i845 limits 3D destination to 4B-aligned offset if un-tiled.

	 * i845 limits 3D destination to ~4kB-aligned offset if tiled.

	 * i845 limits 3D destination to pitch of 8B - 8kB, in dwords.

	 * i845 limits 3D destination drawing rect to w,h of 2048,2048.

	 *

	 * For the tiled issues, the only tiled buffer we draw to should be

	 * the front, which will have an appropriate pitch/offset already set up,

	 * so UXA doesn't need to worry.

	 */

	if (INTEL_INFO(intel)->gen >= 040) {

		intel->accel_pixmap_offset_alignment = 4 * 2;

		intel->accel_max_x = 8192;

		intel->accel_max_y = 8192;

	} else {

		intel->accel_pixmap_offset_alignment = 4;

		intel->accel_max_x = 2048;

		intel->accel_max_y = 2048;

	}

}

{

	intel_screen_private *intel = intel_get_screen_private();

	intel->vertex_count = 0;

	intel->vertex_offset = 0;

	intel->vertex_used = 0;

	intel->floats_per_vertex = 0;

	intel->last_floats_per_vertex = 0;

	intel->vertex_bo = NULL;

	intel->surface_used = 0;

	intel->surface_reloc = 0;

	intel->uxa_driver->check_composite = i965_check_composite;

	intel->uxa_driver->check_composite_texture = i965_check_composite_texture;

	intel->uxa_driver->prepare_composite = i965_prepare_composite;

	intel->uxa_driver->composite = i965_composite;

	intel->uxa_driver->done_composite = i830_done_composite;

*/

	intel->vertex_flush = i965_vertex_flush;

	intel->batch_flush = i965_batch_flush;

	intel->batch_commit_notify = i965_batch_commit_notify;

		intel->context_switch = gen4_context_switch;

	} else if (IS_GEN5(intel)) {

		intel->context_switch = gen5_context_switch;

	} else {

		intel->context_switch = gen6_context_switch;

	}

}

	.gen = -1,

};

	.gen = 030,

};

static const struct intel_device_info intel_i945_info = {

	.gen = 031,

};

	.gen = 033,

};

	.gen = 040,

};

	.gen = 045,

};

	.gen = 050,

};

	.gen = 060,

};

	.gen = 070,

};

	.gen = 071,

};

	.gen = 075,

};

    { 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0x3 << 16, 0xff << 16, (intptr_t)(i) }

	INTEL_I915GM_IDS(&intel_i915_info),

	INTEL_I945G_IDS(&intel_i945_info),

	INTEL_I945GM_IDS(&intel_i945_info),

	INTEL_PINEVIEW_IDS(&intel_g33_info),

	INTEL_I965GM_IDS(&intel_i965_info),

	INTEL_GM45_IDS(&intel_g4x_info),

	INTEL_IRONLAKE_M_IDS(&intel_ironlake_info),

	INTEL_SNB_M_IDS(&intel_sandybridge_info),

	INTEL_IVB_M_IDS(&intel_ivybridge_info),

	INTEL_HSW_M_IDS(&intel_haswell_info),

	INTEL_VLV_M_IDS(&intel_valleyview_info),

};

{

    while(list->device_id)

    {

        if(dev==list->device_id)

            return list;

        list++;

    }

    return NULL;

}

intel_detect_chipset(struct pci_device *pci)

{

    const struct pci_id_match *ent = NULL;

        return (const struct intel_device_info*)ent->match_data;

    else

        return &intel_generic_info;

}