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Rev | Author | Line No. | Line |
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3254 | Serge | 1 | //#include "../bitmap.h" |
2 | |||
3 | #include |
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4 | #include |
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5 | |||
6 | #include "sna.h" |
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7 | |||
8 | |||
9 | const struct intel_device_info * |
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10 | intel_detect_chipset(struct pci_device *pci); |
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11 | |||
12 | //struct kgem_bo *create_bo(bitmap_t *bitmap); |
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13 | |||
14 | static bool sna_solid_cache_init(struct sna *sna); |
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15 | |||
16 | struct sna *sna_device; |
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17 | |||
18 | void no_render_init(struct sna *sna) |
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19 | { |
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20 | struct sna_render *render = &sna->render; |
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21 | |||
22 | memset (render,0, sizeof (*render)); |
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23 | |||
24 | render->prefer_gpu = PREFER_GPU_BLT; |
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25 | |||
26 | render->vertices = render->vertex_data; |
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27 | render->vertex_size = ARRAY_SIZE(render->vertex_data); |
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28 | |||
29 | // render->composite = no_render_composite; |
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30 | |||
31 | // render->copy_boxes = no_render_copy_boxes; |
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32 | // render->copy = no_render_copy; |
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33 | |||
34 | // render->fill_boxes = no_render_fill_boxes; |
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35 | // render->fill = no_render_fill; |
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36 | // render->fill_one = no_render_fill_one; |
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37 | // render->clear = no_render_clear; |
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38 | |||
39 | // render->reset = no_render_reset; |
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40 | // render->flush = no_render_flush; |
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41 | // render->fini = no_render_fini; |
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42 | |||
43 | // sna->kgem.context_switch = no_render_context_switch; |
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44 | // sna->kgem.retire = no_render_retire; |
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45 | |||
46 | // if (sna->kgem.gen >= 60) |
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47 | sna->kgem.ring = KGEM_RENDER; |
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48 | |||
49 | sna_vertex_init(sna); |
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50 | } |
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51 | |||
52 | void sna_vertex_init(struct sna *sna) |
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53 | { |
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54 | // pthread_mutex_init(&sna->render.lock, NULL); |
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55 | // pthread_cond_init(&sna->render.wait, NULL); |
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56 | sna->render.active = 0; |
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57 | } |
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58 | |||
59 | bool sna_accel_init(struct sna *sna) |
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60 | { |
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61 | const char *backend; |
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62 | |||
63 | // list_init(&sna->deferred_free); |
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64 | // list_init(&sna->dirty_pixmaps); |
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65 | // list_init(&sna->active_pixmaps); |
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66 | // list_init(&sna->inactive_clock[0]); |
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67 | // list_init(&sna->inactive_clock[1]); |
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68 | |||
69 | // sna_accel_install_timers(sna); |
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70 | |||
71 | |||
72 | backend = "no"; |
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73 | no_render_init(sna); |
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74 | |||
75 | if (sna->info->gen >= 0100) { |
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76 | /* } else if (sna->info->gen >= 070) { |
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77 | if (gen7_render_init(sna)) |
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78 | backend = "IvyBridge"; */ |
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79 | } else if (sna->info->gen >= 060) { |
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80 | if (gen6_render_init(sna)) |
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81 | backend = "SandyBridge"; |
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82 | /* } else if (sna->info->gen >= 050) { |
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83 | if (gen5_render_init(sna)) |
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84 | backend = "Ironlake"; |
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85 | } else if (sna->info->gen >= 040) { |
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86 | if (gen4_render_init(sna)) |
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87 | backend = "Broadwater/Crestline"; |
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88 | } else if (sna->info->gen >= 030) { |
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89 | if (gen3_render_init(sna)) |
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90 | backend = "gen3"; |
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91 | } else if (sna->info->gen >= 020) { |
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92 | if (gen2_render_init(sna)) |
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93 | backend = "gen2"; */ |
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94 | } |
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95 | |||
96 | DBG(("%s(backend=%s, prefer_gpu=%x)\n", |
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97 | __FUNCTION__, backend, sna->render.prefer_gpu)); |
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98 | |||
99 | kgem_reset(&sna->kgem); |
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100 | |||
101 | // if (!sna_solid_cache_init(sna)) |
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102 | // return false; |
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103 | |||
104 | sna_device = sna; |
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105 | #if 0 |
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106 | { |
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107 | struct kgem_bo *screen_bo; |
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108 | bitmap_t screen; |
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109 | |||
110 | screen.pitch = 1024*4; |
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111 | screen.gaddr = 0; |
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112 | screen.width = 1024; |
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113 | screen.height = 768; |
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114 | screen.obj = (void*)-1; |
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115 | |||
116 | screen_bo = create_bo(&screen); |
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117 | |||
118 | sna->render.clear(sna, &screen, screen_bo); |
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119 | } |
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120 | #endif |
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121 | |||
122 | return true; |
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123 | } |
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124 | |||
125 | int sna_init(uint32_t service) |
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126 | { |
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127 | ioctl_t io; |
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128 | |||
129 | static struct pci_device device; |
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130 | struct sna *sna; |
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131 | |||
132 | DBG(("%s\n", __FUNCTION__)); |
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133 | |||
134 | sna = malloc(sizeof(struct sna)); |
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135 | if (sna == NULL) |
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136 | return false; |
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137 | |||
138 | io.handle = service; |
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3256 | Serge | 139 | io.io_code = SRV_GET_PCI_INFO; |
3254 | Serge | 140 | io.input = &device; |
141 | io.inp_size = sizeof(device); |
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142 | io.output = NULL; |
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143 | io.out_size = 0; |
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144 | |||
145 | if (call_service(&io)!=0) |
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146 | return false; |
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147 | |||
148 | sna->PciInfo = &device; |
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149 | |||
150 | sna->info = intel_detect_chipset(sna->PciInfo); |
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151 | |||
152 | kgem_init(&sna->kgem, service, sna->PciInfo, sna->info->gen); |
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153 | /* |
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154 | if (!xf86ReturnOptValBool(sna->Options, |
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155 | OPTION_RELAXED_FENCING, |
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156 | sna->kgem.has_relaxed_fencing)) { |
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157 | xf86DrvMsg(scrn->scrnIndex, |
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158 | sna->kgem.has_relaxed_fencing ? X_CONFIG : X_PROBED, |
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159 | "Disabling use of relaxed fencing\n"); |
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160 | sna->kgem.has_relaxed_fencing = 0; |
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161 | } |
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162 | if (!xf86ReturnOptValBool(sna->Options, |
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163 | OPTION_VMAP, |
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164 | sna->kgem.has_vmap)) { |
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165 | xf86DrvMsg(scrn->scrnIndex, |
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166 | sna->kgem.has_vmap ? X_CONFIG : X_PROBED, |
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167 | "Disabling use of vmap\n"); |
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168 | sna->kgem.has_vmap = 0; |
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169 | } |
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170 | */ |
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171 | |||
172 | /* Disable tiling by default */ |
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173 | sna->tiling = SNA_TILING_DISABLE; |
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174 | |||
175 | /* Default fail-safe value of 75 Hz */ |
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176 | // sna->vblank_interval = 1000 * 1000 * 1000 / 75; |
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177 | |||
178 | sna->flags = 0; |
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179 | |||
180 | return sna_accel_init(sna); |
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181 | } |
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182 | |||
183 | #if 0 |
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184 | |||
185 | static bool sna_solid_cache_init(struct sna *sna) |
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186 | { |
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187 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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188 | |||
189 | DBG(("%s\n", __FUNCTION__)); |
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190 | |||
191 | cache->cache_bo = |
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192 | kgem_create_linear(&sna->kgem, sizeof(cache->color)); |
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193 | if (!cache->cache_bo) |
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194 | return FALSE; |
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195 | |||
196 | /* |
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197 | * Initialise [0] with white since it is very common and filling the |
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198 | * zeroth slot simplifies some of the checks. |
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199 | */ |
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200 | cache->color[0] = 0xffffffff; |
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201 | cache->bo[0] = kgem_create_proxy(cache->cache_bo, 0, sizeof(uint32_t)); |
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202 | cache->bo[0]->pitch = 4; |
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203 | cache->dirty = 1; |
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204 | cache->size = 1; |
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205 | cache->last = 0; |
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206 | |||
207 | return TRUE; |
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208 | } |
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209 | |||
210 | void |
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211 | sna_render_flush_solid(struct sna *sna) |
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212 | { |
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213 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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214 | |||
215 | DBG(("sna_render_flush_solid(size=%d)\n", cache->size)); |
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216 | assert(cache->dirty); |
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217 | assert(cache->size); |
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218 | |||
219 | kgem_bo_write(&sna->kgem, cache->cache_bo, |
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220 | cache->color, cache->size*sizeof(uint32_t)); |
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221 | cache->dirty = 0; |
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222 | cache->last = 0; |
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223 | } |
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224 | |||
225 | static void |
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226 | sna_render_finish_solid(struct sna *sna, bool force) |
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227 | { |
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228 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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229 | int i; |
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230 | |||
231 | DBG(("sna_render_finish_solid(force=%d, domain=%d, busy=%d, dirty=%d)\n", |
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232 | force, cache->cache_bo->domain, cache->cache_bo->rq != NULL, cache->dirty)); |
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233 | |||
234 | if (!force && cache->cache_bo->domain != DOMAIN_GPU) |
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235 | return; |
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236 | |||
237 | if (cache->dirty) |
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238 | sna_render_flush_solid(sna); |
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239 | |||
240 | for (i = 0; i < cache->size; i++) { |
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241 | if (cache->bo[i] == NULL) |
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242 | continue; |
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243 | |||
244 | kgem_bo_destroy(&sna->kgem, cache->bo[i]); |
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245 | cache->bo[i] = NULL; |
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246 | } |
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247 | kgem_bo_destroy(&sna->kgem, cache->cache_bo); |
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248 | |||
249 | DBG(("sna_render_finish_solid reset\n")); |
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250 | |||
251 | cache->cache_bo = kgem_create_linear(&sna->kgem, sizeof(cache->color)); |
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252 | cache->bo[0] = kgem_create_proxy(cache->cache_bo, 0, sizeof(uint32_t)); |
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253 | cache->bo[0]->pitch = 4; |
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254 | if (force) |
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255 | cache->size = 1; |
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256 | } |
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257 | |||
258 | |||
259 | struct kgem_bo * |
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260 | sna_render_get_solid(struct sna *sna, uint32_t color) |
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261 | { |
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262 | struct sna_solid_cache *cache = &sna->render.solid_cache; |
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263 | int i; |
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264 | |||
265 | DBG(("%s: %08x\n", __FUNCTION__, color)); |
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266 | |||
267 | // if ((color & 0xffffff) == 0) /* alpha only */ |
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268 | // return kgem_bo_reference(sna->render.alpha_cache.bo[color>>24]); |
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269 | |||
270 | if (color == 0xffffffff) { |
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271 | DBG(("%s(white)\n", __FUNCTION__)); |
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272 | return kgem_bo_reference(cache->bo[0]); |
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273 | } |
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274 | |||
275 | if (cache->color[cache->last] == color) { |
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276 | DBG(("sna_render_get_solid(%d) = %x (last)\n", |
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277 | cache->last, color)); |
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278 | return kgem_bo_reference(cache->bo[cache->last]); |
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279 | } |
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280 | |||
281 | for (i = 1; i < cache->size; i++) { |
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282 | if (cache->color[i] == color) { |
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283 | if (cache->bo[i] == NULL) { |
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284 | DBG(("sna_render_get_solid(%d) = %x (recreate)\n", |
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285 | i, color)); |
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286 | goto create; |
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287 | } else { |
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288 | DBG(("sna_render_get_solid(%d) = %x (old)\n", |
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289 | i, color)); |
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290 | goto done; |
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291 | } |
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292 | } |
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293 | } |
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294 | |||
295 | sna_render_finish_solid(sna, i == ARRAY_SIZE(cache->color)); |
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296 | |||
297 | i = cache->size++; |
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298 | cache->color[i] = color; |
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299 | cache->dirty = 1; |
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300 | DBG(("sna_render_get_solid(%d) = %x (new)\n", i, color)); |
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301 | |||
302 | create: |
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303 | cache->bo[i] = kgem_create_proxy(cache->cache_bo, |
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304 | i*sizeof(uint32_t), sizeof(uint32_t)); |
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305 | cache->bo[i]->pitch = 4; |
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306 | |||
307 | done: |
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308 | cache->last = i; |
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309 | return kgem_bo_reference(cache->bo[i]); |
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310 | } |
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311 | |||
312 | #endif |
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313 | |||
314 | |||
315 | int sna_blit_copy(uint32_t dst_bitmap, int dst_x, int dst_y, |
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316 | int w, int h, uint32_t src_bitmap, int src_x, int src_y) |
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317 | |||
318 | { |
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319 | struct sna_copy_op copy; |
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320 | struct kgem_bo src_bo, dst_bo; |
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321 | |||
322 | memset(&src_bo, 0, sizeof(src_bo)); |
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323 | memset(&dst_bo, 0, sizeof(dst_bo)); |
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324 | |||
325 | // src_bo.gaddr = src_bitmap->gaddr; |
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326 | // src_bo.pitch = src_bitmap->pitch; |
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327 | // src_bo.tiling = 0; |
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328 | |||
329 | // dst_bo.gaddr = dst_bitmap->gaddr; |
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330 | // dst_bo.pitch = dst_bitmap->pitch; |
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331 | // dst_bo.tiling = 0; |
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332 | |||
333 | memset(©, 0, sizeof(copy)); |
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334 | |||
335 | sna_device->render.copy(sna_device, GXcopy, NULL, &src_bo, NULL, &dst_bo, ©); |
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336 | copy.blt(sna_device, ©, src_x, src_y, w, h, dst_x, dst_y); |
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337 | copy.done(sna_device, ©); |
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338 | |||
339 | |||
340 | |||
341 | // _kgem_submit(&sna_device->kgem, &execbuffer); |
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342 | |||
343 | }; |
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344 | |||
345 | |||
346 | /* |
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347 | |||
348 | int sna_blit_tex(bitmap_t *dst_bitmap, int dst_x, int dst_y, |
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349 | int w, int h, bitmap_t *src_bitmap, int src_x, int src_y, |
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350 | bitmap_t *mask_bitmap) |
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351 | |||
352 | { |
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353 | struct sna_composite_op cop; |
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354 | batchbuffer_t execbuffer; |
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355 | BoxRec box; |
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356 | |||
357 | struct kgem_bo src_bo, mask_bo, dst_bo; |
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358 | |||
359 | memset(&cop, 0, sizeof(cop)); |
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360 | memset(&execbuffer, 0, sizeof(execbuffer)); |
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361 | memset(&src_bo, 0, sizeof(src_bo)); |
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362 | memset(&dst_bo, 0, sizeof(dst_bo)); |
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363 | memset(&mask_bo, 0, sizeof(mask_bo)); |
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364 | |||
365 | src_bo.gaddr = src_bitmap->gaddr; |
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366 | src_bo.pitch = src_bitmap->pitch; |
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367 | src_bo.tiling = 0; |
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368 | |||
369 | dst_bo.gaddr = dst_bitmap->gaddr; |
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370 | dst_bo.pitch = dst_bitmap->pitch; |
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371 | dst_bo.tiling = 0; |
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372 | |||
373 | mask_bo.gaddr = mask_bitmap->gaddr; |
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374 | mask_bo.pitch = mask_bitmap->pitch; |
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375 | mask_bo.tiling = 0; |
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376 | |||
377 | box.x1 = dst_x; |
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378 | box.y1 = dst_y; |
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379 | box.x2 = dst_x+w; |
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380 | box.y2 = dst_y+h; |
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381 | |||
382 | sna_device->render.composite(sna_device, 0, |
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383 | src_bitmap, &src_bo, |
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384 | mask_bitmap, &mask_bo, |
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385 | dst_bitmap, &dst_bo, |
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386 | src_x, src_y, |
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387 | src_x, src_y, |
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388 | dst_x, dst_y, |
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389 | w, h, &cop); |
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390 | |||
391 | cop.box(sna_device, &cop, &box); |
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392 | cop.done(sna_device, &cop); |
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393 | |||
394 | INIT_LIST_HEAD(&execbuffer.objects); |
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395 | list_add_tail(&src_bitmap->obj->exec_list, &execbuffer.objects); |
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396 | list_add_tail(&mask_bitmap->obj->exec_list, &execbuffer.objects); |
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397 | |||
398 | _kgem_submit(&sna_device->kgem, &execbuffer); |
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399 | |||
400 | }; |
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401 | |||
402 | */ |
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403 | |||
404 | static const struct intel_device_info intel_generic_info = { |
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405 | .gen = -1, |
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406 | }; |
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407 | |||
408 | static const struct intel_device_info intel_i915_info = { |
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409 | .gen = 030, |
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410 | }; |
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411 | static const struct intel_device_info intel_i945_info = { |
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412 | .gen = 031, |
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413 | }; |
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414 | |||
415 | static const struct intel_device_info intel_g33_info = { |
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416 | .gen = 033, |
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417 | }; |
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418 | |||
419 | static const struct intel_device_info intel_i965_info = { |
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420 | .gen = 040, |
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421 | }; |
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422 | |||
423 | static const struct intel_device_info intel_g4x_info = { |
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424 | .gen = 045, |
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425 | }; |
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426 | |||
427 | static const struct intel_device_info intel_ironlake_info = { |
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428 | .gen = 050, |
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429 | }; |
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430 | |||
431 | static const struct intel_device_info intel_sandybridge_info = { |
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432 | .gen = 060, |
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433 | }; |
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434 | |||
435 | static const struct intel_device_info intel_ivybridge_info = { |
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436 | .gen = 070, |
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437 | }; |
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438 | |||
439 | static const struct intel_device_info intel_valleyview_info = { |
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440 | .gen = 071, |
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441 | }; |
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442 | |||
443 | static const struct intel_device_info intel_haswell_info = { |
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444 | .gen = 075, |
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445 | }; |
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446 | |||
447 | #define INTEL_DEVICE_MATCH(d,i) \ |
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448 | { 0x8086, (d), PCI_MATCH_ANY, PCI_MATCH_ANY, 0x3 << 16, 0xff << 16, (intptr_t)(i) } |
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449 | |||
450 | |||
451 | static const struct pci_id_match intel_device_match[] = { |
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452 | |||
453 | |||
454 | INTEL_DEVICE_MATCH (PCI_CHIP_I915_G, &intel_i915_info ), |
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455 | INTEL_DEVICE_MATCH (PCI_CHIP_E7221_G, &intel_i915_info ), |
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456 | INTEL_DEVICE_MATCH (PCI_CHIP_I915_GM, &intel_i915_info ), |
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457 | INTEL_DEVICE_MATCH (PCI_CHIP_I945_G, &intel_i945_info ), |
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458 | INTEL_DEVICE_MATCH (PCI_CHIP_I945_GM, &intel_i945_info ), |
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459 | INTEL_DEVICE_MATCH (PCI_CHIP_I945_GME, &intel_i945_info ), |
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460 | |||
461 | INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_M, &intel_g33_info ), |
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462 | INTEL_DEVICE_MATCH (PCI_CHIP_PINEVIEW_G, &intel_g33_info ), |
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463 | INTEL_DEVICE_MATCH (PCI_CHIP_G33_G, &intel_g33_info ), |
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464 | INTEL_DEVICE_MATCH (PCI_CHIP_Q33_G, &intel_g33_info ), |
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465 | /* Another marketing win: Q35 is another g33 device not a gen4 part |
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466 | * like its G35 brethren. |
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467 | */ |
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468 | INTEL_DEVICE_MATCH (PCI_CHIP_Q35_G, &intel_g33_info ), |
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469 | |||
470 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_G, &intel_i965_info ), |
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471 | INTEL_DEVICE_MATCH (PCI_CHIP_G35_G, &intel_i965_info ), |
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472 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_Q, &intel_i965_info ), |
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473 | INTEL_DEVICE_MATCH (PCI_CHIP_I946_GZ, &intel_i965_info ), |
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474 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_GM, &intel_i965_info ), |
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475 | INTEL_DEVICE_MATCH (PCI_CHIP_I965_GME, &intel_i965_info ), |
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476 | |||
477 | INTEL_DEVICE_MATCH (PCI_CHIP_GM45_GM, &intel_g4x_info ), |
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478 | INTEL_DEVICE_MATCH (PCI_CHIP_G45_E_G, &intel_g4x_info ), |
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479 | INTEL_DEVICE_MATCH (PCI_CHIP_G45_G, &intel_g4x_info ), |
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480 | INTEL_DEVICE_MATCH (PCI_CHIP_Q45_G, &intel_g4x_info ), |
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481 | INTEL_DEVICE_MATCH (PCI_CHIP_G41_G, &intel_g4x_info ), |
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482 | INTEL_DEVICE_MATCH (PCI_CHIP_B43_G, &intel_g4x_info ), |
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483 | INTEL_DEVICE_MATCH (PCI_CHIP_B43_G1, &intel_g4x_info ), |
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484 | |||
485 | INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_D_G, &intel_ironlake_info ), |
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486 | INTEL_DEVICE_MATCH (PCI_CHIP_IRONLAKE_M_G, &intel_ironlake_info ), |
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487 | |||
488 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT1, &intel_sandybridge_info ), |
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489 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2, &intel_sandybridge_info ), |
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490 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_GT2_PLUS, &intel_sandybridge_info ), |
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491 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT1, &intel_sandybridge_info ), |
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492 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2, &intel_sandybridge_info ), |
||
493 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS, &intel_sandybridge_info ), |
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494 | INTEL_DEVICE_MATCH (PCI_CHIP_SANDYBRIDGE_S_GT, &intel_sandybridge_info ), |
||
495 | |||
496 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT1, &intel_ivybridge_info ), |
||
497 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_M_GT2, &intel_ivybridge_info ), |
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498 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT1, &intel_ivybridge_info ), |
||
499 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_D_GT2, &intel_ivybridge_info ), |
||
500 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT1, &intel_ivybridge_info ), |
||
501 | INTEL_DEVICE_MATCH (PCI_CHIP_IVYBRIDGE_S_GT2, &intel_ivybridge_info ), |
||
502 | |||
503 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT1, &intel_haswell_info ), |
||
504 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2, &intel_haswell_info ), |
||
505 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_D_GT2_PLUS, &intel_haswell_info ), |
||
506 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT1, &intel_haswell_info ), |
||
507 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2, &intel_haswell_info ), |
||
508 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_M_GT2_PLUS, &intel_haswell_info ), |
||
509 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT1, &intel_haswell_info ), |
||
510 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2, &intel_haswell_info ), |
||
511 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_S_GT2_PLUS, &intel_haswell_info ), |
||
512 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT1, &intel_haswell_info ), |
||
513 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2, &intel_haswell_info ), |
||
514 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_D_GT2_PLUS, &intel_haswell_info ), |
||
515 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT1, &intel_haswell_info ), |
||
516 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2, &intel_haswell_info ), |
||
517 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_M_GT2_PLUS, &intel_haswell_info ), |
||
518 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT1, &intel_haswell_info ), |
||
519 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2, &intel_haswell_info ), |
||
520 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_SDV_S_GT2_PLUS, &intel_haswell_info ), |
||
521 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT1, &intel_haswell_info ), |
||
522 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2, &intel_haswell_info ), |
||
523 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_D_GT2_PLUS, &intel_haswell_info ), |
||
524 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT1, &intel_haswell_info ), |
||
525 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2, &intel_haswell_info ), |
||
526 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_M_GT2_PLUS, &intel_haswell_info ), |
||
527 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT1, &intel_haswell_info ), |
||
528 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2, &intel_haswell_info ), |
||
529 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_ULT_S_GT2_PLUS, &intel_haswell_info ), |
||
530 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT1, &intel_haswell_info ), |
||
531 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2, &intel_haswell_info ), |
||
532 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_D_GT2_PLUS, &intel_haswell_info ), |
||
533 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT1, &intel_haswell_info ), |
||
534 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2, &intel_haswell_info ), |
||
535 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_M_GT2_PLUS, &intel_haswell_info ), |
||
536 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT1, &intel_haswell_info ), |
||
537 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2, &intel_haswell_info ), |
||
538 | INTEL_DEVICE_MATCH (PCI_CHIP_HASWELL_CRW_S_GT2_PLUS, &intel_haswell_info ), |
||
539 | |||
540 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_PO, &intel_valleyview_info ), |
||
541 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_1, &intel_valleyview_info ), |
||
542 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_2, &intel_valleyview_info ), |
||
543 | INTEL_DEVICE_MATCH (PCI_CHIP_VALLEYVIEW_3, &intel_valleyview_info ), |
||
544 | |||
545 | INTEL_DEVICE_MATCH (PCI_MATCH_ANY, &intel_generic_info ), |
||
546 | |||
547 | { 0, 0, 0 }, |
||
548 | }; |
||
549 | |||
550 | const struct pci_id_match *PciDevMatch(uint16_t dev,const struct pci_id_match *list) |
||
551 | { |
||
552 | while(list->device_id) |
||
553 | { |
||
554 | if(dev==list->device_id) |
||
555 | return list; |
||
556 | list++; |
||
557 | } |
||
558 | return NULL; |
||
559 | } |
||
560 | |||
561 | const struct intel_device_info * |
||
562 | intel_detect_chipset(struct pci_device *pci) |
||
563 | { |
||
564 | const struct pci_id_match *ent = NULL; |
||
565 | const char *name = NULL; |
||
566 | int i; |
||
567 | |||
568 | ent = PciDevMatch(pci->device_id, intel_device_match); |
||
569 | |||
570 | if(ent != NULL) |
||
571 | return (const struct intel_device_info*)ent->match_data; |
||
572 | else |
||
573 | return &intel_generic_info; |
||
574 | |||
575 | #if 0 |
||
576 | for (i = 0; intel_chipsets[i].name != NULL; i++) { |
||
577 | if (DEVICE_ID(pci) == intel_chipsets[i].token) { |
||
578 | name = intel_chipsets[i].name; |
||
579 | break; |
||
580 | } |
||
581 | } |
||
582 | if (name == NULL) { |
||
583 | xf86DrvMsg(scrn->scrnIndex, X_WARNING, "unknown chipset\n"); |
||
584 | name = "unknown"; |
||
585 | } else { |
||
586 | xf86DrvMsg(scrn->scrnIndex, from, |
||
587 | "Integrated Graphics Chipset: Intel(R) %s\n", |
||
588 | name); |
||
589 | } |
||
590 | |||
591 | scrn->chipset = name; |
||
592 | #endif |
||
593 | |||
594 | }><>><>>> |
||
595 |