Rev 1029 | Details | Compare with Previous | Last modification | View Log | RSS feed
| Rev | Author | Line No. | Line |
|---|---|---|---|
| 1029 | serge | 1 | |
| 2 | |||
| 3 | rhdPtr->MMIOMapSize = 1 << rhdPtr->memsize[RHD_MMIO_BAR]; |
||
| 4 | rhdPtr->MMIOBase = MapIoMem(rhdPtr->memBase[RHD_MMIO_BAR], |
||
| 5 | rhdPtr->MMIOMapSize,PG_SW+PG_NOCACHE); |
||
| 6 | if( rhdPtr->MMIOBase==0) |
||
| 7 | return 0; |
||
| 8 | |||
| 9 | DBG(dbgprintf("Mapped IO at %x (size %x)\n", rhdPtr->MMIOBase, rhdPtr->MMIOMapSize)); |
||
| 10 | |||
| 11 | } |
||
| 12 | |||
| 13 | /* Read MC register */ |
||
| 14 | |||
| 15 | { |
||
| 16 | u32_t data; |
||
| 17 | |||
| 18 | if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
||
| 19 | |||
| 20 | OUTREG(RS690_MC_INDEX, (addr & RS690_MC_INDEX_MASK)); |
||
| 21 | data = INREG(RS690_MC_DATA); |
||
| 22 | } else if (info->ChipFamily == CHIP_FAMILY_RS600) { |
||
| 23 | OUTREG(RS600_MC_INDEX, (addr & RS600_MC_INDEX_MASK)); |
||
| 24 | data = INREG(RS600_MC_DATA); |
||
| 25 | } else if (IS_AVIVO_VARIANT) { |
||
| 26 | OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0x7f0000); |
||
| 27 | (void)INREG(AVIVO_MC_INDEX); |
||
| 28 | data = INREG(AVIVO_MC_DATA); |
||
| 29 | |||
| 30 | OUTREG(AVIVO_MC_INDEX, 0); |
||
| 31 | |||
| 32 | } else { |
||
| 33 | OUTREG(R300_MC_IND_INDEX, addr & 0x3f); |
||
| 34 | (void)INREG(R300_MC_IND_INDEX); |
||
| 35 | data = INREG(R300_MC_IND_DATA); |
||
| 36 | |||
| 37 | OUTREG(R300_MC_IND_INDEX, 0); |
||
| 38 | |||
| 39 | } |
||
| 40 | |||
| 41 | return data; |
||
| 42 | |||
| 43 | |||
| 44 | /* Write MC information */ |
||
| 45 | |||
| 46 | { |
||
| 47 | if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
||
| 48 | (info->ChipFamily == CHIP_FAMILY_RS740)) { |
||
| 49 | OUTREG(RS690_MC_INDEX, ((addr & RS690_MC_INDEX_MASK) | RS690_MC_INDEX_WR_EN)); |
||
| 50 | OUTREG(RS690_MC_DATA, data); |
||
| 51 | OUTREG(RS690_MC_INDEX, RS690_MC_INDEX_WR_ACK); |
||
| 52 | } |
||
| 53 | else if (info->ChipFamily == CHIP_FAMILY_RS600) { |
||
| 54 | OUTREG(RS600_MC_INDEX, ((addr & RS600_MC_INDEX_MASK) | RS600_MC_INDEX_WR_EN)); |
||
| 55 | OUTREG(RS600_MC_DATA, data); |
||
| 56 | OUTREG(RS600_MC_INDEX, RS600_MC_INDEX_WR_ACK); |
||
| 57 | } |
||
| 58 | else if (IS_AVIVO_VARIANT) { |
||
| 59 | OUTREG(AVIVO_MC_INDEX, (addr & 0xff) | 0xff0000); |
||
| 60 | (void)INREG(AVIVO_MC_INDEX); |
||
| 61 | OUTREG(AVIVO_MC_DATA, data); |
||
| 62 | OUTREG(AVIVO_MC_INDEX, 0); |
||
| 63 | (void)INREG(AVIVO_MC_INDEX); |
||
| 64 | } |
||
| 65 | else { |
||
| 66 | OUTREG(R300_MC_IND_INDEX, (((addr) & 0x3f) | R300_MC_IND_WR_EN)); |
||
| 67 | (void)INREG(R300_MC_IND_INDEX); |
||
| 68 | OUTREG(R300_MC_IND_DATA, data); |
||
| 69 | OUTREG(R300_MC_IND_INDEX, 0); |
||
| 70 | (void)INREG(R300_MC_IND_INDEX); |
||
| 71 | } |
||
| 72 | } |
||
| 73 | |||
| 74 | static Bool avivo_get_mc_idle(RHDPtr info) |
||
| 75 | |||
| 76 | |||
| 77 | if (info->ChipFamily >= CHIP_FAMILY_R600) { |
||
| 78 | |||
| 79 | return TRUE; |
||
| 80 | } |
||
| 81 | else if (info->ChipFamily == CHIP_FAMILY_RV515) { |
||
| 82 | if (INMC(info, RV515_MC_STATUS) & RV515_MC_STATUS_IDLE) |
||
| 83 | return TRUE; |
||
| 84 | else |
||
| 85 | return FALSE; |
||
| 86 | } |
||
| 87 | else if (info->ChipFamily == CHIP_FAMILY_RS600) |
||
| 88 | { |
||
| 89 | if (INMC(info, RS600_MC_STATUS) & RS600_MC_STATUS_IDLE) |
||
| 90 | return TRUE; |
||
| 91 | else |
||
| 92 | return FALSE; |
||
| 93 | } |
||
| 94 | else if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
||
| 95 | (info->ChipFamily == CHIP_FAMILY_RS740)) { |
||
| 96 | if (INMC(info, RS690_MC_STATUS) & RS690_MC_STATUS_IDLE) |
||
| 97 | return TRUE; |
||
| 98 | else |
||
| 99 | return FALSE; |
||
| 100 | } |
||
| 101 | else { |
||
| 102 | if (INMC(info, R520_MC_STATUS) & R520_MC_STATUS_IDLE) |
||
| 103 | return TRUE; |
||
| 104 | else |
||
| 105 | return FALSE; |
||
| 106 | } |
||
| 107 | } |
||
| 108 | |||
| 109 | #define LOC_FB 0x1 |
||
| 110 | |||
| 111 | |||
| 112 | static void radeon_read_mc_fb_agp_location(RHDPtr info, int mask, |
||
| 113 | |||
| 114 | { |
||
| 115 | |||
| 116 | if (info->ChipFamily >= CHIP_FAMILY_RV770) |
||
| 117 | |||
| 118 | if (mask & LOC_FB) |
||
| 119 | *fb_loc = INREG(R700_MC_VM_FB_LOCATION); |
||
| 120 | if (mask & LOC_AGP) { |
||
| 121 | *agp_loc = INREG(R600_MC_VM_AGP_BOT); |
||
| 122 | *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP); |
||
| 123 | } |
||
| 124 | } |
||
| 125 | else if (info->ChipFamily >= CHIP_FAMILY_R600) |
||
| 126 | { |
||
| 127 | if (mask & LOC_FB) |
||
| 128 | *fb_loc = INREG(R600_MC_VM_FB_LOCATION); |
||
| 129 | if (mask & LOC_AGP) { |
||
| 130 | *agp_loc = INREG(R600_MC_VM_AGP_BOT); |
||
| 131 | *agp_loc_hi = INREG(R600_MC_VM_AGP_TOP); |
||
| 132 | } |
||
| 133 | } |
||
| 134 | else if (info->ChipFamily == CHIP_FAMILY_RV515) |
||
| 135 | { |
||
| 136 | if (mask & LOC_FB) |
||
| 137 | *fb_loc = INMC(info, RV515_MC_FB_LOCATION); |
||
| 138 | if (mask & LOC_AGP) { |
||
| 139 | *agp_loc = INMC(info, RV515_MC_AGP_LOCATION); |
||
| 140 | *agp_loc_hi = 0; |
||
| 141 | } |
||
| 142 | } |
||
| 143 | else if (info->ChipFamily == CHIP_FAMILY_RS600) |
||
| 144 | { |
||
| 145 | if (mask & LOC_FB) |
||
| 146 | *fb_loc = INMC(info, RS600_MC_FB_LOCATION); |
||
| 147 | if (mask & LOC_AGP) { |
||
| 148 | *agp_loc = 0;//INMC(pScrn, RS600_MC_AGP_LOCATION); |
||
| 149 | *agp_loc_hi = 0; |
||
| 150 | } |
||
| 151 | } |
||
| 152 | else if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
||
| 153 | (info->ChipFamily == CHIP_FAMILY_RS740)) |
||
| 154 | { |
||
| 155 | if (mask & LOC_FB) |
||
| 156 | *fb_loc = INMC(info, RS690_MC_FB_LOCATION); |
||
| 157 | if (mask & LOC_AGP) { |
||
| 158 | *agp_loc = INMC(info, RS690_MC_AGP_LOCATION); |
||
| 159 | *agp_loc_hi = 0; |
||
| 160 | } |
||
| 161 | } |
||
| 162 | else if (info->ChipFamily >= CHIP_FAMILY_R520) |
||
| 163 | { |
||
| 164 | if (mask & LOC_FB) |
||
| 165 | *fb_loc = INMC(info, R520_MC_FB_LOCATION); |
||
| 166 | if (mask & LOC_AGP) { |
||
| 167 | *agp_loc = INMC(info, R520_MC_AGP_LOCATION); |
||
| 168 | *agp_loc_hi = 0; |
||
| 169 | } |
||
| 170 | } |
||
| 171 | else |
||
| 172 | { |
||
| 173 | if (mask & LOC_FB) |
||
| 174 | *fb_loc = INREG(RADEON_MC_FB_LOCATION); |
||
| 175 | if (mask & LOC_AGP) |
||
| 176 | *agp_loc = INREG(RADEON_MC_AGP_LOCATION); |
||
| 177 | } |
||
| 178 | } |
||
| 179 | |||
| 180 | static void radeon_write_mc_fb_agp_location(RHDPtr info, int mask, u32_t fb_loc, |
||
| 181 | |||
| 182 | { |
||
| 183 | |||
| 184 | if (info->ChipFamily >= CHIP_FAMILY_RV770) { |
||
| 185 | |||
| 186 | OUTREG(R700_MC_VM_FB_LOCATION, fb_loc); |
||
| 187 | if (mask & LOC_AGP) { |
||
| 188 | OUTREG(R600_MC_VM_AGP_BOT, agp_loc); |
||
| 189 | OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi); |
||
| 190 | } |
||
| 191 | } |
||
| 192 | else if (info->ChipFamily >= CHIP_FAMILY_R600) |
||
| 193 | { |
||
| 194 | if (mask & LOC_FB) |
||
| 195 | OUTREG(R600_MC_VM_FB_LOCATION, fb_loc); |
||
| 196 | if (mask & LOC_AGP) { |
||
| 197 | OUTREG(R600_MC_VM_AGP_BOT, agp_loc); |
||
| 198 | OUTREG(R600_MC_VM_AGP_TOP, agp_loc_hi); |
||
| 199 | } |
||
| 200 | } |
||
| 201 | else if (info->ChipFamily == CHIP_FAMILY_RV515) |
||
| 202 | { |
||
| 203 | if (mask & LOC_FB) |
||
| 204 | OUTMC(info, RV515_MC_FB_LOCATION, fb_loc); |
||
| 205 | if (mask & LOC_AGP) |
||
| 206 | OUTMC(info, RV515_MC_AGP_LOCATION, agp_loc); |
||
| 207 | (void)INMC(info, RV515_MC_AGP_LOCATION); |
||
| 208 | } |
||
| 209 | else if (info->ChipFamily == CHIP_FAMILY_RS600) |
||
| 210 | { |
||
| 211 | if (mask & LOC_FB) |
||
| 212 | OUTMC(info, RS600_MC_FB_LOCATION, fb_loc); |
||
| 213 | /* if (mask & LOC_AGP) |
||
| 214 | OUTMC(pScrn, RS600_MC_AGP_LOCATION, agp_loc);*/ |
||
| 215 | } |
||
| 216 | else if ((info->ChipFamily == CHIP_FAMILY_RS690) || |
||
| 217 | (info->ChipFamily == CHIP_FAMILY_RS740)) |
||
| 218 | { |
||
| 219 | if (mask & LOC_FB) |
||
| 220 | OUTMC(info, RS690_MC_FB_LOCATION, fb_loc); |
||
| 221 | if (mask & LOC_AGP) |
||
| 222 | OUTMC(info, RS690_MC_AGP_LOCATION, agp_loc); |
||
| 223 | } |
||
| 224 | else if (info->ChipFamily >= CHIP_FAMILY_R520) |
||
| 225 | { |
||
| 226 | if (mask & LOC_FB) |
||
| 227 | OUTMC(info, R520_MC_FB_LOCATION, fb_loc); |
||
| 228 | if (mask & LOC_AGP) |
||
| 229 | OUTMC(info, R520_MC_AGP_LOCATION, agp_loc); |
||
| 230 | (void)INMC(info, R520_MC_FB_LOCATION); |
||
| 231 | } |
||
| 232 | else { |
||
| 233 | if (mask & LOC_FB) |
||
| 234 | OUTREG(RADEON_MC_FB_LOCATION, fb_loc); |
||
| 235 | if (mask & LOC_AGP) |
||
| 236 | OUTREG(RADEON_MC_AGP_LOCATION, agp_loc); |
||
| 237 | } |
||
| 238 | } |
||
| 239 | |||
| 240 | |||
| 241 | |||
| 242 | |||
| 243 | u32_t timeout; |
||
| 244 | |||
| 245 | u32_t mc_fb_loc, mc_agp_loc, mc_agp_loc_hi; |
||
| 246 | |||
| 247 | radeon_read_mc_fb_agp_location(info, LOC_FB | LOC_AGP, &mc_fb_loc, |
||
| 248 | |||
| 249 | |||
| 250 | if (IS_AVIVO_VARIANT) |
||
| 251 | |||
| 252 | |||
| 253 | if (mc_fb_loc != info->mc_fb_location || |
||
| 254 | |||
| 255 | { |
||
| 256 | u32_t d1crtc, d2crtc; |
||
| 257 | u32_t tmp; |
||
| 258 | // RADEONWaitForIdleMMIO(pScrn); |
||
| 259 | |||
| 260 | OUTREG(AVIVO_D1VGA_CONTROL, INREG(AVIVO_D1VGA_CONTROL) & ~AVIVO_DVGA_CONTROL_MODE_ENABLE); |
||
| 261 | |||
| 262 | |||
| 263 | /* Stop display & memory access */ |
||
| 264 | |||
| 265 | OUTREG(AVIVO_D1CRTC_CONTROL, d1crtc & ~AVIVO_CRTC_EN); |
||
| 266 | |||
| 267 | d2crtc = INREG(AVIVO_D2CRTC_CONTROL); |
||
| 268 | |||
| 269 | |||
| 270 | tmp = INREG(AVIVO_D2CRTC_CONTROL); |
||
| 271 | |||
| 272 | usleep(1000); |
||
| 273 | |||
| 274 | while (!(avivo_get_mc_idle(info))) |
||
| 275 | { |
||
| 276 | if (++timeout > 1000000) |
||
| 277 | { |
||
| 278 | dbgprintf("Timeout trying to update memory controller settings !\n"); |
||
| 279 | dbgprintf("You will probably crash now ... \n"); |
||
| 280 | /* Nothing we can do except maybe try to kill the server, |
||
| 281 | * let's wait 2 seconds to leave the above message a chance |
||
| 282 | * to maybe hit the disk and continue trying to setup despite |
||
| 283 | * the MC being non-idle |
||
| 284 | */ |
||
| 285 | usleep(20000); |
||
| 286 | } |
||
| 287 | usleep(10); |
||
| 288 | } |
||
| 289 | |||
| 290 | radeon_write_mc_fb_agp_location(info, LOC_FB | LOC_AGP, |
||
| 291 | |||
| 292 | info->mc_agp_location, |
||
| 293 | info->mc_agp_location_hi); |
||
| 294 | |||
| 295 | if (info->ChipFamily < CHIP_FAMILY_R600) { |
||
| 296 | |||
| 297 | } |
||
| 298 | else { |
||
| 299 | OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000); |
||
| 300 | } |
||
| 301 | |||
| 302 | OUTREG(AVIVO_D1CRTC_CONTROL, d1crtc ); |
||
| 303 | |||
| 304 | OUTREG(AVIVO_D2CRTC_CONTROL, d2crtc ); |
||
| 305 | |||
| 306 | tmp = INREG(AVIVO_D2CRTC_CONTROL); |
||
| 307 | |||
| 308 | /* Reset the engine and HDP */ |
||
| 309 | |||
| 310 | } |
||
| 311 | } |
||
| 312 | else |
||
| 313 | { |
||
| 314 | |||
| 315 | /* Write memory mapping registers only if their value change |
||
| 316 | |||
| 317 | * reprogrammed |
||
| 318 | */ |
||
| 319 | if ( mc_fb_loc != info->mc_fb_location || |
||
| 320 | mc_agp_loc != info->mc_agp_location) |
||
| 321 | { |
||
| 322 | u32_t crtc_ext_cntl, crtc_gen_cntl, crtc2_gen_cntl=0, ov0_scale_cntl; |
||
| 323 | u32_t old_mc_status, status_idle; |
||
| 324 | |||
| 325 | dbgprintf(" Map Changed ! Applying ...\n"); |
||
| 326 | |||
| 327 | /* Make sure engine is idle. We assume the CCE is stopped |
||
| 328 | |||
| 329 | */ |
||
| 330 | // RADEONWaitForIdleMMIO(info); |
||
| 331 | |||
| 332 | if (info->IsIGP) |
||
| 333 | |||
| 334 | |||
| 335 | /* Capture MC_STATUS in case things go wrong ... */ |
||
| 336 | |||
| 337 | |||
| 338 | /* Stop display & memory access */ |
||
| 339 | |||
| 340 | OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl & ~RADEON_SCALER_ENABLE); |
||
| 341 | crtc_ext_cntl = INREG(RADEON_CRTC_EXT_CNTL); |
||
| 342 | OUTREG(RADEON_CRTC_EXT_CNTL, crtc_ext_cntl | RADEON_CRTC_DISPLAY_DIS); |
||
| 343 | crtc_gen_cntl = INREG(RADEON_CRTC_GEN_CNTL); |
||
| 344 | // RADEONWaitForVerticalSync(pScrn); |
||
| 345 | OUTREG(RADEON_CRTC_GEN_CNTL, |
||
| 346 | (crtc_gen_cntl & ~(RADEON_CRTC_CUR_EN | RADEON_CRTC_ICON_EN)) |
||
| 347 | | RADEON_CRTC_DISP_REQ_EN_B | RADEON_CRTC_EXT_DISP_EN); |
||
| 348 | |||
| 349 | if (info->HasCRTC2) |
||
| 350 | |||
| 351 | crtc2_gen_cntl = INREG(RADEON_CRTC2_GEN_CNTL); |
||
| 352 | // RADEONWaitForVerticalSync2(pScrn); |
||
| 353 | OUTREG(RADEON_CRTC2_GEN_CNTL, (crtc2_gen_cntl |
||
| 354 | & ~(RADEON_CRTC2_CUR_EN | RADEON_CRTC2_ICON_EN)) |
||
| 355 | | RADEON_CRTC2_DISP_REQ_EN_B); |
||
| 356 | } |
||
| 357 | |||
| 358 | /* Make sure the chip settles down (paranoid !) */ |
||
| 359 | |||
| 360 | |||
| 361 | /* Wait for MC idle */ |
||
| 362 | |||
| 363 | status_idle = R300_MC_IDLE; |
||
| 364 | else |
||
| 365 | status_idle = RADEON_MC_IDLE; |
||
| 366 | |||
| 367 | timeout = 0; |
||
| 368 | |||
| 369 | { |
||
| 370 | if (++timeout > 1000000) |
||
| 371 | { |
||
| 372 | dbgprintf("Timeout trying to update memory controller settings !\n"); |
||
| 373 | dbgprintf("MC_STATUS = 0x%08x (on entry = 0x%08x)\n", |
||
| 374 | INREG(RADEON_MC_STATUS), old_mc_status); |
||
| 375 | dbgprintf("You will probably crash now ... \n"); |
||
| 376 | /* Nothing we can do except maybe try to kill the server, |
||
| 377 | * let's wait 2 seconds to leave the above message a chance |
||
| 378 | * to maybe hit the disk and continue trying to setup despite |
||
| 379 | * the MC being non-idle |
||
| 380 | */ |
||
| 381 | usleep(20000); |
||
| 382 | } |
||
| 383 | usleep(10); |
||
| 384 | } |
||
| 385 | |||
| 386 | /* Update maps, first clearing out AGP to make sure we don't get |
||
| 387 | |||
| 388 | */ |
||
| 389 | OUTREG(RADEON_MC_AGP_LOCATION, 0xfffffffc); |
||
| 390 | OUTREG(RADEON_MC_FB_LOCATION, info->mc_fb_location); |
||
| 391 | radeon_write_mc_fb_agp_location(info, LOC_FB | LOC_AGP, info->mc_fb_location, |
||
| 392 | 0xfffffffc, 0); |
||
| 393 | |||
| 394 | OUTREG(RADEON_CRTC_GEN_CNTL,crtc_gen_cntl ); |
||
| 395 | |||
| 396 | OUTREG(RADEON_OV0_SCALE_CNTL, ov0_scale_cntl ); |
||
| 397 | |||
| 398 | |||
| 399 | |||
| 400 | |||
| 401 | info->mc_agp_location, 0); |
||
| 402 | /* Make sure map fully reached the chip */ |
||
| 403 | (void)INREG(RADEON_MC_FB_LOCATION); |
||
| 404 | |||
| 405 | dbgprintf(" Map applied, resetting engine ...\n"); |
||
| 406 | |||
| 407 | /* Reset the engine and HDP */ |
||
| 408 | |||
| 409 | |||
| 410 | /* Make sure we have sane offsets before re-enabling the CRTCs, disable |
||
| 411 | |||
| 412 | */ |
||
| 413 | |||
| 414 | OUTREG(RADEON_CRTC_OFFSET_CNTL, RADEON_CRTC_OFFSET_FLIP_CNTL); |
||
| 415 | |||
| 416 | OUTREG(RADEON_CUR_OFFSET, 0); |
||
| 417 | timeout = 0; |
||
| 418 | while(INREG(RADEON_CRTC_OFFSET) & RADEON_CRTC_OFFSET__GUI_TRIG_OFFSET) |
||
| 419 | { |
||
| 420 | if (timeout++ > 1000000) { |
||
| 421 | dbgprintf("Timeout waiting for CRTC offset to update !\n"); |
||
| 422 | break; |
||
| 423 | } |
||
| 424 | usleep(1000); |
||
| 425 | } |
||
| 426 | if (info->HasCRTC2) |
||
| 427 | { |
||
| 428 | OUTREG(RADEON_CRTC2_OFFSET_CNTL, RADEON_CRTC2_OFFSET_FLIP_CNTL); |
||
| 429 | OUTREG(RADEON_CRTC2_OFFSET, 0); |
||
| 430 | OUTREG(RADEON_CUR2_OFFSET, 0); |
||
| 431 | timeout = 0; |
||
| 432 | while(INREG(RADEON_CRTC2_OFFSET) & RADEON_CRTC2_OFFSET__GUI_TRIG_OFFSET) |
||
| 433 | { |
||
| 434 | if (timeout++ > 1000000) { |
||
| 435 | dbgprintf("Timeout waiting for CRTC2 offset to update !\n"); |
||
| 436 | break; |
||
| 437 | } |
||
| 438 | usleep(1000); |
||
| 439 | } |
||
| 440 | } |
||
| 441 | } |
||
| 442 | |||
| 443 | dbgprintf("Updating display base addresses...\n"); |
||
| 444 | |||
| 445 | OUTREG(RADEON_DISPLAY_BASE_ADDR, info->fbLocation); |
||
| 446 | |||
| 447 | OUTREG(RADEON_DISPLAY2_BASE_ADDR, info->fbLocation); |
||
| 448 | OUTREG(RADEON_OV0_BASE_ADDR, info->fbLocation); |
||
| 449 | (void)INREG(RADEON_OV0_BASE_ADDR); |
||
| 450 | |||
| 451 | /* More paranoia delays, wait 100ms */ |
||
| 452 | |||
| 453 | |||
| 454 | dbgprintf("Memory map updated.\n"); |
||
| 455 | |||
| 456 | }; |
||
| 457 | |||
| 458 | |||
| 459 | |||
| 460 | |||
| 461 | u32_t mem_size; |
||
| 462 | u32_t aper_size; |
||
| 463 | |||
| 464 | radeon_read_mc_fb_agp_location(info, LOC_FB | LOC_AGP, &info->mc_fb_location, |
||
| 465 | |||
| 466 | |||
| 467 | dbgprintf(" MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location); |
||
| 468 | |||
| 469 | |||
| 470 | |||
| 471 | |||
| 472 | |||
| 473 | */ |
||
| 474 | if (info->ChipFamily >= CHIP_FAMILY_R600){ |
||
| 475 | mem_size = INREG(R600_CONFIG_MEMSIZE); |
||
| 476 | aper_size = INREG(R600_CONFIG_APER_SIZE); |
||
| 477 | } |
||
| 478 | else { |
||
| 479 | mem_size = INREG(RADEON_CONFIG_MEMSIZE); |
||
| 480 | aper_size = INREG(RADEON_CONFIG_APER_SIZE); |
||
| 481 | } |
||
| 482 | |||
| 483 | if (mem_size == 0) |
||
| 484 | |||
| 485 | |||
| 486 | /* Fix for RN50, M6, M7 with 8/16/32(??) MBs of VRAM - |
||
| 487 | |||
| 488 | if (aper_size > mem_size) |
||
| 489 | mem_size = aper_size; |
||
| 490 | |||
| 491 | |||
| 492 | |||
| 493 | |||
| 494 | (info->ChipFamily != CHIP_FAMILY_RS740)) |
||
| 495 | { |
||
| 496 | if (info->IsIGP) |
||
| 497 | info->mc_fb_location = INREG(RADEON_NB_TOM); |
||
| 498 | else |
||
| 499 | { |
||
| 500 | u32_t aper0_base; |
||
| 501 | |||
| 502 | if (info->ChipFamily >= CHIP_FAMILY_R600) { |
||
| 503 | |||
| 504 | } |
||
| 505 | else { |
||
| 506 | aper0_base = INREG(RADEON_CONFIG_APER_0_BASE); |
||
| 507 | } |
||
| 508 | dbgprintf("aper0 base %x\n", aper0_base ); |
||
| 509 | |||
| 510 | /* Recent chips have an "issue" with the memory controller, the |
||
| 511 | |||
| 512 | * too bad if we walk over the top of system memory, we don't |
||
| 513 | * use DMA without a remapped anyway. |
||
| 514 | * Affected chips are rv280, all r3xx, and all r4xx, but not IGP |
||
| 515 | */ |
||
| 516 | if ( info->ChipFamily == CHIP_FAMILY_RV280 || |
||
| 517 | info->ChipFamily == CHIP_FAMILY_R300 || |
||
| 518 | info->ChipFamily == CHIP_FAMILY_R350 || |
||
| 519 | info->ChipFamily == CHIP_FAMILY_RV350 || |
||
| 520 | info->ChipFamily == CHIP_FAMILY_RV380 || |
||
| 521 | info->ChipFamily == CHIP_FAMILY_R420 || |
||
| 522 | info->ChipFamily == CHIP_FAMILY_RV410) |
||
| 523 | aper0_base &= ~(mem_size - 1); |
||
| 524 | |||
| 525 | if ( info->ChipFamily >= CHIP_FAMILY_R600) { |
||
| 526 | |||
| 527 | (((aper0_base + mem_size - 1) & 0xff000000U) >> 8); |
||
| 528 | dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location); |
||
| 529 | } |
||
| 530 | else { |
||
| 531 | info->mc_fb_location = (aper0_base >> 16) | |
||
| 532 | ((aper0_base + mem_size - 1) & 0xffff0000U); |
||
| 533 | dbgprintf("mc fb loc is %08x\n", (unsigned int)info->mc_fb_location); |
||
| 534 | } |
||
| 535 | } |
||
| 536 | } |
||
| 537 | if (info->ChipFamily >= CHIP_FAMILY_R600) { |
||
| 538 | info->fbLocation = (info->mc_fb_location & 0xffff) << 24; |
||
| 539 | } |
||
| 540 | else { |
||
| 541 | info->fbLocation = (info->mc_fb_location & 0xffff) << 16; |
||
| 542 | } |
||
| 543 | /* Just disable the damn AGP apertures for now, it may be |
||
| 544 | * re-enabled later by the DRM |
||
| 545 | */ |
||
| 546 | |||
| 547 | if (IS_AVIVO_VARIANT) { |
||
| 548 | |||
| 549 | OUTREG(R600_HDP_NONSURFACE_BASE, (info->mc_fb_location << 16) & 0xff0000); |
||
| 550 | } |
||
| 551 | else { |
||
| 552 | OUTREG(AVIVO_HDP_FB_LOCATION, info->mc_fb_location); |
||
| 553 | } |
||
| 554 | info->mc_agp_location = 0x003f0000; |
||
| 555 | } |
||
| 556 | else |
||
| 557 | info->mc_agp_location = 0xffffffc0; |
||
| 558 | |||
| 559 | dbgprintf("RADEONInitMemoryMap() : \n"); |
||
| 560 | |||
| 561 | dbgprintf(" MC_FB_LOCATION : 0x%08x\n", (unsigned)info->mc_fb_location); |
||
| 562 | dbgprintf(" MC_AGP_LOCATION : 0x%08x\n", (unsigned)info->mc_agp_location); |
||
| 563 | dbgprintf(" FB_LOCATION : 0x%08x\n", (unsigned)info->fbLocation); |
||
| 564 | |||
| 565 | |||
| 566 | |||
| 567 | |||
| 568 | |||
| 569 | |||
| 570 | |||
| 571 | static void RADEONGetVRamType(RHDPtr info) |
||
| 572 | |||
| 573 | u32_t tmp; |
||
| 574 | |||
| 575 | if (info->IsIGP || (info->ChipFamily >= CHIP_FAMILY_R300)) |
||
| 576 | |||
| 577 | else if (INREG(RADEON_MEM_SDRAM_MODE_REG) & RADEON_MEM_CFG_TYPE_DDR) |
||
| 578 | info->IsDDR = TRUE; |
||
| 579 | else |
||
| 580 | info->IsDDR = FALSE; |
||
| 581 | |||
| 582 | if ( (info->ChipFamily >= CHIP_FAMILY_R600) && |
||
| 583 | |||
| 584 | { |
||
| 585 | int chansize; |
||
| 586 | /* r6xx */ |
||
| 587 | tmp = INREG(R600_RAMCFG); |
||
| 588 | if (tmp & R600_CHANSIZE_OVERRIDE) |
||
| 589 | chansize = 16; |
||
| 590 | else if (tmp & R600_CHANSIZE) |
||
| 591 | chansize = 64; |
||
| 592 | else |
||
| 593 | chansize = 32; |
||
| 594 | if (info->ChipFamily == CHIP_FAMILY_R600) |
||
| 595 | info->RamWidth = 8 * chansize; |
||
| 596 | else if (info->ChipFamily == CHIP_FAMILY_RV670) |
||
| 597 | info->RamWidth = 4 * chansize; |
||
| 598 | else if ((info->ChipFamily == CHIP_FAMILY_RV610) || |
||
| 599 | (info->ChipFamily == CHIP_FAMILY_RV620)) |
||
| 600 | info->RamWidth = chansize; |
||
| 601 | else if ((info->ChipFamily == CHIP_FAMILY_RV630) || |
||
| 602 | (info->ChipFamily == CHIP_FAMILY_RV635)) |
||
| 603 | info->RamWidth = 2 * chansize; |
||
| 604 | } |
||
| 605 | else if (info->ChipFamily == CHIP_FAMILY_RV515) { |
||
| 606 | /* rv515/rv550 */ |
||
| 607 | tmp = INMC(info, RV515_MC_CNTL); |
||
| 608 | tmp &= RV515_MEM_NUM_CHANNELS_MASK; |
||
| 609 | switch (tmp) { |
||
| 610 | case 0: info->RamWidth = 64; break; |
||
| 611 | case 1: info->RamWidth = 128; break; |
||
| 612 | default: info->RamWidth = 128; break; |
||
| 613 | } |
||
| 614 | } |
||
| 615 | else if ((info->ChipFamily >= CHIP_FAMILY_R520) && |
||
| 616 | (info->ChipFamily <= CHIP_FAMILY_RV570)){ |
||
| 617 | /* r520/rv530/rv560/rv570/r580 */ |
||
| 618 | tmp = INMC(info, R520_MC_CNTL0); |
||
| 619 | switch ((tmp & R520_MEM_NUM_CHANNELS_MASK) >> R520_MEM_NUM_CHANNELS_SHIFT) { |
||
| 620 | case 0: info->RamWidth = 32; break; |
||
| 621 | case 1: info->RamWidth = 64; break; |
||
| 622 | case 2: info->RamWidth = 128; break; |
||
| 623 | case 3: info->RamWidth = 256; break; |
||
| 624 | default: info->RamWidth = 64; break; |
||
| 625 | } |
||
| 626 | if (tmp & R520_MC_CHANNEL_SIZE) { |
||
| 627 | info->RamWidth *= 2; |
||
| 628 | } |
||
| 629 | } |
||
| 630 | else if ((info->ChipFamily >= CHIP_FAMILY_R300) && |
||
| 631 | (info->ChipFamily <= CHIP_FAMILY_RV410)) { |
||
| 632 | /* r3xx, r4xx */ |
||
| 633 | tmp = INREG(RADEON_MEM_CNTL); |
||
| 634 | tmp &= R300_MEM_NUM_CHANNELS_MASK; |
||
| 635 | switch (tmp) { |
||
| 636 | case 0: info->RamWidth = 64; break; |
||
| 637 | case 1: info->RamWidth = 128; break; |
||
| 638 | case 2: info->RamWidth = 256; break; |
||
| 639 | default: info->RamWidth = 128; break; |
||
| 640 | } |
||
| 641 | } |
||
| 642 | else if ((info->ChipFamily == CHIP_FAMILY_RV100) || |
||
| 643 | (info->ChipFamily == CHIP_FAMILY_RS100) || |
||
| 644 | (info->ChipFamily == CHIP_FAMILY_RS200)){ |
||
| 645 | tmp = INREG(RADEON_MEM_CNTL); |
||
| 646 | if (tmp & RV100_HALF_MODE) |
||
| 647 | info->RamWidth = 32; |
||
| 648 | else |
||
| 649 | info->RamWidth = 64; |
||
| 650 | |||
| 651 | if (!info->HasCRTC2) { |
||
| 652 | |||
| 653 | info->IsDDR = TRUE; |
||
| 654 | } |
||
| 655 | } |
||
| 656 | else if (info->ChipFamily <= CHIP_FAMILY_RV280) { |
||
| 657 | tmp = INREG(RADEON_MEM_CNTL); |
||
| 658 | if (tmp & RADEON_MEM_NUM_CHANNELS_MASK) |
||
| 659 | info->RamWidth = 128; |
||
| 660 | else |
||
| 661 | info->RamWidth = 64; |
||
| 662 | } else { |
||
| 663 | /* newer IGPs */ |
||
| 664 | info->RamWidth = 128; |
||
| 665 | } |
||
| 666 | |||
| 667 | /* This may not be correct, as some cards can have half of channel disabled |
||
| 668 | |||
| 669 | */ |
||
| 670 | } |
||
| 671 | |||
| 672 | /* |
||
| 673 | |||
| 674 | * accessible to the CPU can vary. This function is our best shot at figuring |
||
| 675 | * it out. Returns a value in KB. |
||
| 676 | */ |
||
| 677 | static u32_t RADEONGetAccessibleVRAM(RHDPtr info) |
||
| 678 | { |
||
| 679 | u32_t aper_size; |
||
| 680 | unsigned char byte; |
||
| 681 | |||
| 682 | if (info->ChipFamily >= CHIP_FAMILY_R600) |
||
| 683 | |||
| 684 | else |
||
| 685 | aper_size = INREG(RADEON_CONFIG_APER_SIZE) / 1024; |
||
| 686 | |||
| 687 | |||
| 688 | |||
| 689 | |||
| 690 | */ |
||
| 691 | if (info->ChipFamily == CHIP_FAMILY_RV280 || |
||
| 692 | info->ChipFamily == CHIP_FAMILY_RV350 || |
||
| 693 | info->ChipFamily == CHIP_FAMILY_RV380 || |
||
| 694 | info->ChipFamily == CHIP_FAMILY_R420 || |
||
| 695 | info->ChipFamily == CHIP_FAMILY_RV410 || |
||
| 696 | IS_AVIVO_VARIANT) { |
||
| 697 | MASKREG (RADEON_HOST_PATH_CNTL, RADEON_HDP_APER_CNTL, |
||
| 698 | ~RADEON_HDP_APER_CNTL); |
||
| 699 | dbgprintf("Generation 2 PCI interface, using max accessible memory\n"); |
||
| 700 | return aper_size * 2; |
||
| 701 | } |
||
| 702 | |||
| 703 | /* Older cards have all sorts of funny issues to deal with. First |
||
| 704 | |||
| 705 | * header type... Limit those to one aperture size |
||
| 706 | */ |
||
| 707 | byte = pciReadByte(info->PciTag, 0xe); |
||
| 708 | if (byte & 0x80) { |
||
| 709 | dbgprintf("Generation 1 PCI interface in multifunction mode, " |
||
| 710 | "accessible memory limited to one aperture\n"); |
||
| 711 | return aper_size; |
||
| 712 | } |
||
| 713 | |||
| 714 | /* Single function older card. We read HDP_APER_CNTL to see how the BIOS |
||
| 715 | |||
| 716 | * we expect the BIOS to have done the right thing (might be too optimistic...) |
||
| 717 | */ |
||
| 718 | if (INREG(RADEON_HOST_PATH_CNTL) & RADEON_HDP_APER_CNTL) |
||
| 719 | return aper_size * 2; |
||
| 720 | |||
| 721 | return aper_size; |
||
| 722 | |||
| 723 | |||
| 724 | int RADEONDRIGetPciAperTableSize(RHDPtr info) |
||
| 725 | |||
| 726 | int ret_size; |
||
| 727 | int num_pages; |
||
| 728 | |||
| 729 | num_pages = (info->pciAperSize * 1024 * 1024) / 4096; |
||
| 730 | |||
| 731 | ret_size = num_pages * sizeof(unsigned int); |
||
| 732 | |||
| 733 | return ret_size; |
||
| 734 | |||
| 735 | |||
| 736 | static Bool RADEONPreInitVRAM(RHDPtr info) |
||
| 737 | |||
| 738 | u32_t accessible, bar_size; |
||
| 739 | |||
| 740 | if ((!IS_AVIVO_VARIANT) && info->IsIGP) |
||
| 741 | |||
| 742 | u32_t tom = INREG(RADEON_NB_TOM); |
||
| 743 | |||
| 744 | info->videoRam = (((tom >> 16) - |
||
| 745 | |||
| 746 | |||
| 747 | OUTREG(RADEON_CONFIG_MEMSIZE, info->videoRam * 1024); |
||
| 748 | |||
| 749 | else |
||
| 750 | { |
||
| 751 | if (info->ChipFamily >= CHIP_FAMILY_R600) |
||
| 752 | info->videoRam = INREG(R600_CONFIG_MEMSIZE) / 1024; |
||
| 753 | else |
||
| 754 | { |
||
| 755 | /* Read VRAM size from card */ |
||
| 756 | info->videoRam = INREG(RADEON_CONFIG_MEMSIZE) / 1024; |
||
| 757 | |||
| 758 | /* Some production boards of m6 will return 0 if it's 8 MB */ |
||
| 759 | |||
| 760 | { |
||
| 761 | info->videoRam = 8192; |
||
| 762 | OUTREG(RADEON_CONFIG_MEMSIZE, 0x800000); |
||
| 763 | } |
||
| 764 | } |
||
| 765 | } |
||
| 766 | |||
| 767 | RADEONGetVRamType(info); |
||
| 768 | |||
| 769 | /* Get accessible memory */ |
||
| 770 | |||
| 771 | |||
| 772 | /* Crop it to the size of the PCI BAR */ |
||
| 773 | |||
| 774 | |||
| 775 | bar_size = 1 << (info->memsize[RHD_FB_BAR] - 10); |
||
| 776 | |||
| 777 | if (bar_size == 0) |
||
| 778 | |||
| 779 | if (accessible > bar_size) |
||
| 780 | accessible = bar_size; |
||
| 781 | |||
| 782 | dbgprintf("Detected total video RAM=%dK width=%dbit," |
||
| 783 | |||
| 784 | info->videoRam, info->RamWidth, |
||
| 785 | (unsigned)accessible, (unsigned)bar_size); |
||
| 786 | |||
| 787 | if (info->videoRam > accessible) |
||
| 788 | |||
| 789 | |||
| 790 | if (!IS_AVIVO_VARIANT) |
||
| 791 | |||
| 792 | info->BusCntl = INREG(RADEON_BUS_CNTL); |
||
| 793 | |||
| 794 | info->videoRam &= ~1023; |
||
| 795 | |||
| 796 | |||
| 797 | // info->gartSize = RADEON_DEFAULT_GART_SIZE; |
||
| 798 | |||
| 799 | info->bufSize = RADEON_DEFAULT_BUFFER_SIZE; |
||
| 800 | |||
| 801 | // info->gartTexSize = info->gartSize - (info->ringSize + info->bufSize); |
||
| 802 | |||
| 803 | info->pciAperSize = RADEON_DEFAULT_PCI_APER_SIZE; |
||
| 804 | |||
| 805 | |||
| 806 | |||
| 807 | |||
| 808 | |||
| 809 | |||
| 810 | // if (info->cardType == CARD_PCIE ) |
||
| 811 | |||
| 812 | // info->FbSecureSize = RADEONDRIGetPciAperTableSize(info); |
||
| 813 | // else |
||
| 814 | // info->FbSecureSize = 0; |
||
| 815 | |||
| 816 | return TRUE; |
||
| 817 | |||
| 818 | |||
| 819 | |||
| 820 | |||
| 821 | |||
| 822 | u32_t cmd_stat; |
||
| 823 | |||
| 824 | rhdPtr->ChipErrata = 0; |
||
| 825 | |||
| 826 | if ( (rhdPtr->ChipFamily == CHIP_FAMILY_R300) && |
||
| 827 | |||
| 828 | == RADEON_CFG_ATI_REV_A11)) |
||
| 829 | rhdPtr->ChipErrata |= CHIP_ERRATA_R300_CG; |
||
| 830 | |||
| 831 | if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV200) || |
||
| 832 | |||
| 833 | rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DUMMYREADS; |
||
| 834 | |||
| 835 | if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RV100) || |
||
| 836 | |||
| 837 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS200) ) |
||
| 838 | rhdPtr->ChipErrata |= CHIP_ERRATA_PLL_DELAY; |
||
| 839 | |||
| 840 | rhdPtr->cardType = CARD_PCI; |
||
| 841 | |||
| 842 | |||
| 843 | |||
| 844 | |||
| 845 | if (cmd_stat & RADEON_CAP_LIST) |
||
| 846 | |||
| 847 | u32_t cap_ptr, cap_id; |
||
| 848 | |||
| 849 | cap_ptr = pciReadLong(rhdPtr->PciTag, RADEON_CAPABILITIES_PTR_PCI_CONFIG); |
||
| 850 | |||
| 851 | |||
| 852 | while(cap_ptr != RADEON_CAP_ID_NULL) |
||
| 853 | |||
| 854 | cap_id = pciReadLong(rhdPtr->PciTag, cap_ptr); |
||
| 855 | if ((cap_id & 0xff)== RADEON_CAP_ID_AGP) { |
||
| 856 | rhdPtr->cardType = CARD_AGP; |
||
| 857 | break; |
||
| 858 | } |
||
| 859 | if ((cap_id & 0xff)== RADEON_CAP_ID_EXP) { |
||
| 860 | rhdPtr->cardType = CARD_PCIE; |
||
| 861 | break; |
||
| 862 | } |
||
| 863 | cap_ptr = (cap_id >> 8) & RADEON_CAP_PTR_MASK; |
||
| 864 | } |
||
| 865 | } |
||
| 866 | |||
| 867 | dbgprintf("%s card detected\n",(rhdPtr->cardType==CARD_PCI) ? "PCI" : |
||
| 868 | |||
| 869 | |||
| 870 | /* treat PCIE IGP cards as PCI */ |
||
| 871 | |||
| 872 | rhdPtr->cardType = CARD_PCI; |
||
| 873 | |||
| 874 | if ( (rhdPtr->ChipFamily == CHIP_FAMILY_RS100) || |
||
| 875 | |||
| 876 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS300) || |
||
| 877 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS400) || |
||
| 878 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS480) || |
||
| 879 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS600) || |
||
| 880 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS690) || |
||
| 881 | (rhdPtr->ChipFamily == CHIP_FAMILY_RS740)) |
||
| 882 | rhdPtr->has_tcl = FALSE; |
||
| 883 | else { |
||
| 884 | rhdPtr->has_tcl = TRUE; |
||
| 885 | } |
||
| 886 | |||
| 887 | // rhdPtr->LinearAddr = rhdPtr->memBase[RHD_FB_BAR]; |
||
| 888 | |||
| 889 | return TRUE; |
||
| 890 | |||
| 891 | |||
| 892 | #if 0 |
||
| 893 | |||
| 894 | { |
||
| 895 | unsigned char *RADEONMMIO = info->MMIO; |
||
| 896 | // unsigned long mode = drmAgpGetMode(info->dri->drmFD); /* Default mode */ |
||
| 897 | // unsigned int vendor = drmAgpVendorId(info->dri->drmFD); |
||
| 898 | // unsigned int device = drmAgpDeviceId(info->dri->drmFD); |
||
| 899 | /* ignore agp 3.0 mode bit from the chip as it's buggy on some cards with |
||
| 900 | pcie-agp rialto bridge chip - use the one from bridge which must match */ |
||
| 901 | uint32_t agp_status = (INREG(RADEON_AGP_STATUS) ); // & RADEON_AGP_MODE_MASK; |
||
| 902 | Bool is_v3 = (agp_status & RADEON_AGPv3_MODE); |
||
| 903 | unsigned int defaultMode; |
||
| 904 | |||
| 905 | if (is_v3) { |
||
| 906 | |||
| 907 | } else { |
||
| 908 | if (agp_status & RADEON_AGP_4X_MODE) defaultMode = 4; |
||
| 909 | else if (agp_status & RADEON_AGP_2X_MODE) defaultMode = 2; |
||
| 910 | else defaultMode = 1; |
||
| 911 | } |
||
| 912 | |||
| 913 | // agpMode = defaultMode; |
||
| 914 | |||
| 915 | dbgprintf(pScreen->myNum, from, "Using AGP %dx\n", dbgprintf); |
||
| 916 | |||
| 917 | mode &= ~RADEON_AGP_MODE_MASK; |
||
| 918 | |||
| 919 | /* only set one mode bit for AGPv3 */ |
||
| 920 | switch (defaultMode) { |
||
| 921 | case 8: mode |= RADEON_AGPv3_8X_MODE; break; |
||
| 922 | case 4: default: mode |= RADEON_AGPv3_4X_MODE; |
||
| 923 | } |
||
| 924 | /*TODO: need to take care of other bits valid for v3 mode |
||
| 925 | * currently these bits are not used in all tested cards. |
||
| 926 | */ |
||
| 927 | } else { |
||
| 928 | switch (defaultMode) { |
||
| 929 | case 4: mode |= RADEON_AGP_4X_MODE; |
||
| 930 | case 2: mode |= RADEON_AGP_2X_MODE; |
||
| 931 | case 1: default: mode |= RADEON_AGP_1X_MODE; |
||
| 932 | } |
||
| 933 | } |
||
| 934 | |||
| 935 | /* AGP Fast Writes. |
||
| 936 | |||
| 937 | * writes at all */ |
||
| 938 | mode &= ~RADEON_AGP_FW_MODE; /* Disable per default */ |
||
| 939 | |||
| 940 | dbgprintf("AGP Mode 0x%08lx\n", mode); |
||
| 941 | |||
| 942 | if (drmAgpEnable(info->dri->drmFD, mode) < 0) { |
||
| 943 | |||
| 944 | drmAgpRelease(info->dri->drmFD); |
||
| 945 | return FALSE; |
||
| 946 | } |
||
| 947 | |||
| 948 | /* Workaround for some hardware bugs */ |
||
| 949 | |||
| 950 | OUTREG(RADEON_AGP_CNTL, INREG(RADEON_AGP_CNTL) | 0x000e0000); |
||
| 951 | |||
| 952 | /* Modify the mode if the default mode |
||
| 953 | |||
| 954 | * particular combination of graphics |
||
| 955 | * card and AGP chipset. |
||
| 956 | */ |
||
| 957 | |||
| 958 | return TRUE; |
||
| 959 | |||
| 960 | #endif |
||
| 961 | |||
| 962 | Bool RHDPreInit() |
||
| 963 | |||
| 964 | RHDPtr info; |
||
| 965 | |||
| 966 | /* We need access to IO space already */ |
||
| 967 | |||
| 968 | dbgprintf("Failed to map MMIO.\n"); |
||
| 969 | return FALSE; |
||
| 970 | }; |
||
| 971 | |||
| 972 | if( !RADEONPreInitChipType(&rhd)) |
||
| 973 | |||
| 974 | |||
| 975 | if (!RADEONPreInitVRAM(&rhd)) |
||
| 976 | |||
| 977 | |||
| 978 | RADEONInitMemoryMap(&rhd); |
||
| 979 | |||
| 980 | if (!rhd.videoRam) |
||
| 981 | |||
| 982 | dbgprintf("No Video RAM detected.\n"); |
||
| 983 | goto error1; |
||
| 984 | } |
||
| 985 | dbgprintf("VideoRAM: %d kByte\n",rhd.videoRam); |
||
| 986 | |||
| 987 | /* setup the raster pipes */ |
||
| 988 | |||
| 989 | |||
| 990 | init_gart(&rhd); |
||
| 991 | |||
| 992 | rhd.FbFreeSize = rhd.videoRam << 10; |
||
| 993 | |||
| 994 | rhd.FbFreeStart = 10*1024*1024; |
||
| 995 | |||
| 996 | |||
| 997 | rhdInitHeap(&rhd); |
||
| 998 | |||
| 999 | info = &rhd; |
||
| 1000 | |||
| 1001 | return TRUE; |
||
| 1002 | |||
| 1003 | error1: |
||
| 1004 | |||
| 1005 | return FALSE; |
||
| 1006 | |||
| 1007 | |||
| 1008 | static void RADEONPllErrataAfterIndex() |
||
| 1009 | |||
| 1010 | if (!(rhd.ChipErrata & CHIP_ERRATA_PLL_DUMMYREADS)) |
||
| 1011 | return; |
||
| 1012 | |||
| 1013 | /* This workaround is necessary on rv200 and RS200 or PLL |
||
| 1014 | |||
| 1015 | */ |
||
| 1016 | (void)INREG(RADEON_CLOCK_CNTL_DATA); |
||
| 1017 | (void)INREG(RADEON_CRTC_GEN_CNTL); |
||
| 1018 | } |
||
| 1019 | |||
| 1020 | |||
| 1021 | |||
| 1022 | |||
| 1023 | |||
| 1024 | /* This function is required to workaround a hardware bug in some (all?) |
||
| 1025 | |||
| 1026 | * CLOCK_CNTL_INDEX register access. If not, register reads afterward |
||
| 1027 | * may not be correct. |
||
| 1028 | */ |
||
| 1029 | if (rhd.ChipFamily <= CHIP_FAMILY_RV380) |
||
| 1030 | { |
||
| 1031 | u32_t save, tmp; |
||
| 1032 | |||
| 1033 | save = INREG(RADEON_CLOCK_CNTL_INDEX); |
||
| 1034 | |||
| 1035 | OUTREG(RADEON_CLOCK_CNTL_INDEX, tmp); |
||
| 1036 | tmp = INREG(RADEON_CLOCK_CNTL_DATA); |
||
| 1037 | OUTREG(RADEON_CLOCK_CNTL_INDEX, save); |
||
| 1038 | } |
||
| 1039 | } |
||
| 1040 | |||
| 1041 | |||
| 1042 | |||
| 1043 | |||
| 1044 | { |
||
| 1045 | u32_t data; |
||
| 1046 | |||
| 1047 | OUTREG8(RADEON_CLOCK_CNTL_INDEX, addr & 0x3f); |
||
| 1048 | |||
| 1049 | data = INREG(RADEON_CLOCK_CNTL_DATA); |
||
| 1050 | RADEONPllErrataAfterData(); |
||
| 1051 | |||
| 1052 | return data; |
||
| 1053 | |||
| 1054 | |||
| 1055 | /* Write PLL information */ |
||
| 1056 | |||
| 1057 | { |
||
| 1058 | OUTREG8(RADEON_CLOCK_CNTL_INDEX, (((addr) & 0x3f) | |
||
| 1059 | RADEON_PLL_WR_EN)); |
||
| 1060 | RADEONPllErrataAfterIndex(); |
||
| 1061 | OUTREG(RADEON_CLOCK_CNTL_DATA, data); |
||
| 1062 | RADEONPllErrataAfterData(); |
||
| 1063 | } |
||
| 1064 | |||
| 1065 | static void init_pipes(RHDPtr info) |
||
| 1066 | |||
| 1067 | u32_t gb_tile_config = 0; |
||
| 1068 | |||
| 1069 | if ( (info->ChipFamily == CHIP_FAMILY_RV410) || |
||
| 1070 | |||
| 1071 | (info->ChipFamily == CHIP_FAMILY_RS600) || |
||
| 1072 | (info->ChipFamily == CHIP_FAMILY_RS690) || |
||
| 1073 | (info->ChipFamily == CHIP_FAMILY_RS740) || |
||
| 1074 | (info->ChipFamily == CHIP_FAMILY_RS400) || |
||
| 1075 | (info->ChipFamily == CHIP_FAMILY_RS480) || IS_R500_3D) |
||
| 1076 | { |
||
| 1077 | u32_t gb_pipe_sel = INREG(R400_GB_PIPE_SELECT); |
||
| 1078 | |||
| 1079 | info->num_gb_pipes = ((gb_pipe_sel >> 12) & 0x3) + 1; |
||
| 1080 | |||
| 1081 | OUTPLL(R500_DYN_SCLK_PWMEM_PIPE, (1 | ((gb_pipe_sel >> 8) & 0xf) << 4)); |
||
| 1082 | } |
||
| 1083 | else |
||
| 1084 | { |
||
| 1085 | if ((info->ChipFamily == CHIP_FAMILY_R300) || |
||
| 1086 | (info->ChipFamily == CHIP_FAMILY_R350)) |
||
| 1087 | { |
||
| 1088 | /* R3xx chips */ |
||
| 1089 | info->num_gb_pipes = 2; |
||
| 1090 | } |
||
| 1091 | else { |
||
| 1092 | /* RV3xx chips */ |
||
| 1093 | info->num_gb_pipes = 1; |
||
| 1094 | } |
||
| 1095 | } |
||
| 1096 | |||
| 1097 | if (IS_R300_3D || IS_R500_3D) |
||
| 1098 | |||
| 1099 | |||
| 1100 | dbgprintf("num quad-pipes is %d\n", info->num_gb_pipes); |
||
| 1101 | |||
| 1102 | switch(info->num_gb_pipes) { |
||
| 1103 | |||
| 1104 | case 3: gb_tile_config |= R300_PIPE_COUNT_R420_3P; break; |
||
| 1105 | case 4: gb_tile_config |= R300_PIPE_COUNT_R420; break; |
||
| 1106 | default: |
||
| 1107 | case 1: gb_tile_config |= R300_PIPE_COUNT_RV350; break; |
||
| 1108 | } |
||
| 1109 | |||
| 1110 | OUTREG(R300_GB_TILE_CONFIG, gb_tile_config); |
||
| 1111 | |||
| 1112 | OUTREG(R300_DST_PIPE_CONFIG, INREG(R300_DST_PIPE_CONFIG) | R300_PIPE_AUTO_CONFIG); |
||
| 1113 | OUTREG(R300_RB2D_DSTCACHE_MODE, (INREG(R300_RB2D_DSTCACHE_MODE) | |
||
| 1114 | R300_DC_AUTOFLUSH_ENABLE | |
||
| 1115 | R300_DC_DC_DISABLE_IGNORE_PE)); |
||
| 1116 | } |
||
| 1117 | else |
||
| 1118 | OUTREG(RADEON_RB3D_CNTL, 0); |
||
| 1119 | }; |
||
| 1120 | |||
| 1121 | #define RADEON_AIC_PT_BASE 0x01d8 |
||
| 1122 | |||
| 1123 | #define RADEON_AIC_HI_ADDR 0x01e0 |
||
| 1124 | #define RADEON_AIC_TLB_ADDR 0x01e4 |
||
| 1125 | #define RADEON_AIC_TLB_DATA 0x01e8 |
||
| 1126 | |||
| 1127 | #define RADEON_PCIE_INDEX 0x0030 |
||
| 1128 | |||
| 1129 | #define RADEON_PCIE_TX_GART_CNTL 0x10 |
||
| 1130 | # define RADEON_PCIE_TX_GART_EN (1 << 0) |
||
| 1131 | # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_PASS_THRU (0 << 1) |
||
| 1132 | # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_CLAMP_LO (1 << 1) |
||
| 1133 | # define RADEON_PCIE_TX_GART_UNMAPPED_ACCESS_DISCARD (3 << 1) |
||
| 1134 | # define RADEON_PCIE_TX_GART_MODE_32_128_CACHE (0 << 3) |
||
| 1135 | # define RADEON_PCIE_TX_GART_MODE_8_4_128_CACHE (1 << 3) |
||
| 1136 | # define RADEON_PCIE_TX_GART_CHK_RW_VALID_EN (1 << 5) |
||
| 1137 | # define RADEON_PCIE_TX_GART_INVALIDATE_TLB (1 << 8) |
||
| 1138 | #define RADEON_PCIE_TX_DISCARD_RD_ADDR_LO 0x11 |
||
| 1139 | #define RADEON_PCIE_TX_DISCARD_RD_ADDR_HI 0x12 |
||
| 1140 | #define RADEON_PCIE_TX_GART_BASE 0x13 |
||
| 1141 | #define RADEON_PCIE_TX_GART_START_LO 0x14 |
||
| 1142 | #define RADEON_PCIE_TX_GART_START_HI 0x15 |
||
| 1143 | #define RADEON_PCIE_TX_GART_END_LO 0x16 |
||
| 1144 | #define RADEON_PCIE_TX_GART_END_HI 0x17 |
||
| 1145 | |||
| 1146 | |||
| 1147 | |||
| 1148 | |||
| 1149 | |||
| 1150 | #define RADEON_WRITE_PCIE( addr, val ) \ |
||
| 1151 | |||
| 1152 | RADEON_WRITE8( RADEON_PCIE_INDEX, \ |
||
| 1153 | ((addr) & 0xff)); \ |
||
| 1154 | OUTREG( RADEON_PCIE_DATA, (val) ); \ |
||
| 1155 | } while (0) |
||
| 1156 | |||
| 1157 | static u32_t RADEON_READ_PCIE(int addr) |
||
| 1158 | |||
| 1159 | RADEON_WRITE8(RADEON_PCIE_INDEX, addr & 0xff); |
||
| 1160 | return INREG(RADEON_PCIE_DATA); |
||
| 1161 | } |
||
| 1162 | |||
| 1163 | static void radeon_set_pciegart(RHDPtr info, int on) |
||
| 1164 | |||
| 1165 | u32_t tmp = RADEON_READ_PCIE(RADEON_PCIE_TX_GART_CNTL); |
||
| 1166 | if (on) |
||
| 1167 | { |
||
| 1168 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_DISCARD_RD_ADDR_LO, |
||
| 1169 | info->gart_vm_start); |
||
| 1170 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_BASE, |
||
| 1171 | info->gart_table_dma); |
||
| 1172 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_START_LO, |
||
| 1173 | info->gart_vm_start); |
||
| 1174 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_END_LO, |
||
| 1175 | info->gart_vm_start + info->gart_size - 1); |
||
| 1176 | |||
| 1177 | // radeon_write_agp_location(dev_priv, 0xffffffc0); /* ?? */ |
||
| 1178 | |||
| 1179 | |||
| 1180 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, |
||
| 1181 | |||
| 1182 | } else { |
||
| 1183 | RADEON_WRITE_PCIE(RADEON_PCIE_TX_GART_CNTL, |
||
| 1184 | tmp & ~RADEON_PCIE_TX_GART_EN); |
||
| 1185 | } |
||
| 1186 | } |
||
| 1187 | |||
| 1188 | |||
| 1189 | |||
| 1190 | |||
| 1191 | u32_t tmp; |
||
| 1192 | |||
| 1193 | tmp = INREG(RADEON_AIC_CNTL); |
||
| 1194 | |||
| 1195 | if( on ) |
||
| 1196 | |||
| 1197 | OUTREG(RADEON_AIC_CNTL, tmp | RADEON_PCIGART_TRANSLATE_EN); |
||
| 1198 | |||
| 1199 | /* set PCI GART page-table base address |
||
| 1200 | |||
| 1201 | OUTREG(RADEON_AIC_PT_BASE, info->gart_table_dma); |
||
| 1202 | |||
| 1203 | /* set address range for PCI address translate |
||
| 1204 | |||
| 1205 | OUTREG(RADEON_AIC_LO_ADDR, info->gart_vm_start); |
||
| 1206 | OUTREG(RADEON_AIC_HI_ADDR, info->gart_vm_start |
||
| 1207 | + info->gart_size - 1); |
||
| 1208 | |||
| 1209 | /* Turn off AGP aperture -- is this required for PCI GART? |
||
| 1210 | |||
| 1211 | // radeon_write_agp_location(dev_priv, 0xffffffc0); |
||
| 1212 | OUTREG(RADEON_AGP_COMMAND, 0); /* clear AGP_COMMAND */ |
||
| 1213 | } |
||
| 1214 | else OUTREG(RADEON_AIC_CNTL, tmp & ~RADEON_PCIGART_TRANSLATE_EN); |
||
| 1215 | |||
| 1216 | } |
||
| 1217 | |||
| 1218 | |||
| 1219 | |||
| 1220 | |||
| 1221 | u32_t *pci_gart; |
||
| 1222 | count_t pages; |
||
| 1223 | |||
| 1224 | info->gart_size = 16*1024*1024; |
||
| 1225 | |||
| 1226 | info->gart_vm_start = info->fbLocation + (info->videoRam << 10); |
||
| 1227 | |||
| 1228 | |||
| 1229 | |||
| 1230 | |||
| 1231 | - RADEON_PCIGART_TABLE_SIZE; |
||
| 1232 | else |
||
| 1233 | info->gart_table_dma = AllocPages(RADEON_PCIGART_TABLE_SIZE >> 12); |
||
| 1234 | |||
| 1235 | if ( ! info->gart_table_dma) { |
||
| 1236 | |||
| 1237 | return; |
||
| 1238 | } |
||
| 1239 | |||
| 1240 | info->gart_table = (u32_t*)MapIoMem(info->gart_table_dma, |
||
| 1241 | |||
| 1242 | PG_SW | PG_NOCACHE); |
||
| 1243 | |||
| 1244 | if ( ! info->gart_table) { |
||
| 1245 | |||
| 1246 | return; |
||
| 1247 | } |
||
| 1248 | |||
| 1249 | pci_gart = info->gart_table; |
||
| 1250 | |||
| 1251 | memset(pci_gart, 0, RADEON_PCIGART_TABLE_SIZE); |
||
| 1252 | |||
| 1253 | __asm__ __volatile( |
||
| 1254 | |||
| 1255 | :::"memory"); |
||
| 1256 | |||
| 1257 | if( info->gart_type == RADEON_IS_PCIE) |
||
| 1258 | |||
| 1259 | else |
||
| 1260 | radeon_set_pcigart(info, 1); |
||
| 1261 | |||
| 1262 | dbgprintf("gart size 0x%x\n", info->gart_size); |
||
| 1263 | |||
| 1264 | dbgprintf("gart table 0x%x\n", info->gart_table); |
||
| 1265 | dbgprintf("gart table dma 0x%x\n", info->gart_table_dma); |
||
| 1266 | |||
| 1267 | } |
||
| 1268 |