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2967 | Serge | 1 | /* |
2 | * Copyright © 2007-2008 Intel Corporation |
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3 | * Jesse Barnes |
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4 | * |
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5 | * Permission is hereby granted, free of charge, to any person obtaining a |
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6 | * copy of this software and associated documentation files (the "Software"), |
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7 | * to deal in the Software without restriction, including without limitation |
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8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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9 | * and/or sell copies of the Software, and to permit persons to whom the |
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10 | * Software is furnished to do so, subject to the following conditions: |
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11 | * |
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12 | * The above copyright notice and this permission notice shall be included in |
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13 | * all copies or substantial portions of the Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR |
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19 | * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
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20 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
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21 | * OTHER DEALINGS IN THE SOFTWARE. |
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22 | */ |
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23 | #ifndef __DRM_EDID_H__ |
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24 | #define __DRM_EDID_H__ |
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25 | |||
26 | #include |
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27 | |||
28 | #define EDID_LENGTH 128 |
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29 | #define DDC_ADDR 0x50 |
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5270 | serge | 30 | #define DDC_ADDR2 0x52 /* E-DDC 1.2 - where DisplayID can hide */ |
2967 | Serge | 31 | |
32 | #define CEA_EXT 0x02 |
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33 | #define VTB_EXT 0x10 |
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34 | #define DI_EXT 0x40 |
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35 | #define LS_EXT 0x50 |
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36 | #define MI_EXT 0x60 |
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5270 | serge | 37 | #define DISPLAYID_EXT 0x70 |
2967 | Serge | 38 | |
39 | struct est_timings { |
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40 | u8 t1; |
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41 | u8 t2; |
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42 | u8 mfg_rsvd; |
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43 | } __attribute__((packed)); |
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44 | |||
45 | /* 00=16:10, 01=4:3, 10=5:4, 11=16:9 */ |
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46 | #define EDID_TIMING_ASPECT_SHIFT 6 |
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47 | #define EDID_TIMING_ASPECT_MASK (0x3 << EDID_TIMING_ASPECT_SHIFT) |
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48 | |||
49 | /* need to add 60 */ |
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50 | #define EDID_TIMING_VFREQ_SHIFT 0 |
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51 | #define EDID_TIMING_VFREQ_MASK (0x3f << EDID_TIMING_VFREQ_SHIFT) |
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52 | |||
53 | struct std_timing { |
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54 | u8 hsize; /* need to multiply by 8 then add 248 */ |
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55 | u8 vfreq_aspect; |
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56 | } __attribute__((packed)); |
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57 | |||
58 | #define DRM_EDID_PT_HSYNC_POSITIVE (1 << 1) |
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59 | #define DRM_EDID_PT_VSYNC_POSITIVE (1 << 2) |
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60 | #define DRM_EDID_PT_SEPARATE_SYNC (3 << 3) |
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61 | #define DRM_EDID_PT_STEREO (1 << 5) |
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62 | #define DRM_EDID_PT_INTERLACED (1 << 7) |
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63 | |||
64 | /* If detailed data is pixel timing */ |
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65 | struct detailed_pixel_timing { |
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66 | u8 hactive_lo; |
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67 | u8 hblank_lo; |
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68 | u8 hactive_hblank_hi; |
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69 | u8 vactive_lo; |
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70 | u8 vblank_lo; |
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71 | u8 vactive_vblank_hi; |
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72 | u8 hsync_offset_lo; |
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73 | u8 hsync_pulse_width_lo; |
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74 | u8 vsync_offset_pulse_width_lo; |
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75 | u8 hsync_vsync_offset_pulse_width_hi; |
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76 | u8 width_mm_lo; |
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77 | u8 height_mm_lo; |
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78 | u8 width_height_mm_hi; |
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79 | u8 hborder; |
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80 | u8 vborder; |
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81 | u8 misc; |
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82 | } __attribute__((packed)); |
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83 | |||
84 | /* If it's not pixel timing, it'll be one of the below */ |
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85 | struct detailed_data_string { |
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86 | u8 str[13]; |
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87 | } __attribute__((packed)); |
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88 | |||
89 | struct detailed_data_monitor_range { |
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90 | u8 min_vfreq; |
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91 | u8 max_vfreq; |
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92 | u8 min_hfreq_khz; |
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93 | u8 max_hfreq_khz; |
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94 | u8 pixel_clock_mhz; /* need to multiply by 10 */ |
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3031 | serge | 95 | u8 flags; |
96 | union { |
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97 | struct { |
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98 | u8 reserved; |
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6082 | serge | 99 | u8 hfreq_start_khz; /* need to multiply by 2 */ |
100 | u8 c; /* need to divide by 2 */ |
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101 | __le16 m; |
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102 | u8 k; |
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103 | u8 j; /* need to divide by 2 */ |
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3031 | serge | 104 | } __attribute__((packed)) gtf2; |
105 | struct { |
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106 | u8 version; |
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107 | u8 data1; /* high 6 bits: extra clock resolution */ |
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108 | u8 data2; /* plus low 2 of above: max hactive */ |
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109 | u8 supported_aspects; |
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110 | u8 flags; /* preferred aspect and blanking support */ |
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111 | u8 supported_scalings; |
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112 | u8 preferred_refresh; |
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113 | } __attribute__((packed)) cvt; |
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114 | } formula; |
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2967 | Serge | 115 | } __attribute__((packed)); |
116 | |||
117 | struct detailed_data_wpindex { |
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118 | u8 white_yx_lo; /* Lower 2 bits each */ |
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119 | u8 white_x_hi; |
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120 | u8 white_y_hi; |
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121 | u8 gamma; /* need to divide by 100 then add 1 */ |
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122 | } __attribute__((packed)); |
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123 | |||
124 | struct detailed_data_color_point { |
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125 | u8 windex1; |
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126 | u8 wpindex1[3]; |
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127 | u8 windex2; |
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128 | u8 wpindex2[3]; |
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129 | } __attribute__((packed)); |
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130 | |||
131 | struct cvt_timing { |
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132 | u8 code[3]; |
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133 | } __attribute__((packed)); |
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134 | |||
135 | struct detailed_non_pixel { |
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136 | u8 pad1; |
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137 | u8 type; /* ff=serial, fe=string, fd=monitor range, fc=monitor name |
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138 | fb=color point data, fa=standard timing data, |
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139 | f9=undefined, f8=mfg. reserved */ |
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140 | u8 pad2; |
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141 | union { |
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142 | struct detailed_data_string str; |
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143 | struct detailed_data_monitor_range range; |
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144 | struct detailed_data_wpindex color; |
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145 | struct std_timing timings[6]; |
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146 | struct cvt_timing cvt[4]; |
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147 | } data; |
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148 | } __attribute__((packed)); |
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149 | |||
150 | #define EDID_DETAIL_EST_TIMINGS 0xf7 |
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151 | #define EDID_DETAIL_CVT_3BYTE 0xf8 |
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152 | #define EDID_DETAIL_COLOR_MGMT_DATA 0xf9 |
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153 | #define EDID_DETAIL_STD_MODES 0xfa |
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154 | #define EDID_DETAIL_MONITOR_CPDATA 0xfb |
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155 | #define EDID_DETAIL_MONITOR_NAME 0xfc |
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156 | #define EDID_DETAIL_MONITOR_RANGE 0xfd |
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157 | #define EDID_DETAIL_MONITOR_STRING 0xfe |
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158 | #define EDID_DETAIL_MONITOR_SERIAL 0xff |
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159 | |||
160 | struct detailed_timing { |
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161 | __le16 pixel_clock; /* need to multiply by 10 KHz */ |
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162 | union { |
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163 | struct detailed_pixel_timing pixel_data; |
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164 | struct detailed_non_pixel other_data; |
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165 | } data; |
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166 | } __attribute__((packed)); |
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167 | |||
168 | #define DRM_EDID_INPUT_SERRATION_VSYNC (1 << 0) |
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169 | #define DRM_EDID_INPUT_SYNC_ON_GREEN (1 << 1) |
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170 | #define DRM_EDID_INPUT_COMPOSITE_SYNC (1 << 2) |
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171 | #define DRM_EDID_INPUT_SEPARATE_SYNCS (1 << 3) |
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172 | #define DRM_EDID_INPUT_BLANK_TO_BLACK (1 << 4) |
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173 | #define DRM_EDID_INPUT_VIDEO_LEVEL (3 << 5) |
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174 | #define DRM_EDID_INPUT_DIGITAL (1 << 7) |
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175 | #define DRM_EDID_DIGITAL_DEPTH_MASK (7 << 4) |
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176 | #define DRM_EDID_DIGITAL_DEPTH_UNDEF (0 << 4) |
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177 | #define DRM_EDID_DIGITAL_DEPTH_6 (1 << 4) |
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178 | #define DRM_EDID_DIGITAL_DEPTH_8 (2 << 4) |
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179 | #define DRM_EDID_DIGITAL_DEPTH_10 (3 << 4) |
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180 | #define DRM_EDID_DIGITAL_DEPTH_12 (4 << 4) |
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181 | #define DRM_EDID_DIGITAL_DEPTH_14 (5 << 4) |
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182 | #define DRM_EDID_DIGITAL_DEPTH_16 (6 << 4) |
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183 | #define DRM_EDID_DIGITAL_DEPTH_RSVD (7 << 4) |
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184 | #define DRM_EDID_DIGITAL_TYPE_UNDEF (0) |
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185 | #define DRM_EDID_DIGITAL_TYPE_DVI (1) |
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186 | #define DRM_EDID_DIGITAL_TYPE_HDMI_A (2) |
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187 | #define DRM_EDID_DIGITAL_TYPE_HDMI_B (3) |
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188 | #define DRM_EDID_DIGITAL_TYPE_MDDI (4) |
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189 | #define DRM_EDID_DIGITAL_TYPE_DP (5) |
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190 | |||
191 | #define DRM_EDID_FEATURE_DEFAULT_GTF (1 << 0) |
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192 | #define DRM_EDID_FEATURE_PREFERRED_TIMING (1 << 1) |
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193 | #define DRM_EDID_FEATURE_STANDARD_COLOR (1 << 2) |
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194 | /* If analog */ |
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195 | #define DRM_EDID_FEATURE_DISPLAY_TYPE (3 << 3) /* 00=mono, 01=rgb, 10=non-rgb, 11=unknown */ |
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196 | /* If digital */ |
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197 | #define DRM_EDID_FEATURE_COLOR_MASK (3 << 3) |
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198 | #define DRM_EDID_FEATURE_RGB (0 << 3) |
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199 | #define DRM_EDID_FEATURE_RGB_YCRCB444 (1 << 3) |
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200 | #define DRM_EDID_FEATURE_RGB_YCRCB422 (2 << 3) |
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201 | #define DRM_EDID_FEATURE_RGB_YCRCB (3 << 3) /* both 4:4:4 and 4:2:2 */ |
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202 | |||
203 | #define DRM_EDID_FEATURE_PM_ACTIVE_OFF (1 << 5) |
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204 | #define DRM_EDID_FEATURE_PM_SUSPEND (1 << 6) |
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205 | #define DRM_EDID_FEATURE_PM_STANDBY (1 << 7) |
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206 | |||
5056 | serge | 207 | #define DRM_EDID_HDMI_DC_48 (1 << 6) |
208 | #define DRM_EDID_HDMI_DC_36 (1 << 5) |
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209 | #define DRM_EDID_HDMI_DC_30 (1 << 4) |
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210 | #define DRM_EDID_HDMI_DC_Y444 (1 << 3) |
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211 | |||
5270 | serge | 212 | /* ELD Header Block */ |
213 | #define DRM_ELD_HEADER_BLOCK_SIZE 4 |
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214 | |||
215 | #define DRM_ELD_VER 0 |
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216 | # define DRM_ELD_VER_SHIFT 3 |
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217 | # define DRM_ELD_VER_MASK (0x1f << 3) |
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6082 | serge | 218 | # define DRM_ELD_VER_CEA861D (2 << 3) /* supports 861D or below */ |
219 | # define DRM_ELD_VER_CANNED (0x1f << 3) |
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5270 | serge | 220 | |
221 | #define DRM_ELD_BASELINE_ELD_LEN 2 /* in dwords! */ |
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222 | |||
223 | /* ELD Baseline Block for ELD_Ver == 2 */ |
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224 | #define DRM_ELD_CEA_EDID_VER_MNL 4 |
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225 | # define DRM_ELD_CEA_EDID_VER_SHIFT 5 |
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226 | # define DRM_ELD_CEA_EDID_VER_MASK (7 << 5) |
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227 | # define DRM_ELD_CEA_EDID_VER_NONE (0 << 5) |
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228 | # define DRM_ELD_CEA_EDID_VER_CEA861 (1 << 5) |
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229 | # define DRM_ELD_CEA_EDID_VER_CEA861A (2 << 5) |
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230 | # define DRM_ELD_CEA_EDID_VER_CEA861BCD (3 << 5) |
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231 | # define DRM_ELD_MNL_SHIFT 0 |
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232 | # define DRM_ELD_MNL_MASK (0x1f << 0) |
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233 | |||
234 | #define DRM_ELD_SAD_COUNT_CONN_TYPE 5 |
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235 | # define DRM_ELD_SAD_COUNT_SHIFT 4 |
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236 | # define DRM_ELD_SAD_COUNT_MASK (0xf << 4) |
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237 | # define DRM_ELD_CONN_TYPE_SHIFT 2 |
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238 | # define DRM_ELD_CONN_TYPE_MASK (3 << 2) |
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239 | # define DRM_ELD_CONN_TYPE_HDMI (0 << 2) |
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240 | # define DRM_ELD_CONN_TYPE_DP (1 << 2) |
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241 | # define DRM_ELD_SUPPORTS_AI (1 << 1) |
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242 | # define DRM_ELD_SUPPORTS_HDCP (1 << 0) |
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243 | |||
244 | #define DRM_ELD_AUD_SYNCH_DELAY 6 /* in units of 2 ms */ |
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245 | # define DRM_ELD_AUD_SYNCH_DELAY_MAX 0xfa /* 500 ms */ |
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246 | |||
247 | #define DRM_ELD_SPEAKER 7 |
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248 | # define DRM_ELD_SPEAKER_RLRC (1 << 6) |
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249 | # define DRM_ELD_SPEAKER_FLRC (1 << 5) |
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250 | # define DRM_ELD_SPEAKER_RC (1 << 4) |
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251 | # define DRM_ELD_SPEAKER_RLR (1 << 3) |
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252 | # define DRM_ELD_SPEAKER_FC (1 << 2) |
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253 | # define DRM_ELD_SPEAKER_LFE (1 << 1) |
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254 | # define DRM_ELD_SPEAKER_FLR (1 << 0) |
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255 | |||
256 | #define DRM_ELD_PORT_ID 8 /* offsets 8..15 inclusive */ |
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257 | # define DRM_ELD_PORT_ID_LEN 8 |
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258 | |||
259 | #define DRM_ELD_MANUFACTURER_NAME0 16 |
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260 | #define DRM_ELD_MANUFACTURER_NAME1 17 |
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261 | |||
262 | #define DRM_ELD_PRODUCT_CODE0 18 |
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263 | #define DRM_ELD_PRODUCT_CODE1 19 |
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264 | |||
265 | #define DRM_ELD_MONITOR_NAME_STRING 20 /* offsets 20..(20+mnl-1) inclusive */ |
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266 | |||
267 | #define DRM_ELD_CEA_SAD(mnl, sad) (20 + (mnl) + 3 * (sad)) |
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268 | |||
2967 | Serge | 269 | struct edid { |
270 | u8 header[8]; |
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271 | /* Vendor & product info */ |
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272 | u8 mfg_id[2]; |
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273 | u8 prod_code[2]; |
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274 | u32 serial; /* FIXME: byte order */ |
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275 | u8 mfg_week; |
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276 | u8 mfg_year; |
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277 | /* EDID version */ |
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278 | u8 version; |
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279 | u8 revision; |
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280 | /* Display info: */ |
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281 | u8 input; |
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282 | u8 width_cm; |
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283 | u8 height_cm; |
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284 | u8 gamma; |
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285 | u8 features; |
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286 | /* Color characteristics */ |
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287 | u8 red_green_lo; |
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288 | u8 black_white_lo; |
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289 | u8 red_x; |
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290 | u8 red_y; |
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291 | u8 green_x; |
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292 | u8 green_y; |
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293 | u8 blue_x; |
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294 | u8 blue_y; |
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295 | u8 white_x; |
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296 | u8 white_y; |
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297 | /* Est. timings and mfg rsvd timings*/ |
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298 | struct est_timings established_timings; |
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299 | /* Standard timings 1-8*/ |
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300 | struct std_timing standard_timings[8]; |
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301 | /* Detailing timings 1-4 */ |
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302 | struct detailed_timing detailed_timings[4]; |
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303 | /* Number of 128 byte ext. blocks */ |
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304 | u8 extensions; |
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305 | /* Checksum */ |
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306 | u8 checksum; |
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307 | } __attribute__((packed)); |
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308 | |||
309 | #define EDID_PRODUCT_ID(e) ((e)->prod_code[0] | ((e)->prod_code[1] << 8)) |
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310 | |||
3747 | Serge | 311 | /* Short Audio Descriptor */ |
312 | struct cea_sad { |
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313 | u8 format; |
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314 | u8 channels; /* max number of channels - 1 */ |
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315 | u8 freq; |
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316 | u8 byte2; /* meaning depends on format */ |
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317 | }; |
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318 | |||
2967 | Serge | 319 | struct drm_encoder; |
320 | struct drm_connector; |
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321 | struct drm_display_mode; |
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3391 | Serge | 322 | struct hdmi_avi_infoframe; |
4103 | Serge | 323 | struct hdmi_vendor_infoframe; |
3391 | Serge | 324 | |
2967 | Serge | 325 | void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid); |
3747 | Serge | 326 | int drm_edid_to_sad(struct edid *edid, struct cea_sad **sads); |
4103 | Serge | 327 | int drm_edid_to_speaker_allocation(struct edid *edid, u8 **sadb); |
2967 | Serge | 328 | int drm_av_sync_delay(struct drm_connector *connector, |
6082 | serge | 329 | const struct drm_display_mode *mode); |
330 | struct drm_connector *drm_select_eld(struct drm_encoder *encoder); |
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3031 | serge | 331 | int drm_load_edid_firmware(struct drm_connector *connector); |
2967 | Serge | 332 | |
3391 | Serge | 333 | int |
334 | drm_hdmi_avi_infoframe_from_display_mode(struct hdmi_avi_infoframe *frame, |
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335 | const struct drm_display_mode *mode); |
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4103 | Serge | 336 | int |
337 | drm_hdmi_vendor_infoframe_from_display_mode(struct hdmi_vendor_infoframe *frame, |
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338 | const struct drm_display_mode *mode); |
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3391 | Serge | 339 | |
5270 | serge | 340 | /** |
341 | * drm_eld_mnl - Get ELD monitor name length in bytes. |
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342 | * @eld: pointer to an eld memory structure with mnl set |
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343 | */ |
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344 | static inline int drm_eld_mnl(const uint8_t *eld) |
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345 | { |
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346 | return (eld[DRM_ELD_CEA_EDID_VER_MNL] & DRM_ELD_MNL_MASK) >> DRM_ELD_MNL_SHIFT; |
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347 | } |
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348 | |||
349 | /** |
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6082 | serge | 350 | * drm_eld_sad - Get ELD SAD structures. |
351 | * @eld: pointer to an eld memory structure with sad_count set |
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352 | */ |
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353 | static inline const uint8_t *drm_eld_sad(const uint8_t *eld) |
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354 | { |
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355 | unsigned int ver, mnl; |
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356 | |||
357 | ver = (eld[DRM_ELD_VER] & DRM_ELD_VER_MASK) >> DRM_ELD_VER_SHIFT; |
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358 | if (ver != 2 && ver != 31) |
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359 | return NULL; |
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360 | |||
361 | mnl = drm_eld_mnl(eld); |
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362 | if (mnl > 16) |
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363 | return NULL; |
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364 | |||
365 | return eld + DRM_ELD_CEA_SAD(mnl, 0); |
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366 | } |
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367 | |||
368 | /** |
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5270 | serge | 369 | * drm_eld_sad_count - Get ELD SAD count. |
370 | * @eld: pointer to an eld memory structure with sad_count set |
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371 | */ |
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372 | static inline int drm_eld_sad_count(const uint8_t *eld) |
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373 | { |
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374 | return (eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_SAD_COUNT_MASK) >> |
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375 | DRM_ELD_SAD_COUNT_SHIFT; |
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376 | } |
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377 | |||
378 | /** |
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379 | * drm_eld_calc_baseline_block_size - Calculate baseline block size in bytes |
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380 | * @eld: pointer to an eld memory structure with mnl and sad_count set |
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381 | * |
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382 | * This is a helper for determining the payload size of the baseline block, in |
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383 | * bytes, for e.g. setting the Baseline_ELD_Len field in the ELD header block. |
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384 | */ |
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385 | static inline int drm_eld_calc_baseline_block_size(const uint8_t *eld) |
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386 | { |
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387 | return DRM_ELD_MONITOR_NAME_STRING - DRM_ELD_HEADER_BLOCK_SIZE + |
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388 | drm_eld_mnl(eld) + drm_eld_sad_count(eld) * 3; |
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389 | } |
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390 | |||
391 | /** |
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392 | * drm_eld_size - Get ELD size in bytes |
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393 | * @eld: pointer to a complete eld memory structure |
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394 | * |
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395 | * The returned value does not include the vendor block. It's vendor specific, |
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396 | * and comprises of the remaining bytes in the ELD memory buffer after |
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397 | * drm_eld_size() bytes of header and baseline block. |
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398 | * |
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399 | * The returned value is guaranteed to be a multiple of 4. |
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400 | */ |
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401 | static inline int drm_eld_size(const uint8_t *eld) |
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402 | { |
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403 | return DRM_ELD_HEADER_BLOCK_SIZE + eld[DRM_ELD_BASELINE_ELD_LEN] * 4; |
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404 | } |
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405 | |||
7143 | serge | 406 | /** |
407 | * drm_eld_get_conn_type - Get device type hdmi/dp connected |
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408 | * @eld: pointer to an ELD memory structure |
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409 | * |
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410 | * The caller need to use %DRM_ELD_CONN_TYPE_HDMI or %DRM_ELD_CONN_TYPE_DP to |
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411 | * identify the display type connected. |
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412 | */ |
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413 | static inline u8 drm_eld_get_conn_type(const uint8_t *eld) |
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414 | { |
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415 | return eld[DRM_ELD_SAD_COUNT_CONN_TYPE] & DRM_ELD_CONN_TYPE_MASK; |
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416 | } |
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417 | |||
5270 | serge | 418 | struct edid *drm_do_get_edid(struct drm_connector *connector, |
419 | int (*get_edid_block)(void *data, u8 *buf, unsigned int block, |
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420 | size_t len), |
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421 | void *data); |
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422 | |||
2967 | Serge | 423 | #endif /* __DRM_EDID_H__ */><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |