WebSVN – Kolibri OS – Blame – /drivers/include/drm/drm.h

Rev	Author	Line No.	Line
1408	serge	1	/**
		2	* \file drm.h
		3	* Header for the Direct Rendering Manager
		4	*
		5	* \author Rickard E. (Rik) Faith
		6	*
		7	* \par Acknowledgments:
		8	* Dec 1999, Richard Henderson , move to generic \c cmpxchg.
		9	*/
		10
		11	/*
		12	* Copyright 1999 Precision Insight, Inc., Cedar Park, Texas.
		13	* Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
		14	* All rights reserved.
		15	*
		16	* Permission is hereby granted, free of charge, to any person obtaining a
		17	* copy of this software and associated documentation files (the "Software"),
		18	* to deal in the Software without restriction, including without limitation
		19	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
		20	* and/or sell copies of the Software, and to permit persons to whom the
		21	* Software is furnished to do so, subject to the following conditions:
		22	*
		23	* The above copyright notice and this permission notice (including the next
		24	* paragraph) shall be included in all copies or substantial portions of the
		25	* Software.
		26	*
		27	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
		28	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
		29	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
		30	* VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
		31	* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
		32	* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
		33	* OTHER DEALINGS IN THE SOFTWARE.
		34	*/
		35
		36	#ifndef _DRM_H_
		37	#define _DRM_H_
		38
		39	#include
		40	#include
		41	typedef unsigned int drm_handle_t;
		42
		43	//#include /* For _IO* macros */
		44
		45	#define DRM_MAJOR 226
		46	#define DRM_MAX_MINOR 15
		47
		48	#define DRM_NAME "drm" /*< Name in kernel, /dev, and /proc /
		49	#define DRM_MIN_ORDER 5 /*< At least 2^5 bytes = 32 bytes /
		50	#define DRM_MAX_ORDER 22 /*< Up to 2^22 bytes = 4MB /
		51	#define DRM_RAM_PERCENT 10 /*< How much system ram can we lock? /
		52
		53	#define _DRM_LOCK_HELD 0x80000000U /*< Hardware lock is held /
		54	#define _DRM_LOCK_CONT 0x40000000U /*< Hardware lock is contended /
		55	#define _DRM_LOCK_IS_HELD(lock) ((lock) & _DRM_LOCK_HELD)
		56	#define _DRM_LOCK_IS_CONT(lock) ((lock) & _DRM_LOCK_CONT)
		57	#define _DRM_LOCKING_CONTEXT(lock) ((lock) & ~(_DRM_LOCK_HELD\|_DRM_LOCK_CONT))
		58
		59	typedef unsigned int drm_context_t;
		60	typedef unsigned int drm_drawable_t;
		61	typedef unsigned int drm_magic_t;
		62
		63	/**
		64	* Cliprect.
		65	*
		66	* \warning: If you change this structure, make sure you change
		67	* XF86DRIClipRectRec in the server as well
		68	*
		69	* \note KW: Actually it's illegal to change either for
		70	* backwards-compatibility reasons.
		71	*/
		72	struct drm_clip_rect {
		73	unsigned short x1;
		74	unsigned short y1;
		75	unsigned short x2;
		76	unsigned short y2;
		77	};
		78
		79	/**
		80	* Drawable information.
		81	*/
		82	struct drm_drawable_info {
		83	unsigned int num_rects;
		84	struct drm_clip_rect *rects;
		85	};
		86
		87	/**
		88	* Texture region,
		89	*/
		90	struct drm_tex_region {
		91	unsigned char next;
		92	unsigned char prev;
		93	unsigned char in_use;
		94	unsigned char padding;
		95	unsigned int age;
		96	};
		97
		98	/**
		99	* Hardware lock.
		100	*
		101	* The lock structure is a simple cache-line aligned integer. To avoid
		102	* processor bus contention on a multiprocessor system, there should not be any
		103	* other data stored in the same cache line.
		104	*/
		105	struct drm_hw_lock {
		106	__volatile__ unsigned int lock; /*< lock variable /
		107	char padding[60]; /*< Pad to cache line /
		108	};
		109
		110	/**
		111	* DRM_IOCTL_VERSION ioctl argument type.
		112	*
		113	* \sa drmGetVersion().
		114	*/
		115	struct drm_version {
		116	int version_major; /*< Major version /
		117	int version_minor; /*< Minor version /
		118	int version_patchlevel; /*< Patch level /
		119	size_t name_len; /*< Length of name buffer /
		120	char __user name; /< Name of driver /
		121	size_t date_len; /*< Length of date buffer /
		122	char __user date; /< User-space buffer to hold date /
		123	size_t desc_len; /*< Length of desc buffer /
		124	char __user desc; /< User-space buffer to hold desc /
		125	};
		126
		127	/**
		128	* DRM_IOCTL_GET_UNIQUE ioctl argument type.
		129	*
		130	* \sa drmGetBusid() and drmSetBusId().
		131	*/
		132	struct drm_unique {
		133	size_t unique_len; /*< Length of unique /
		134	char __user unique; /< Unique name for driver instantiation /
		135	};
		136
		137	struct drm_list {
		138	int count; /*< Length of user-space structures /
		139	struct drm_version __user *version;
		140	};
		141
		142	struct drm_block {
		143	int unused;
		144	};
		145
		146	/**
		147	* DRM_IOCTL_CONTROL ioctl argument type.
		148	*
		149	* \sa drmCtlInstHandler() and drmCtlUninstHandler().
		150	*/
		151	struct drm_control {
		152	enum {
		153	DRM_ADD_COMMAND,
		154	DRM_RM_COMMAND,
		155	DRM_INST_HANDLER,
		156	DRM_UNINST_HANDLER
		157	} func;
		158	int irq;
		159	};
		160
		161	/**
		162	* Type of memory to map.
		163	*/
		164	enum drm_map_type {
		165	_DRM_FRAME_BUFFER = 0, /*< WC (no caching), no core dump /
		166	_DRM_REGISTERS = 1, /*< no caching, no core dump /
		167	_DRM_SHM = 2, /*< shared, cached /
		168	_DRM_AGP = 3, /*< AGP/GART /
		169	_DRM_SCATTER_GATHER = 4, /*< Scatter/gather memory for PCI DMA /
		170	_DRM_CONSISTENT = 5, /*< Consistent memory for PCI DMA /
		171	};
		172
		173	/**
		174	* Memory mapping flags.
		175	*/
		176	enum drm_map_flags {
		177	_DRM_RESTRICTED = 0x01, /*< Cannot be mapped to user-virtual /
		178	_DRM_READ_ONLY = 0x02,
		179	_DRM_LOCKED = 0x04, /*< shared, cached, locked /
		180	_DRM_KERNEL = 0x08, /*< kernel requires access /
		181	_DRM_WRITE_COMBINING = 0x10, /*< use write-combining if available /
		182	_DRM_CONTAINS_LOCK = 0x20, /*< SHM page that contains lock /
		183	_DRM_REMOVABLE = 0x40, /*< Removable mapping /
		184	_DRM_DRIVER = 0x80 /*< Managed by driver /
		185	};
		186
		187	struct drm_ctx_priv_map {
		188	unsigned int ctx_id; /*< Context requesting private mapping /
		189	void handle; /< Handle of map /
		190	};
		191
		192	/**
		193	* DRM_IOCTL_GET_MAP, DRM_IOCTL_ADD_MAP and DRM_IOCTL_RM_MAP ioctls
		194	* argument type.
		195	*
		196	* \sa drmAddMap().
		197	*/
		198	struct drm_map {
		199	unsigned long offset; /*< Requested physical address (0 for SAREA)/
		200	unsigned long size; /*< Requested physical size (bytes) /
		201	enum drm_map_type type; /*< Type of memory to map /
		202	enum drm_map_flags flags; /*< Flags /
		203	void handle; /< User-space: "Handle" to pass to mmap() /
		204	/*< Kernel-space: kernel-virtual address /
		205	int mtrr; /*< MTRR slot used /
		206	/* Private data */
		207	};
		208
		209	/**
		210	* DRM_IOCTL_GET_CLIENT ioctl argument type.
		211	*/
		212	struct drm_client {
		213	int idx; /*< Which client desired? /
		214	int auth; /*< Is client authenticated? /
		215	unsigned long pid; /*< Process ID /
		216	unsigned long uid; /*< User ID /
		217	unsigned long magic; /*< Magic /
		218	unsigned long iocs; /*< Ioctl count /
		219	};
		220
		221	enum drm_stat_type {
		222	_DRM_STAT_LOCK,
		223	_DRM_STAT_OPENS,
		224	_DRM_STAT_CLOSES,
		225	_DRM_STAT_IOCTLS,
		226	_DRM_STAT_LOCKS,
		227	_DRM_STAT_UNLOCKS,
		228	_DRM_STAT_VALUE, /*< Generic value /
		229	_DRM_STAT_BYTE, /*< Generic byte counter (1024bytes/K) /
		230	_DRM_STAT_COUNT, /*< Generic non-byte counter (1000/k) /
		231
		232	_DRM_STAT_IRQ, /*< IRQ /
		233	_DRM_STAT_PRIMARY, /*< Primary DMA bytes /
		234	_DRM_STAT_SECONDARY, /*< Secondary DMA bytes /
		235	_DRM_STAT_DMA, /*< DMA /
		236	_DRM_STAT_SPECIAL, /*< Special DMA (e.g., priority or polled) /
		237	_DRM_STAT_MISSED /*< Missed DMA opportunity /
		238	/* Add to the END of the list */
		239	};
		240
		241	/**
		242	* DRM_IOCTL_GET_STATS ioctl argument type.
		243	*/
		244	struct drm_stats {
		245	unsigned long count;
		246	struct {
		247	unsigned long value;
		248	enum drm_stat_type type;
		249	} data[15];
		250	};
		251
		252	/**
		253	* Hardware locking flags.
		254	*/
		255	enum drm_lock_flags {
		256	_DRM_LOCK_READY = 0x01, /*< Wait until hardware is ready for DMA /
		257	_DRM_LOCK_QUIESCENT = 0x02, /*< Wait until hardware quiescent /
		258	_DRM_LOCK_FLUSH = 0x04, /*< Flush this context's DMA queue first /
		259	_DRM_LOCK_FLUSH_ALL = 0x08, /*< Flush all DMA queues first /
		260	/* These HALT flags aren't supported yet
		261	-- they will be used to support the
		262	full-screen DGA-like mode. */
		263	_DRM_HALT_ALL_QUEUES = 0x10, /*< Halt all current and future queues /
		264	_DRM_HALT_CUR_QUEUES = 0x20 /*< Halt all current queues /
		265	};
		266
		267	/**
		268	* DRM_IOCTL_LOCK, DRM_IOCTL_UNLOCK and DRM_IOCTL_FINISH ioctl argument type.
		269	*
		270	* \sa drmGetLock() and drmUnlock().
		271	*/
		272	struct drm_lock {
		273	int context;
		274	enum drm_lock_flags flags;
		275	};
		276
		277	/**
		278	* DMA flags
		279	*
		280	* \warning
		281	* These values \e must match xf86drm.h.
		282	*
		283	* \sa drm_dma.
		284	*/
		285	enum drm_dma_flags {
		286	/* Flags for DMA buffer dispatch */
		287	_DRM_DMA_BLOCK = 0x01, /**<
		288	* Block until buffer dispatched.
		289	*
		290	* \note The buffer may not yet have
		291	* been processed by the hardware --
		292	* getting a hardware lock with the
		293	* hardware quiescent will ensure
		294	* that the buffer has been
		295	* processed.
		296	*/
		297	_DRM_DMA_WHILE_LOCKED = 0x02, /*< Dispatch while lock held /
		298	_DRM_DMA_PRIORITY = 0x04, /*< High priority dispatch /
		299
		300	/* Flags for DMA buffer request */
		301	_DRM_DMA_WAIT = 0x10, /*< Wait for free buffers /
		302	_DRM_DMA_SMALLER_OK = 0x20, /*< Smaller-than-requested buffers OK /
		303	_DRM_DMA_LARGER_OK = 0x40 /*< Larger-than-requested buffers OK /
		304	};
		305
		306	/**
		307	* DRM_IOCTL_ADD_BUFS and DRM_IOCTL_MARK_BUFS ioctl argument type.
		308	*
		309	* \sa drmAddBufs().
		310	*/
		311	struct drm_buf_desc {
		312	int count; /*< Number of buffers of this size /
		313	int size; /*< Size in bytes /
		314	int low_mark; /*< Low water mark /
		315	int high_mark; /*< High water mark /
		316	enum {
		317	_DRM_PAGE_ALIGN = 0x01, /*< Align on page boundaries for DMA /
		318	_DRM_AGP_BUFFER = 0x02, /*< Buffer is in AGP space /
		319	_DRM_SG_BUFFER = 0x04, /*< Scatter/gather memory buffer /
		320	_DRM_FB_BUFFER = 0x08, /*< Buffer is in frame buffer /
		321	_DRM_PCI_BUFFER_RO = 0x10 /*< Map PCI DMA buffer read-only /
		322	} flags;
		323	unsigned long agp_start; /**<
		324	* Start address of where the AGP buffers are
		325	* in the AGP aperture
		326	*/
		327	};
		328
		329	/**
		330	* DRM_IOCTL_INFO_BUFS ioctl argument type.
		331	*/
		332	struct drm_buf_info {
		333	int count; /*< Entries in list /
		334	struct drm_buf_desc __user *list;
		335	};
		336
		337	/**
		338	* DRM_IOCTL_FREE_BUFS ioctl argument type.
		339	*/
		340	struct drm_buf_free {
		341	int count;
		342	int __user *list;
		343	};
		344
		345	/**
		346	* Buffer information
		347	*
		348	* \sa drm_buf_map.
		349	*/
		350	struct drm_buf_pub {
		351	int idx; /*< Index into the master buffer list /
		352	int total; /*< Buffer size /
		353	int used; /*< Amount of buffer in use (for DMA) /
		354	void __user address; /< Address of buffer /
		355	};
		356
		357	/**
		358	* DRM_IOCTL_MAP_BUFS ioctl argument type.
		359	*/
		360	struct drm_buf_map {
		361	int count; /*< Length of the buffer list /
		362	void __user virtual; /< Mmap'd area in user-virtual /
		363	struct drm_buf_pub __user list; /< Buffer information /
		364	};
		365
		366	/**
		367	* DRM_IOCTL_DMA ioctl argument type.
		368	*
		369	* Indices here refer to the offset into the buffer list in drm_buf_get.
		370	*
		371	* \sa drmDMA().
		372	*/
		373	struct drm_dma {
		374	int context; /*< Context handle /
		375	int send_count; /*< Number of buffers to send /
		376	int __user send_indices; /< List of handles to buffers /
		377	int __user send_sizes; /< Lengths of data to send /
		378	enum drm_dma_flags flags; /*< Flags /
		379	int request_count; /*< Number of buffers requested /
		380	int request_size; /*< Desired size for buffers /
		381	int __user request_indices; /< Buffer information /
		382	int __user *request_sizes;
		383	int granted_count; /*< Number of buffers granted /
		384	};
		385
		386	enum drm_ctx_flags {
		387	_DRM_CONTEXT_PRESERVED = 0x01,
		388	_DRM_CONTEXT_2DONLY = 0x02
		389	};
		390
		391	/**
		392	* DRM_IOCTL_ADD_CTX ioctl argument type.
		393	*
		394	* \sa drmCreateContext() and drmDestroyContext().
		395	*/
		396	struct drm_ctx {
		397	drm_context_t handle;
		398	enum drm_ctx_flags flags;
		399	};
		400
		401	/**
		402	* DRM_IOCTL_RES_CTX ioctl argument type.
		403	*/
		404	struct drm_ctx_res {
		405	int count;
		406	struct drm_ctx __user *contexts;
		407	};
		408
		409	/**
		410	* DRM_IOCTL_ADD_DRAW and DRM_IOCTL_RM_DRAW ioctl argument type.
		411	*/
		412	struct drm_draw {
		413	drm_drawable_t handle;
		414	};
		415
		416	/**
		417	* DRM_IOCTL_UPDATE_DRAW ioctl argument type.
		418	*/
		419	typedef enum {
		420	DRM_DRAWABLE_CLIPRECTS,
		421	} drm_drawable_info_type_t;
		422
		423	struct drm_update_draw {
		424	drm_drawable_t handle;
		425	unsigned int type;
		426	unsigned int num;
		427	unsigned long long data;
		428	};
		429
		430	/**
		431	* DRM_IOCTL_GET_MAGIC and DRM_IOCTL_AUTH_MAGIC ioctl argument type.
		432	*/
		433	struct drm_auth {
		434	drm_magic_t magic;
		435	};
		436
		437	/**
		438	* DRM_IOCTL_IRQ_BUSID ioctl argument type.
		439	*
		440	* \sa drmGetInterruptFromBusID().
		441	*/
		442	struct drm_irq_busid {
		443	int irq; /*< IRQ number /
		444	int busnum; /*< bus number /
		445	int devnum; /*< device number /
		446	int funcnum; /*< function number /
		447	};
		448
		449	enum drm_vblank_seq_type {
		450	_DRM_VBLANK_ABSOLUTE = 0x0, /*< Wait for specific vblank sequence number /
		451	_DRM_VBLANK_RELATIVE = 0x1, /*< Wait for given number of vblanks /
1964	serge	452	/* bits 1-6 are reserved for high crtcs */
		453	_DRM_VBLANK_HIGH_CRTC_MASK = 0x0000003e,
1408	serge	454	_DRM_VBLANK_EVENT = 0x4000000, /*< Send event instead of blocking /
		455	_DRM_VBLANK_FLIP = 0x8000000, /*< Scheduled buffer swap should flip /
		456	_DRM_VBLANK_NEXTONMISS = 0x10000000, /*< If missed, wait for next vblank /
		457	_DRM_VBLANK_SECONDARY = 0x20000000, /*< Secondary display controller /
		458	_DRM_VBLANK_SIGNAL = 0x40000000 /*< Send signal instead of blocking, unsupported /
		459	};
1964	serge	460	#define _DRM_VBLANK_HIGH_CRTC_SHIFT 1
1408	serge	461
		462	#define _DRM_VBLANK_TYPES_MASK (_DRM_VBLANK_ABSOLUTE \| _DRM_VBLANK_RELATIVE)
		463	#define _DRM_VBLANK_FLAGS_MASK (_DRM_VBLANK_EVENT \| _DRM_VBLANK_SIGNAL \| \
		464	_DRM_VBLANK_SECONDARY \| _DRM_VBLANK_NEXTONMISS)
		465
		466	struct drm_wait_vblank_request {
		467	enum drm_vblank_seq_type type;
		468	unsigned int sequence;
		469	unsigned long signal;
		470	};
		471
		472	struct drm_wait_vblank_reply {
		473	enum drm_vblank_seq_type type;
		474	unsigned int sequence;
		475	long tval_sec;
		476	long tval_usec;
		477	};
		478
		479	/**
		480	* DRM_IOCTL_WAIT_VBLANK ioctl argument type.
		481	*
		482	* \sa drmWaitVBlank().
		483	*/
		484	union drm_wait_vblank {
		485	struct drm_wait_vblank_request request;
		486	struct drm_wait_vblank_reply reply;
		487	};
		488
		489	#define _DRM_PRE_MODESET 1
		490	#define _DRM_POST_MODESET 2
		491
		492	/**
		493	* DRM_IOCTL_MODESET_CTL ioctl argument type
		494	*
		495	* \sa drmModesetCtl().
		496	*/
		497	struct drm_modeset_ctl {
		498	__u32 crtc;
		499	__u32 cmd;
		500	};
		501
		502	/**
		503	* DRM_IOCTL_AGP_ENABLE ioctl argument type.
		504	*
		505	* \sa drmAgpEnable().
		506	*/
		507	struct drm_agp_mode {
		508	unsigned long mode; /*< AGP mode /
		509	};
		510
		511	/**
		512	* DRM_IOCTL_AGP_ALLOC and DRM_IOCTL_AGP_FREE ioctls argument type.
		513	*
		514	* \sa drmAgpAlloc() and drmAgpFree().
		515	*/
		516	struct drm_agp_buffer {
		517	unsigned long size; /*< In bytes -- will round to page boundary /
		518	unsigned long handle; /*< Used for binding / unbinding /
		519	unsigned long type; /*< Type of memory to allocate /
		520	unsigned long physical; /*< Physical used by i810 /
		521	};
		522
		523	/**
		524	* DRM_IOCTL_AGP_BIND and DRM_IOCTL_AGP_UNBIND ioctls argument type.
		525	*
		526	* \sa drmAgpBind() and drmAgpUnbind().
		527	*/
		528	struct drm_agp_binding {
		529	unsigned long handle; /*< From drm_agp_buffer /
		530	unsigned long offset; /*< In bytes -- will round to page boundary /
		531	};
		532
		533	/**
		534	* DRM_IOCTL_AGP_INFO ioctl argument type.
		535	*
		536	* \sa drmAgpVersionMajor(), drmAgpVersionMinor(), drmAgpGetMode(),
		537	* drmAgpBase(), drmAgpSize(), drmAgpMemoryUsed(), drmAgpMemoryAvail(),
		538	* drmAgpVendorId() and drmAgpDeviceId().
		539	*/
		540	struct drm_agp_info {
		541	int agp_version_major;
		542	int agp_version_minor;
		543	unsigned long mode;
		544	unsigned long aperture_base; /* physical address */
		545	unsigned long aperture_size; /* bytes */
		546	unsigned long memory_allowed; /* bytes */
		547	unsigned long memory_used;
		548
		549	/* PCI information */
		550	unsigned short id_vendor;
		551	unsigned short id_device;
		552	};
		553
		554	/**
		555	* DRM_IOCTL_SG_ALLOC ioctl argument type.
		556	*/
		557	struct drm_scatter_gather {
		558	unsigned long size; /*< In bytes -- will round to page boundary /
		559	unsigned long handle; /*< Used for mapping / unmapping /
		560	};
		561
		562	/**
		563	* DRM_IOCTL_SET_VERSION ioctl argument type.
		564	*/
		565	struct drm_set_version {
		566	int drm_di_major;
		567	int drm_di_minor;
		568	int drm_dd_major;
		569	int drm_dd_minor;
		570	};
		571
		572	/** DRM_IOCTL_GEM_CLOSE ioctl argument type */
		573	struct drm_gem_close {
		574	/** Handle of the object to be closed. */
		575	__u32 handle;
		576	__u32 pad;
		577	};
		578
		579	/** DRM_IOCTL_GEM_FLINK ioctl argument type */
		580	struct drm_gem_flink {
		581	/** Handle for the object being named */
		582	__u32 handle;
		583
		584	/** Returned global name */
		585	__u32 name;
		586	};
		587
		588	/** DRM_IOCTL_GEM_OPEN ioctl argument type */
		589	struct drm_gem_open {
		590	/** Name of object being opened */
		591	__u32 name;
		592
		593	/** Returned handle for the object */
		594	__u32 handle;
		595
		596	/** Returned size of the object */
		597	__u64 size;
		598	};
		599
4559	Serge	600	#define DRM_CAP_DUMB_BUFFER 0x1
		601	#define DRM_CAP_VBLANK_HIGH_CRTC 0x2
		602	#define DRM_CAP_DUMB_PREFERRED_DEPTH 0x3
		603	#define DRM_CAP_DUMB_PREFER_SHADOW 0x4
		604	#define DRM_CAP_PRIME 0x5
		605	#define DRM_PRIME_CAP_IMPORT 0x1
		606	#define DRM_PRIME_CAP_EXPORT 0x2
		607	#define DRM_CAP_TIMESTAMP_MONOTONIC 0x6
		608	#define DRM_CAP_ASYNC_PAGE_FLIP 0x7
		609
1964	serge	610	/** DRM_IOCTL_GET_CAP ioctl argument type */
		611	struct drm_get_cap {
		612	__u64 capability;
		613	__u64 value;
		614	};
		615
4559	Serge	616	/**
		617	* DRM_CLIENT_CAP_STEREO_3D
		618	*
		619	* if set to 1, the DRM core will expose the stereo 3D capabilities of the
		620	* monitor by advertising the supported 3D layouts in the flags of struct
		621	* drm_mode_modeinfo.
		622	*/
		623	#define DRM_CLIENT_CAP_STEREO_3D 1
1408	serge	624
4559	Serge	625	/** DRM_IOCTL_SET_CLIENT_CAP ioctl argument type */
		626	struct drm_set_client_cap {
		627	__u64 capability;
		628	__u64 value;
		629	};
		630
		631	#define DRM_CLOEXEC O_CLOEXEC
		632	struct drm_prime_handle {
		633	__u32 handle;
		634
		635	/** Flags.. only applicable for handle->fd */
		636	__u32 flags;
		637
		638	/** Returned dmabuf file descriptor */
		639	__s32 fd;
		640	};
		641
		642	#include
		643
		644	#if 0
1408	serge	645	#define DRM_IOCTL_BASE 'd'
		646	#define DRM_IO(nr) _IO(DRM_IOCTL_BASE,nr)
		647	#define DRM_IOR(nr,type) _IOR(DRM_IOCTL_BASE,nr,type)
		648	#define DRM_IOW(nr,type) _IOW(DRM_IOCTL_BASE,nr,type)
		649	#define DRM_IOWR(nr,type) _IOWR(DRM_IOCTL_BASE,nr,type)
		650
		651	#define DRM_IOCTL_VERSION DRM_IOWR(0x00, struct drm_version)
		652	#define DRM_IOCTL_GET_UNIQUE DRM_IOWR(0x01, struct drm_unique)
		653	#define DRM_IOCTL_GET_MAGIC DRM_IOR( 0x02, struct drm_auth)
		654	#define DRM_IOCTL_IRQ_BUSID DRM_IOWR(0x03, struct drm_irq_busid)
		655	#define DRM_IOCTL_GET_MAP DRM_IOWR(0x04, struct drm_map)
		656	#define DRM_IOCTL_GET_CLIENT DRM_IOWR(0x05, struct drm_client)
		657	#define DRM_IOCTL_GET_STATS DRM_IOR( 0x06, struct drm_stats)
		658	#define DRM_IOCTL_SET_VERSION DRM_IOWR(0x07, struct drm_set_version)
		659	#define DRM_IOCTL_MODESET_CTL DRM_IOW(0x08, struct drm_modeset_ctl)
		660	#define DRM_IOCTL_GEM_CLOSE DRM_IOW (0x09, struct drm_gem_close)
		661	#define DRM_IOCTL_GEM_FLINK DRM_IOWR(0x0a, struct drm_gem_flink)
		662	#define DRM_IOCTL_GEM_OPEN DRM_IOWR(0x0b, struct drm_gem_open)
1964	serge	663	#define DRM_IOCTL_GET_CAP DRM_IOWR(0x0c, struct drm_get_cap)
4559	Serge	664	#define DRM_IOCTL_SET_CLIENT_CAP DRM_IOW( 0x0d, struct drm_set_client_cap)
1408	serge	665
		666	#define DRM_IOCTL_SET_UNIQUE DRM_IOW( 0x10, struct drm_unique)
		667	#define DRM_IOCTL_AUTH_MAGIC DRM_IOW( 0x11, struct drm_auth)
		668	#define DRM_IOCTL_BLOCK DRM_IOWR(0x12, struct drm_block)
		669	#define DRM_IOCTL_UNBLOCK DRM_IOWR(0x13, struct drm_block)
		670	#define DRM_IOCTL_CONTROL DRM_IOW( 0x14, struct drm_control)
		671	#define DRM_IOCTL_ADD_MAP DRM_IOWR(0x15, struct drm_map)
		672	#define DRM_IOCTL_ADD_BUFS DRM_IOWR(0x16, struct drm_buf_desc)
		673	#define DRM_IOCTL_MARK_BUFS DRM_IOW( 0x17, struct drm_buf_desc)
		674	#define DRM_IOCTL_INFO_BUFS DRM_IOWR(0x18, struct drm_buf_info)
		675	#define DRM_IOCTL_MAP_BUFS DRM_IOWR(0x19, struct drm_buf_map)
		676	#define DRM_IOCTL_FREE_BUFS DRM_IOW( 0x1a, struct drm_buf_free)
		677
		678	#define DRM_IOCTL_RM_MAP DRM_IOW( 0x1b, struct drm_map)
		679
		680	#define DRM_IOCTL_SET_SAREA_CTX DRM_IOW( 0x1c, struct drm_ctx_priv_map)
		681	#define DRM_IOCTL_GET_SAREA_CTX DRM_IOWR(0x1d, struct drm_ctx_priv_map)
		682
		683	#define DRM_IOCTL_SET_MASTER DRM_IO(0x1e)
		684	#define DRM_IOCTL_DROP_MASTER DRM_IO(0x1f)
		685
		686	#define DRM_IOCTL_ADD_CTX DRM_IOWR(0x20, struct drm_ctx)
		687	#define DRM_IOCTL_RM_CTX DRM_IOWR(0x21, struct drm_ctx)
		688	#define DRM_IOCTL_MOD_CTX DRM_IOW( 0x22, struct drm_ctx)
		689	#define DRM_IOCTL_GET_CTX DRM_IOWR(0x23, struct drm_ctx)
		690	#define DRM_IOCTL_SWITCH_CTX DRM_IOW( 0x24, struct drm_ctx)
		691	#define DRM_IOCTL_NEW_CTX DRM_IOW( 0x25, struct drm_ctx)
		692	#define DRM_IOCTL_RES_CTX DRM_IOWR(0x26, struct drm_ctx_res)
		693	#define DRM_IOCTL_ADD_DRAW DRM_IOWR(0x27, struct drm_draw)
		694	#define DRM_IOCTL_RM_DRAW DRM_IOWR(0x28, struct drm_draw)
		695	#define DRM_IOCTL_DMA DRM_IOWR(0x29, struct drm_dma)
		696	#define DRM_IOCTL_LOCK DRM_IOW( 0x2a, struct drm_lock)
		697	#define DRM_IOCTL_UNLOCK DRM_IOW( 0x2b, struct drm_lock)
		698	#define DRM_IOCTL_FINISH DRM_IOW( 0x2c, struct drm_lock)
		699
4559	Serge	700	#define DRM_IOCTL_PRIME_HANDLE_TO_FD DRM_IOWR(0x2d, struct drm_prime_handle)
		701	#define DRM_IOCTL_PRIME_FD_TO_HANDLE DRM_IOWR(0x2e, struct drm_prime_handle)
1964	serge	702
1408	serge	703	#define DRM_IOCTL_AGP_ACQUIRE DRM_IO( 0x30)
		704	#define DRM_IOCTL_AGP_RELEASE DRM_IO( 0x31)
		705	#define DRM_IOCTL_AGP_ENABLE DRM_IOW( 0x32, struct drm_agp_mode)
		706	#define DRM_IOCTL_AGP_INFO DRM_IOR( 0x33, struct drm_agp_info)
		707	#define DRM_IOCTL_AGP_ALLOC DRM_IOWR(0x34, struct drm_agp_buffer)
		708	#define DRM_IOCTL_AGP_FREE DRM_IOW( 0x35, struct drm_agp_buffer)
		709	#define DRM_IOCTL_AGP_BIND DRM_IOW( 0x36, struct drm_agp_binding)
		710	#define DRM_IOCTL_AGP_UNBIND DRM_IOW( 0x37, struct drm_agp_binding)
		711
		712	#define DRM_IOCTL_SG_ALLOC DRM_IOWR(0x38, struct drm_scatter_gather)
		713	#define DRM_IOCTL_SG_FREE DRM_IOW( 0x39, struct drm_scatter_gather)
		714
		715	#define DRM_IOCTL_WAIT_VBLANK DRM_IOWR(0x3a, union drm_wait_vblank)
		716
		717	#define DRM_IOCTL_UPDATE_DRAW DRM_IOW(0x3f, struct drm_update_draw)
		718
		719	#define DRM_IOCTL_MODE_GETRESOURCES DRM_IOWR(0xA0, struct drm_mode_card_res)
		720	#define DRM_IOCTL_MODE_GETCRTC DRM_IOWR(0xA1, struct drm_mode_crtc)
		721	#define DRM_IOCTL_MODE_SETCRTC DRM_IOWR(0xA2, struct drm_mode_crtc)
		722	#define DRM_IOCTL_MODE_CURSOR DRM_IOWR(0xA3, struct drm_mode_cursor)
		723	#define DRM_IOCTL_MODE_GETGAMMA DRM_IOWR(0xA4, struct drm_mode_crtc_lut)
		724	#define DRM_IOCTL_MODE_SETGAMMA DRM_IOWR(0xA5, struct drm_mode_crtc_lut)
		725	#define DRM_IOCTL_MODE_GETENCODER DRM_IOWR(0xA6, struct drm_mode_get_encoder)
		726	#define DRM_IOCTL_MODE_GETCONNECTOR DRM_IOWR(0xA7, struct drm_mode_get_connector)
4559	Serge	727	#define DRM_IOCTL_MODE_ATTACHMODE DRM_IOWR(0xA8, struct drm_mode_mode_cmd) /* deprecated (never worked) */
		728	#define DRM_IOCTL_MODE_DETACHMODE DRM_IOWR(0xA9, struct drm_mode_mode_cmd) /* deprecated (never worked) */
1408	serge	729
		730	#define DRM_IOCTL_MODE_GETPROPERTY DRM_IOWR(0xAA, struct drm_mode_get_property)
		731	#define DRM_IOCTL_MODE_SETPROPERTY DRM_IOWR(0xAB, struct drm_mode_connector_set_property)
		732	#define DRM_IOCTL_MODE_GETPROPBLOB DRM_IOWR(0xAC, struct drm_mode_get_blob)
		733	#define DRM_IOCTL_MODE_GETFB DRM_IOWR(0xAD, struct drm_mode_fb_cmd)
		734	#define DRM_IOCTL_MODE_ADDFB DRM_IOWR(0xAE, struct drm_mode_fb_cmd)
		735	#define DRM_IOCTL_MODE_RMFB DRM_IOWR(0xAF, unsigned int)
		736	#define DRM_IOCTL_MODE_PAGE_FLIP DRM_IOWR(0xB0, struct drm_mode_crtc_page_flip)
1964	serge	737	#define DRM_IOCTL_MODE_DIRTYFB DRM_IOWR(0xB1, struct drm_mode_fb_dirty_cmd)
2003	serge	738
		739	#define DRM_IOCTL_MODE_CREATE_DUMB DRM_IOWR(0xB2, struct drm_mode_create_dumb)
		740	#define DRM_IOCTL_MODE_MAP_DUMB DRM_IOWR(0xB3, struct drm_mode_map_dumb)
		741	#define DRM_IOCTL_MODE_DESTROY_DUMB DRM_IOWR(0xB4, struct drm_mode_destroy_dumb)
2967	Serge	742	#define DRM_IOCTL_MODE_GETPLANERESOURCES DRM_IOWR(0xB5, struct drm_mode_get_plane_res)
		743	#define DRM_IOCTL_MODE_GETPLANE DRM_IOWR(0xB6, struct drm_mode_get_plane)
		744	#define DRM_IOCTL_MODE_SETPLANE DRM_IOWR(0xB7, struct drm_mode_set_plane)
4559	Serge	745	#define DRM_IOCTL_MODE_ADDFB2 DRM_IOWR(0xB8, struct drm_mode_fb_cmd2)
		746	#define DRM_IOCTL_MODE_OBJ_GETPROPERTIES DRM_IOWR(0xB9, struct drm_mode_obj_get_properties)
		747	#define DRM_IOCTL_MODE_OBJ_SETPROPERTY DRM_IOWR(0xBA, struct drm_mode_obj_set_property)
		748	#define DRM_IOCTL_MODE_CURSOR2 DRM_IOWR(0xBB, struct drm_mode_cursor2)
		749	#endif
2003	serge	750
1408	serge	751	/**
		752	* Device specific ioctls should only be in their respective headers
		753	* The device specific ioctl range is from 0x40 to 0x99.
		754	* Generic IOCTLS restart at 0xA0.
		755	*
		756	* \sa drmCommandNone(), drmCommandRead(), drmCommandWrite(), and
		757	* drmCommandReadWrite().
		758	*/
		759	#define DRM_COMMAND_BASE 0x40
		760	#define DRM_COMMAND_END 0xA0
		761
		762	/**
		763	* Header for events written back to userspace on the drm fd. The
		764	* type defines the type of event, the length specifies the total
		765	* length of the event (including the header), and user_data is
		766	* typically a 64 bit value passed with the ioctl that triggered the
		767	* event. A read on the drm fd will always only return complete
		768	* events, that is, if for example the read buffer is 100 bytes, and
		769	* there are two 64 byte events pending, only one will be returned.
		770	*
		771	* Event types 0 - 0x7fffffff are generic drm events, 0x80000000 and
		772	* up are chipset specific.
		773	*/
		774	struct drm_event {
		775	__u32 type;
		776	__u32 length;
		777	};
		778
		779	#define DRM_EVENT_VBLANK 0x01
		780	#define DRM_EVENT_FLIP_COMPLETE 0x02
		781
		782	struct drm_event_vblank {
		783	struct drm_event base;
		784	__u64 user_data;
		785	__u32 tv_sec;
		786	__u32 tv_usec;
		787	__u32 sequence;
		788	__u32 reserved;
		789	};
		790
		791	/* typedef area */
		792	#ifndef __KERNEL__
		793	typedef struct drm_clip_rect drm_clip_rect_t;
		794	typedef struct drm_drawable_info drm_drawable_info_t;
		795	typedef struct drm_tex_region drm_tex_region_t;
		796	typedef struct drm_hw_lock drm_hw_lock_t;
		797	typedef struct drm_version drm_version_t;
		798	typedef struct drm_unique drm_unique_t;
		799	typedef struct drm_list drm_list_t;
		800	typedef struct drm_block drm_block_t;
		801	typedef struct drm_control drm_control_t;
		802	typedef enum drm_map_type drm_map_type_t;
		803	typedef enum drm_map_flags drm_map_flags_t;
		804	typedef struct drm_ctx_priv_map drm_ctx_priv_map_t;
		805	typedef struct drm_map drm_map_t;
		806	typedef struct drm_client drm_client_t;
		807	typedef enum drm_stat_type drm_stat_type_t;
		808	typedef struct drm_stats drm_stats_t;
		809	typedef enum drm_lock_flags drm_lock_flags_t;
		810	typedef struct drm_lock drm_lock_t;
		811	typedef enum drm_dma_flags drm_dma_flags_t;
		812	typedef struct drm_buf_desc drm_buf_desc_t;
		813	typedef struct drm_buf_info drm_buf_info_t;
		814	typedef struct drm_buf_free drm_buf_free_t;
		815	typedef struct drm_buf_pub drm_buf_pub_t;
		816	typedef struct drm_buf_map drm_buf_map_t;
		817	typedef struct drm_dma drm_dma_t;
		818	typedef union drm_wait_vblank drm_wait_vblank_t;
		819	typedef struct drm_agp_mode drm_agp_mode_t;
		820	typedef enum drm_ctx_flags drm_ctx_flags_t;
		821	typedef struct drm_ctx drm_ctx_t;
		822	typedef struct drm_ctx_res drm_ctx_res_t;
		823	typedef struct drm_draw drm_draw_t;
		824	typedef struct drm_update_draw drm_update_draw_t;
		825	typedef struct drm_auth drm_auth_t;
		826	typedef struct drm_irq_busid drm_irq_busid_t;
		827	typedef enum drm_vblank_seq_type drm_vblank_seq_type_t;
		828
		829	typedef struct drm_agp_buffer drm_agp_buffer_t;
		830	typedef struct drm_agp_binding drm_agp_binding_t;
		831	typedef struct drm_agp_info drm_agp_info_t;
		832	typedef struct drm_scatter_gather drm_scatter_gather_t;
		833	typedef struct drm_set_version drm_set_version_t;
		834	#endif
		835
		836	#endif

Subversion Repositories Kolibri OS

(root)/drivers/include/drm/drm.h – Rev 4559