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Rev | Author | Line No. | Line |
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5270 | serge | 1 | #ifndef _ASM_X86_MSR_H |
2 | #define _ASM_X86_MSR_H |
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3 | |||
6082 | serge | 4 | #include "msr-index.h" |
5270 | serge | 5 | |
6 | #ifndef __ASSEMBLY__ |
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7 | |||
8 | #include |
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9 | #include |
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10 | #include |
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6082 | serge | 11 | #include |
5270 | serge | 12 | |
13 | struct msr { |
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14 | union { |
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15 | struct { |
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16 | u32 l; |
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17 | u32 h; |
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18 | }; |
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19 | u64 q; |
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20 | }; |
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21 | }; |
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22 | |||
23 | struct msr_info { |
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24 | u32 msr_no; |
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25 | struct msr reg; |
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26 | struct msr *msrs; |
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27 | int err; |
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28 | }; |
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29 | |||
30 | struct msr_regs_info { |
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31 | u32 *regs; |
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32 | int err; |
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33 | }; |
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34 | |||
6936 | serge | 35 | struct saved_msr { |
36 | bool valid; |
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37 | struct msr_info info; |
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38 | }; |
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39 | |||
40 | struct saved_msrs { |
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41 | unsigned int num; |
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42 | struct saved_msr *array; |
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43 | }; |
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44 | |||
5270 | serge | 45 | static inline unsigned long long native_read_tscp(unsigned int *aux) |
46 | { |
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47 | unsigned long low, high; |
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48 | asm volatile(".byte 0x0f,0x01,0xf9" |
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49 | : "=a" (low), "=d" (high), "=c" (*aux)); |
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50 | return low | ((u64)high << 32); |
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51 | } |
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52 | |||
53 | /* |
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54 | * both i386 and x86_64 returns 64-bit value in edx:eax, but gcc's "A" |
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55 | * constraint has different meanings. For i386, "A" means exactly |
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56 | * edx:eax, while for x86_64 it doesn't mean rdx:rax or edx:eax. Instead, |
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57 | * it means rax *or* rdx. |
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58 | */ |
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59 | #ifdef CONFIG_X86_64 |
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6082 | serge | 60 | /* Using 64-bit values saves one instruction clearing the high half of low */ |
61 | #define DECLARE_ARGS(val, low, high) unsigned long low, high |
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62 | #define EAX_EDX_VAL(val, low, high) ((low) | (high) << 32) |
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5270 | serge | 63 | #define EAX_EDX_RET(val, low, high) "=a" (low), "=d" (high) |
64 | #else |
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65 | #define DECLARE_ARGS(val, low, high) unsigned long long val |
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66 | #define EAX_EDX_VAL(val, low, high) (val) |
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67 | #define EAX_EDX_RET(val, low, high) "=A" (val) |
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68 | #endif |
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69 | |||
70 | static inline unsigned long long native_read_msr(unsigned int msr) |
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71 | { |
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72 | DECLARE_ARGS(val, low, high); |
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73 | |||
74 | asm volatile("rdmsr" : EAX_EDX_RET(val, low, high) : "c" (msr)); |
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75 | return EAX_EDX_VAL(val, low, high); |
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76 | } |
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77 | |||
78 | static inline unsigned long long native_read_msr_safe(unsigned int msr, |
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79 | int *err) |
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80 | { |
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81 | DECLARE_ARGS(val, low, high); |
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82 | |||
83 | asm volatile("2: rdmsr ; xor %[err],%[err]\n" |
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84 | "1:\n\t" |
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85 | ".section .fixup,\"ax\"\n\t" |
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86 | "3: mov %[fault],%[err] ; jmp 1b\n\t" |
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87 | ".previous\n\t" |
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88 | _ASM_EXTABLE(2b, 3b) |
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89 | : [err] "=r" (*err), EAX_EDX_RET(val, low, high) |
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90 | : "c" (msr), [fault] "i" (-EIO)); |
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91 | return EAX_EDX_VAL(val, low, high); |
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92 | } |
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93 | |||
94 | static inline void native_write_msr(unsigned int msr, |
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95 | unsigned low, unsigned high) |
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96 | { |
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97 | asm volatile("wrmsr" : : "c" (msr), "a"(low), "d" (high) : "memory"); |
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98 | } |
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99 | |||
100 | /* Can be uninlined because referenced by paravirt */ |
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101 | notrace static inline int native_write_msr_safe(unsigned int msr, |
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102 | unsigned low, unsigned high) |
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103 | { |
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104 | int err; |
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105 | asm volatile("2: wrmsr ; xor %[err],%[err]\n" |
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106 | "1:\n\t" |
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107 | ".section .fixup,\"ax\"\n\t" |
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108 | "3: mov %[fault],%[err] ; jmp 1b\n\t" |
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109 | ".previous\n\t" |
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110 | _ASM_EXTABLE(2b, 3b) |
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111 | : [err] "=a" (err) |
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112 | : "c" (msr), "0" (low), "d" (high), |
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113 | [fault] "i" (-EIO) |
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114 | : "memory"); |
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115 | return err; |
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116 | } |
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117 | |||
118 | extern int rdmsr_safe_regs(u32 regs[8]); |
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119 | extern int wrmsr_safe_regs(u32 regs[8]); |
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120 | |||
6082 | serge | 121 | /** |
122 | * rdtsc() - returns the current TSC without ordering constraints |
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123 | * |
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124 | * rdtsc() returns the result of RDTSC as a 64-bit integer. The |
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125 | * only ordering constraint it supplies is the ordering implied by |
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126 | * "asm volatile": it will put the RDTSC in the place you expect. The |
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127 | * CPU can and will speculatively execute that RDTSC, though, so the |
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128 | * results can be non-monotonic if compared on different CPUs. |
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129 | */ |
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130 | static __always_inline unsigned long long rdtsc(void) |
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5270 | serge | 131 | { |
132 | DECLARE_ARGS(val, low, high); |
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133 | |||
134 | asm volatile("rdtsc" : EAX_EDX_RET(val, low, high)); |
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135 | |||
136 | return EAX_EDX_VAL(val, low, high); |
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137 | } |
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138 | |||
139 | static inline unsigned long long native_read_pmc(int counter) |
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140 | { |
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141 | DECLARE_ARGS(val, low, high); |
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142 | |||
143 | asm volatile("rdpmc" : EAX_EDX_RET(val, low, high) : "c" (counter)); |
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144 | return EAX_EDX_VAL(val, low, high); |
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145 | } |
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146 | |||
147 | #ifdef CONFIG_PARAVIRT |
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148 | #include |
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149 | #else |
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150 | #include |
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151 | /* |
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152 | * Access to machine-specific registers (available on 586 and better only) |
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153 | * Note: the rd* operations modify the parameters directly (without using |
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154 | * pointer indirection), this allows gcc to optimize better |
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155 | */ |
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156 | |||
157 | #define rdmsr(msr, low, high) \ |
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158 | do { \ |
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159 | u64 __val = native_read_msr((msr)); \ |
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160 | (void)((low) = (u32)__val); \ |
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161 | (void)((high) = (u32)(__val >> 32)); \ |
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162 | } while (0) |
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163 | |||
164 | static inline void wrmsr(unsigned msr, unsigned low, unsigned high) |
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165 | { |
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166 | native_write_msr(msr, low, high); |
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167 | } |
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168 | |||
169 | #define rdmsrl(msr, val) \ |
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170 | ((val) = native_read_msr((msr))) |
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171 | |||
6082 | serge | 172 | static inline void wrmsrl(unsigned msr, u64 val) |
173 | { |
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6936 | serge | 174 | native_write_msr(msr, (u32)(val & 0xffffffffULL), (u32)(val >> 32)); |
6082 | serge | 175 | } |
5270 | serge | 176 | |
177 | /* wrmsr with exception handling */ |
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178 | static inline int wrmsr_safe(unsigned msr, unsigned low, unsigned high) |
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179 | { |
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180 | return native_write_msr_safe(msr, low, high); |
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181 | } |
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182 | |||
183 | /* rdmsr with exception handling */ |
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184 | #define rdmsr_safe(msr, low, high) \ |
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185 | ({ \ |
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186 | int __err; \ |
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187 | u64 __val = native_read_msr_safe((msr), &__err); \ |
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188 | (*low) = (u32)__val; \ |
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189 | (*high) = (u32)(__val >> 32); \ |
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190 | __err; \ |
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191 | }) |
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192 | |||
193 | static inline int rdmsrl_safe(unsigned msr, unsigned long long *p) |
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194 | { |
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195 | int err; |
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196 | |||
197 | *p = native_read_msr_safe(msr, &err); |
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198 | return err; |
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199 | } |
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200 | |||
201 | #define rdpmc(counter, low, high) \ |
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202 | do { \ |
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203 | u64 _l = native_read_pmc((counter)); \ |
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204 | (low) = (u32)_l; \ |
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205 | (high) = (u32)(_l >> 32); \ |
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206 | } while (0) |
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207 | |||
208 | #define rdpmcl(counter, val) ((val) = native_read_pmc(counter)) |
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209 | |||
210 | #endif /* !CONFIG_PARAVIRT */ |
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211 | |||
6082 | serge | 212 | /* |
213 | * 64-bit version of wrmsr_safe(): |
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214 | */ |
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215 | static inline int wrmsrl_safe(u32 msr, u64 val) |
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216 | { |
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217 | return wrmsr_safe(msr, (u32)val, (u32)(val >> 32)); |
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218 | } |
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5270 | serge | 219 | |
220 | #define write_tsc(low, high) wrmsr(MSR_IA32_TSC, (low), (high)) |
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221 | |||
222 | #define write_rdtscp_aux(val) wrmsr(MSR_TSC_AUX, (val), 0) |
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223 | |||
224 | struct msr *msrs_alloc(void); |
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225 | void msrs_free(struct msr *msrs); |
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226 | int msr_set_bit(u32 msr, u8 bit); |
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227 | int msr_clear_bit(u32 msr, u8 bit); |
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228 | |||
229 | #ifdef CONFIG_SMP |
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230 | int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
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231 | int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); |
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232 | int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); |
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233 | int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q); |
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234 | void rdmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); |
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235 | void wrmsr_on_cpus(const struct cpumask *mask, u32 msr_no, struct msr *msrs); |
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236 | int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h); |
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237 | int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h); |
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238 | int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q); |
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239 | int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q); |
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240 | int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); |
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241 | int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]); |
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242 | #else /* CONFIG_SMP */ |
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243 | static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h) |
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244 | { |
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245 | rdmsr(msr_no, *l, *h); |
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246 | return 0; |
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247 | } |
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248 | static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) |
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249 | { |
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250 | wrmsr(msr_no, l, h); |
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251 | return 0; |
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252 | } |
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253 | static inline int rdmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) |
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254 | { |
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255 | rdmsrl(msr_no, *q); |
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256 | return 0; |
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257 | } |
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258 | static inline int wrmsrl_on_cpu(unsigned int cpu, u32 msr_no, u64 q) |
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259 | { |
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260 | wrmsrl(msr_no, q); |
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261 | return 0; |
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262 | } |
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263 | static inline void rdmsr_on_cpus(const struct cpumask *m, u32 msr_no, |
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264 | struct msr *msrs) |
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265 | { |
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266 | rdmsr_on_cpu(0, msr_no, &(msrs[0].l), &(msrs[0].h)); |
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267 | } |
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268 | static inline void wrmsr_on_cpus(const struct cpumask *m, u32 msr_no, |
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269 | struct msr *msrs) |
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270 | { |
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271 | wrmsr_on_cpu(0, msr_no, msrs[0].l, msrs[0].h); |
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272 | } |
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273 | static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, |
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274 | u32 *l, u32 *h) |
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275 | { |
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276 | return rdmsr_safe(msr_no, l, h); |
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277 | } |
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278 | static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h) |
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279 | { |
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280 | return wrmsr_safe(msr_no, l, h); |
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281 | } |
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282 | static inline int rdmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 *q) |
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283 | { |
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284 | return rdmsrl_safe(msr_no, q); |
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285 | } |
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286 | static inline int wrmsrl_safe_on_cpu(unsigned int cpu, u32 msr_no, u64 q) |
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287 | { |
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288 | return wrmsrl_safe(msr_no, q); |
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289 | } |
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290 | static inline int rdmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) |
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291 | { |
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292 | return rdmsr_safe_regs(regs); |
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293 | } |
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294 | static inline int wrmsr_safe_regs_on_cpu(unsigned int cpu, u32 regs[8]) |
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295 | { |
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296 | return wrmsr_safe_regs(regs); |
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297 | } |
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298 | #endif /* CONFIG_SMP */ |
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299 | #endif /* __ASSEMBLY__ */ |
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300 | #endif /* _ASM_X86_MSR_H */><>><> |