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6936 | serge | 1 | #ifndef _ASM_X86_IO_H |
2 | #define _ASM_X86_IO_H |
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3 | |||
4 | /* |
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5 | * This file contains the definitions for the x86 IO instructions |
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6 | * inb/inw/inl/outb/outw/outl and the "string versions" of the same |
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7 | * (insb/insw/insl/outsb/outsw/outsl). You can also use "pausing" |
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8 | * versions of the single-IO instructions (inb_p/inw_p/..). |
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9 | * |
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10 | * This file is not meant to be obfuscating: it's just complicated |
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11 | * to (a) handle it all in a way that makes gcc able to optimize it |
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12 | * as well as possible and (b) trying to avoid writing the same thing |
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13 | * over and over again with slight variations and possibly making a |
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14 | * mistake somewhere. |
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15 | */ |
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16 | |||
17 | /* |
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18 | * Thanks to James van Artsdalen for a better timing-fix than |
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19 | * the two short jumps: using outb's to a nonexistent port seems |
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20 | * to guarantee better timings even on fast machines. |
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21 | * |
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22 | * On the other hand, I'd like to be sure of a non-existent port: |
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23 | * I feel a bit unsafe about using 0x80 (should be safe, though) |
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24 | * |
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25 | * Linus |
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26 | */ |
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27 | |||
28 | /* |
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29 | * Bit simplified and optimized by Jan Hubicka |
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30 | * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999. |
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31 | * |
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32 | * isa_memset_io, isa_memcpy_fromio, isa_memcpy_toio added, |
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33 | * isa_read[wl] and isa_write[wl] fixed |
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34 | * - Arnaldo Carvalho de Melo |
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35 | */ |
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36 | |||
37 | #define ARCH_HAS_IOREMAP_WC |
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38 | #define ARCH_HAS_IOREMAP_WT |
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39 | |||
40 | #include |
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41 | #include |
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42 | |||
43 | #define build_mmio_read(name, size, type, reg, barrier) \ |
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44 | static inline type name(const volatile void __iomem *addr) \ |
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45 | { type ret; asm volatile("mov" size " %1,%0":reg (ret) \ |
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46 | :"m" (*(volatile type __force *)addr) barrier); return ret; } |
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47 | |||
48 | #define build_mmio_write(name, size, type, reg, barrier) \ |
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49 | static inline void name(type val, volatile void __iomem *addr) \ |
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50 | { asm volatile("mov" size " %0,%1": :reg (val), \ |
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51 | "m" (*(volatile type __force *)addr) barrier); } |
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52 | |||
53 | build_mmio_read(readb, "b", unsigned char, "=q", :"memory") |
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54 | build_mmio_read(readw, "w", unsigned short, "=r", :"memory") |
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55 | build_mmio_read(readl, "l", unsigned int, "=r", :"memory") |
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56 | |||
57 | build_mmio_read(__readb, "b", unsigned char, "=q", ) |
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58 | build_mmio_read(__readw, "w", unsigned short, "=r", ) |
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59 | build_mmio_read(__readl, "l", unsigned int, "=r", ) |
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60 | |||
61 | build_mmio_write(writeb, "b", unsigned char, "q", :"memory") |
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62 | build_mmio_write(writew, "w", unsigned short, "r", :"memory") |
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63 | build_mmio_write(writel, "l", unsigned int, "r", :"memory") |
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64 | |||
65 | build_mmio_write(__writeb, "b", unsigned char, "q", ) |
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66 | build_mmio_write(__writew, "w", unsigned short, "r", ) |
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67 | build_mmio_write(__writel, "l", unsigned int, "r", ) |
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68 | |||
69 | #define readb_relaxed(a) __readb(a) |
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70 | #define readw_relaxed(a) __readw(a) |
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71 | #define readl_relaxed(a) __readl(a) |
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72 | #define __raw_readb __readb |
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73 | #define __raw_readw __readw |
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74 | #define __raw_readl __readl |
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75 | |||
76 | #define writeb_relaxed(v, a) __writeb(v, a) |
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77 | #define writew_relaxed(v, a) __writew(v, a) |
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78 | #define writel_relaxed(v, a) __writel(v, a) |
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79 | #define __raw_writeb __writeb |
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80 | #define __raw_writew __writew |
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81 | #define __raw_writel __writel |
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82 | |||
83 | #define mmiowb() barrier() |
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84 | |||
85 | #ifdef CONFIG_X86_64 |
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86 | |||
87 | build_mmio_read(readq, "q", unsigned long, "=r", :"memory") |
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88 | build_mmio_write(writeq, "q", unsigned long, "r", :"memory") |
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89 | |||
90 | #define readq_relaxed(a) readq(a) |
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91 | #define writeq_relaxed(v, a) writeq(v, a) |
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92 | |||
93 | #define __raw_readq(a) readq(a) |
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94 | #define __raw_writeq(val, addr) writeq(val, addr) |
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95 | |||
96 | /* Let people know that we have them */ |
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97 | #define readq readq |
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98 | #define writeq writeq |
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99 | |||
100 | #endif |
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101 | |||
102 | /** |
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103 | * virt_to_phys - map virtual addresses to physical |
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104 | * @address: address to remap |
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105 | * |
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106 | * The returned physical address is the physical (CPU) mapping for |
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107 | * the memory address given. It is only valid to use this function on |
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108 | * addresses directly mapped or allocated via kmalloc. |
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109 | * |
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110 | * This function does not give bus mappings for DMA transfers. In |
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111 | * almost all conceivable cases a device driver should not be using |
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112 | * this function |
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113 | */ |
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114 | |||
115 | |||
116 | /** |
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117 | * phys_to_virt - map physical address to virtual |
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118 | * @address: address to remap |
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119 | * |
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120 | * The returned virtual address is a current CPU mapping for |
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121 | * the memory address given. It is only valid to use this function on |
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122 | * addresses that have a kernel mapping |
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123 | * |
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124 | * This function does not handle bus mappings for DMA transfers. In |
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125 | * almost all conceivable cases a device driver should not be using |
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126 | * this function |
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127 | */ |
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128 | |||
129 | #define isa_page_to_bus(page) ((unsigned int)page_to_phys(page)) |
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130 | #define isa_bus_to_virt phys_to_virt |
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131 | |||
132 | /* |
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133 | * However PCI ones are not necessarily 1:1 and therefore these interfaces |
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134 | * are forbidden in portable PCI drivers. |
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135 | * |
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136 | * Allow them on x86 for legacy drivers, though. |
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137 | */ |
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138 | #define virt_to_bus virt_to_phys |
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139 | #define bus_to_virt phys_to_virt |
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140 | |||
141 | /** |
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142 | * ioremap - map bus memory into CPU space |
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143 | * @offset: bus address of the memory |
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144 | * @size: size of the resource to map |
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145 | * |
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146 | * ioremap performs a platform specific sequence of operations to |
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147 | * make bus memory CPU accessible via the readb/readw/readl/writeb/ |
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148 | * writew/writel functions and the other mmio helpers. The returned |
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149 | * address is not guaranteed to be usable directly as a virtual |
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150 | * address. |
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151 | * |
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152 | * If the area you are trying to map is a PCI BAR you should have a |
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153 | * look at pci_iomap(). |
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154 | */ |
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155 | //extern void __iomem *ioremap_nocache(resource_size_t offset, unsigned long size); |
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156 | extern void __iomem *ioremap_uc(resource_size_t offset, unsigned long size); |
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157 | #define ioremap_uc ioremap_uc |
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158 | |||
159 | extern void __iomem *ioremap_cache(resource_size_t offset, unsigned long size); |
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160 | extern void __iomem *ioremap_prot(resource_size_t offset, unsigned long size, |
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161 | unsigned long prot_val); |
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162 | |||
163 | /* |
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164 | * The default ioremap() behavior is non-cached: |
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165 | */ |
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166 | //static inline void __iomem *ioremap(resource_size_t offset, unsigned long size) |
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167 | //{ |
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168 | // return ioremap_nocache(offset, size); |
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169 | //} |
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170 | |||
171 | //extern void iounmap(volatile void __iomem *addr); |
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172 | |||
173 | extern void set_iounmap_nonlazy(void); |
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174 | |||
175 | #ifdef __KERNEL__ |
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176 | |||
177 | #include |
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178 | |||
179 | /* |
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180 | * Convert a virtual cached pointer to an uncached pointer |
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181 | */ |
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182 | #define xlate_dev_kmem_ptr(p) p |
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183 | |||
184 | static inline void |
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185 | memset_io(volatile void __iomem *addr, unsigned char val, size_t count) |
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186 | { |
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187 | memset((void __force *)addr, val, count); |
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188 | } |
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189 | |||
190 | static inline void |
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191 | memcpy_fromio(void *dst, const volatile void __iomem *src, size_t count) |
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192 | { |
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193 | memcpy(dst, (const void __force *)src, count); |
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194 | } |
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195 | |||
196 | static inline void |
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197 | memcpy_toio(volatile void __iomem *dst, const void *src, size_t count) |
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198 | { |
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199 | memcpy((void __force *)dst, src, count); |
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200 | } |
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201 | |||
202 | /* |
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203 | * ISA space is 'always mapped' on a typical x86 system, no need to |
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204 | * explicitly ioremap() it. The fact that the ISA IO space is mapped |
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205 | * to PAGE_OFFSET is pure coincidence - it does not mean ISA values |
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206 | * are physical addresses. The following constant pointer can be |
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207 | * used as the IO-area pointer (it can be iounmapped as well, so the |
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208 | * analogy with PCI is quite large): |
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209 | */ |
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210 | #define __ISA_IO_base ((char __iomem *)(PAGE_OFFSET)) |
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211 | |||
212 | /* |
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213 | * Cache management |
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214 | * |
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215 | * This needed for two cases |
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216 | * 1. Out of order aware processors |
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217 | * 2. Accidentally out of order processors (PPro errata #51) |
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218 | */ |
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219 | |||
220 | static inline void flush_write_buffers(void) |
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221 | { |
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222 | #if defined(CONFIG_X86_PPRO_FENCE) |
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223 | asm volatile("lock; addl $0,0(%%esp)": : :"memory"); |
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224 | #endif |
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225 | } |
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226 | |||
227 | #endif /* __KERNEL__ */ |
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228 | |||
229 | extern void native_io_delay(void); |
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230 | |||
231 | extern int io_delay_type; |
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232 | extern void io_delay_init(void); |
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233 | |||
234 | #if defined(CONFIG_PARAVIRT) |
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235 | #include |
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236 | #else |
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237 | |||
238 | static inline void slow_down_io(void) |
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239 | { |
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240 | native_io_delay(); |
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241 | #ifdef REALLY_SLOW_IO |
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242 | native_io_delay(); |
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243 | native_io_delay(); |
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244 | native_io_delay(); |
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245 | #endif |
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246 | } |
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247 | |||
248 | #endif |
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249 | |||
250 | #define BUILDIO(bwl, bw, type) \ |
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251 | static inline void out##bwl(unsigned type value, int port) \ |
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252 | { \ |
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253 | asm volatile("out" #bwl " %" #bw "0, %w1" \ |
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254 | : : "a"(value), "Nd"(port)); \ |
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255 | } \ |
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256 | \ |
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257 | static inline unsigned type in##bwl(int port) \ |
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258 | { \ |
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259 | unsigned type value; \ |
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260 | asm volatile("in" #bwl " %w1, %" #bw "0" \ |
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261 | : "=a"(value) : "Nd"(port)); \ |
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262 | return value; \ |
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263 | } \ |
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264 | \ |
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265 | static inline void out##bwl##_p(unsigned type value, int port) \ |
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266 | { \ |
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267 | out##bwl(value, port); \ |
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268 | slow_down_io(); \ |
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269 | } \ |
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270 | \ |
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271 | static inline unsigned type in##bwl##_p(int port) \ |
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272 | { \ |
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273 | unsigned type value = in##bwl(port); \ |
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274 | slow_down_io(); \ |
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275 | return value; \ |
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276 | } \ |
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277 | \ |
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278 | static inline void outs##bwl(int port, const void *addr, unsigned long count) \ |
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279 | { \ |
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280 | asm volatile("rep; outs" #bwl \ |
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281 | : "+S"(addr), "+c"(count) : "d"(port)); \ |
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282 | } \ |
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283 | \ |
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284 | static inline void ins##bwl(int port, void *addr, unsigned long count) \ |
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285 | { \ |
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286 | asm volatile("rep; ins" #bwl \ |
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287 | : "+D"(addr), "+c"(count) : "d"(port)); \ |
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288 | } |
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289 | |||
290 | BUILDIO(b, b, char) |
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291 | BUILDIO(w, w, short) |
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292 | BUILDIO(l, , int) |
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293 | |||
294 | extern void *xlate_dev_mem_ptr(phys_addr_t phys); |
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295 | extern void unxlate_dev_mem_ptr(phys_addr_t phys, void *addr); |
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296 | |||
297 | extern int ioremap_change_attr(unsigned long vaddr, unsigned long size, |
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298 | enum page_cache_mode pcm); |
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299 | //extern void __iomem *ioremap_wc(resource_size_t offset, unsigned long size); |
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300 | extern void __iomem *ioremap_wt(resource_size_t offset, unsigned long size); |
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301 | |||
302 | extern bool is_early_ioremap_ptep(pte_t *ptep); |
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303 | |||
304 | #ifdef CONFIG_XEN |
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305 | #include |
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306 | struct bio_vec; |
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307 | |||
308 | extern bool xen_biovec_phys_mergeable(const struct bio_vec *vec1, |
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309 | const struct bio_vec *vec2); |
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310 | |||
311 | #define BIOVEC_PHYS_MERGEABLE(vec1, vec2) \ |
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312 | (__BIOVEC_PHYS_MERGEABLE(vec1, vec2) && \ |
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313 | (!xen_domain() || xen_biovec_phys_mergeable(vec1, vec2))) |
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314 | #endif /* CONFIG_XEN */ |
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315 | |||
316 | #define IO_SPACE_LIMIT 0xffff |
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317 | |||
318 | #ifdef CONFIG_MTRR |
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319 | extern int __must_check arch_phys_wc_index(int handle); |
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320 | #define arch_phys_wc_index arch_phys_wc_index |
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321 | |||
322 | extern int __must_check arch_phys_wc_add(unsigned long base, |
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323 | unsigned long size); |
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324 | extern void arch_phys_wc_del(int handle); |
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325 | #define arch_phys_wc_add arch_phys_wc_add |
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326 | #endif |
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327 | |||
328 | #endif /* _ASM_X86_IO_H */ |