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#ifndef _ASM_X86_CMPXCHG_32_H
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#define _ASM_X86_CMPXCHG_32_H
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/*
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 * Note: if you use set64_bit(), __cmpxchg64(), or their variants, you
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 *       you need to test for the feature in boot_cpu_data.
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 */
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/*
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 * CMPXCHG8B only writes to the target if we had the previous
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 * value in registers, otherwise it acts as a read and gives us the
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 * "new previous" value.  That is why there is a loop.  Preloading
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 * EDX:EAX is a performance optimization: in the common case it means
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 * we need only one locked operation.
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 *
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 * A SIMD/3DNOW!/MMX/FPU 64-bit store here would require at the very
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 * least an FPU save and/or %cr0.ts manipulation.
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 *
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 * cmpxchg8b must be used with the lock prefix here to allow the
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 * instruction to be executed atomically.  We need to have the reader
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 * side to see the coherent 64bit value.
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 */
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static inline void set_64bit(volatile u64 *ptr, u64 value)
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{
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	u32 low  = value;
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	u32 high = value >> 32;
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	u64 prev = *ptr;
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	asm volatile("\n1:\t"
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		     LOCK_PREFIX "cmpxchg8b %0\n\t"
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		     "jnz 1b"
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		     : "=m" (*ptr), "+A" (prev)
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		     : "b" (low), "c" (high)
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		     : "memory");
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}
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#ifdef CONFIG_X86_CMPXCHG64
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#define cmpxchg64(ptr, o, n)						\
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	((__typeof__(*(ptr)))__cmpxchg64((ptr), (unsigned long long)(o), \
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					 (unsigned long long)(n)))
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#define cmpxchg64_local(ptr, o, n)					\
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	((__typeof__(*(ptr)))__cmpxchg64_local((ptr), (unsigned long long)(o), \
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					       (unsigned long long)(n)))
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#endif
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static inline u64 __cmpxchg64(volatile u64 *ptr, u64 old, u64 new)
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{
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	u64 prev;
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	asm volatile(LOCK_PREFIX "cmpxchg8b %1"
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		     : "=A" (prev),
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		       "+m" (*ptr)
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		     : "b" ((u32)new),
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		       "c" ((u32)(new >> 32)),
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		       "0" (old)
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		     : "memory");
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	return prev;
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}
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static inline u64 __cmpxchg64_local(volatile u64 *ptr, u64 old, u64 new)
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{
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	u64 prev;
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	asm volatile("cmpxchg8b %1"
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		     : "=A" (prev),
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		       "+m" (*ptr)
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		     : "b" ((u32)new),
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		       "c" ((u32)(new >> 32)),
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		       "0" (old)
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		     : "memory");
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	return prev;
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}
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#ifndef CONFIG_X86_CMPXCHG64
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/*
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 * Building a kernel capable running on 80386 and 80486. It may be necessary
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 * to simulate the cmpxchg8b on the 80386 and 80486 CPU.
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 */
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#define cmpxchg64(ptr, o, n)					\
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({								\
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	__typeof__(*(ptr)) __ret;				\
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	__typeof__(*(ptr)) __old = (o);				\
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	__typeof__(*(ptr)) __new = (n);				\
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	alternative_io(LOCK_PREFIX_HERE				\
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			"call cmpxchg8b_emu",			\
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			"lock; cmpxchg8b (%%esi)" ,		\
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		       X86_FEATURE_CX8,				\
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		       "=A" (__ret),				\
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		       "S" ((ptr)), "0" (__old),		\
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		       "b" ((unsigned int)__new),		\
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		       "c" ((unsigned int)(__new>>32))		\
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		       : "memory");				\
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	__ret; })
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#define cmpxchg64_local(ptr, o, n)				\
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({								\
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	__typeof__(*(ptr)) __ret;				\
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	__typeof__(*(ptr)) __old = (o);				\
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	__typeof__(*(ptr)) __new = (n);				\
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	alternative_io("call cmpxchg8b_emu",			\
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		       "cmpxchg8b (%%esi)" ,			\
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		       X86_FEATURE_CX8,				\
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		       "=A" (__ret),				\
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		       "S" ((ptr)), "0" (__old),		\
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		       "b" ((unsigned int)__new),		\
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		       "c" ((unsigned int)(__new>>32))		\
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		       : "memory");				\
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	__ret; })
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#endif
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#define system_has_cmpxchg_double() cpu_has_cx8
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#endif /* _ASM_X86_CMPXCHG_32_H */