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5270 | serge | 1 | #ifndef _ASM_X86_CMPXCHG_32_H |
2 | #define _ASM_X86_CMPXCHG_32_H |
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3 | |||
4 | /* |
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5 | * Note: if you use set64_bit(), __cmpxchg64(), or their variants, you |
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6 | * you need to test for the feature in boot_cpu_data. |
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7 | */ |
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8 | |||
9 | /* |
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10 | * CMPXCHG8B only writes to the target if we had the previous |
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11 | * value in registers, otherwise it acts as a read and gives us the |
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12 | * "new previous" value. That is why there is a loop. Preloading |
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13 | * EDX:EAX is a performance optimization: in the common case it means |
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14 | * we need only one locked operation. |
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15 | * |
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16 | * A SIMD/3DNOW!/MMX/FPU 64-bit store here would require at the very |
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17 | * least an FPU save and/or %cr0.ts manipulation. |
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18 | * |
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19 | * cmpxchg8b must be used with the lock prefix here to allow the |
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20 | * instruction to be executed atomically. We need to have the reader |
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21 | * side to see the coherent 64bit value. |
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22 | */ |
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23 | static inline void set_64bit(volatile u64 *ptr, u64 value) |
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24 | { |
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25 | u32 low = value; |
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26 | u32 high = value >> 32; |
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27 | u64 prev = *ptr; |
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28 | |||
29 | asm volatile("\n1:\t" |
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30 | LOCK_PREFIX "cmpxchg8b %0\n\t" |
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31 | "jnz 1b" |
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32 | : "=m" (*ptr), "+A" (prev) |
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33 | : "b" (low), "c" (high) |
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34 | : "memory"); |
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35 | } |
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36 | |||
37 | #ifdef CONFIG_X86_CMPXCHG64 |
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38 | #define cmpxchg64(ptr, o, n) \ |
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39 | ((__typeof__(*(ptr)))__cmpxchg64((ptr), (unsigned long long)(o), \ |
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40 | (unsigned long long)(n))) |
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41 | #define cmpxchg64_local(ptr, o, n) \ |
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42 | ((__typeof__(*(ptr)))__cmpxchg64_local((ptr), (unsigned long long)(o), \ |
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43 | (unsigned long long)(n))) |
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44 | #endif |
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45 | |||
46 | static inline u64 __cmpxchg64(volatile u64 *ptr, u64 old, u64 new) |
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47 | { |
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48 | u64 prev; |
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49 | asm volatile(LOCK_PREFIX "cmpxchg8b %1" |
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50 | : "=A" (prev), |
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51 | "+m" (*ptr) |
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52 | : "b" ((u32)new), |
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53 | "c" ((u32)(new >> 32)), |
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54 | "0" (old) |
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55 | : "memory"); |
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56 | return prev; |
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57 | } |
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58 | |||
59 | static inline u64 __cmpxchg64_local(volatile u64 *ptr, u64 old, u64 new) |
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60 | { |
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61 | u64 prev; |
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62 | asm volatile("cmpxchg8b %1" |
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63 | : "=A" (prev), |
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64 | "+m" (*ptr) |
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65 | : "b" ((u32)new), |
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66 | "c" ((u32)(new >> 32)), |
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67 | "0" (old) |
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68 | : "memory"); |
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69 | return prev; |
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70 | } |
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71 | |||
72 | #ifndef CONFIG_X86_CMPXCHG64 |
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73 | /* |
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74 | * Building a kernel capable running on 80386 and 80486. It may be necessary |
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75 | * to simulate the cmpxchg8b on the 80386 and 80486 CPU. |
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76 | */ |
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77 | |||
78 | #define cmpxchg64(ptr, o, n) \ |
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79 | ({ \ |
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80 | __typeof__(*(ptr)) __ret; \ |
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81 | __typeof__(*(ptr)) __old = (o); \ |
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82 | __typeof__(*(ptr)) __new = (n); \ |
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83 | alternative_io(LOCK_PREFIX_HERE \ |
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84 | "call cmpxchg8b_emu", \ |
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85 | "lock; cmpxchg8b (%%esi)" , \ |
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86 | X86_FEATURE_CX8, \ |
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87 | "=A" (__ret), \ |
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88 | "S" ((ptr)), "0" (__old), \ |
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89 | "b" ((unsigned int)__new), \ |
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90 | "c" ((unsigned int)(__new>>32)) \ |
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91 | : "memory"); \ |
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92 | __ret; }) |
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93 | |||
94 | |||
95 | #define cmpxchg64_local(ptr, o, n) \ |
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96 | ({ \ |
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97 | __typeof__(*(ptr)) __ret; \ |
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98 | __typeof__(*(ptr)) __old = (o); \ |
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99 | __typeof__(*(ptr)) __new = (n); \ |
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100 | alternative_io("call cmpxchg8b_emu", \ |
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101 | "cmpxchg8b (%%esi)" , \ |
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102 | X86_FEATURE_CX8, \ |
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103 | "=A" (__ret), \ |
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104 | "S" ((ptr)), "0" (__old), \ |
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105 | "b" ((unsigned int)__new), \ |
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106 | "c" ((unsigned int)(__new>>32)) \ |
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107 | : "memory"); \ |
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108 | __ret; }) |
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109 | |||
110 | #endif |
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111 | |||
112 | #define system_has_cmpxchg_double() cpu_has_cx8 |
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113 | |||
114 | #endif /* _ASM_X86_CMPXCHG_32_H */ |