Rev 5140 | Rev 5363 | Go to most recent revision | Details | Compare with Previous | Last modification | View Log | RSS feed
Rev | Author | Line No. | Line |
---|---|---|---|
3545 | hidnplayr | 1 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
2 | ;; ;; |
||
4467 | hidnplayr | 3 | ;; Copyright (C) KolibriOS team 2004-2014. All rights reserved. ;; |
3545 | hidnplayr | 4 | ;; Distributed under terms of the GNU General Public License ;; |
5 | ;; ;; |
||
6 | ;; i8254x driver for KolibriOS ;; |
||
7 | ;; ;; |
||
8 | ;; based on i8254x.asm from baremetal os ;; |
||
9 | ;; ;; |
||
10 | ;; Written by hidnplayr (hidnplayr@gmail.com) ;; |
||
11 | ;; ;; |
||
12 | ;; GNU GENERAL PUBLIC LICENSE ;; |
||
13 | ;; Version 2, June 1991 ;; |
||
14 | ;; ;; |
||
15 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
||
16 | |||
4522 | hidnplayr | 17 | format PE DLL native |
18 | entry START |
||
3545 | hidnplayr | 19 | |
4522 | hidnplayr | 20 | CURRENT_API = 0x0200 |
21 | COMPATIBLE_API = 0x0100 |
||
22 | API_VERSION = (COMPATIBLE_API shl 16) + CURRENT_API |
||
3545 | hidnplayr | 23 | |
24 | MAX_DEVICES = 16 |
||
25 | |||
26 | __DEBUG__ = 1 |
||
3855 | hidnplayr | 27 | __DEBUG_LEVEL__ = 2 ; 1 = verbose, 2 = errors only |
3545 | hidnplayr | 28 | |
4512 | hidnplayr | 29 | MAX_PKT_SIZE = 4096 ; Maximum packet size |
3545 | hidnplayr | 30 | |
4519 | hidnplayr | 31 | RX_RING_SIZE = 8 ; Must be a power of 2, and minimum 8 |
32 | TX_RING_SIZE = 8 ; Must be a power of 2, and minimum 8 |
||
4512 | hidnplayr | 33 | |
4522 | hidnplayr | 34 | section '.flat' readable writable executable |
35 | |||
36 | include '../proc32.inc' |
||
4467 | hidnplayr | 37 | include '../struct.inc' |
38 | include '../macros.inc' |
||
3545 | hidnplayr | 39 | include '../fdo.inc' |
5074 | hidnplayr | 40 | include '../netdrv.inc' |
3545 | hidnplayr | 41 | |
42 | ; Register list |
||
43 | REG_CTRL = 0x0000 ; Control Register |
||
44 | REG_STATUS = 0x0008 ; Device Status Register |
||
45 | REG_CTRLEXT = 0x0018 ; Extended Control Register |
||
46 | REG_MDIC = 0x0020 ; MDI Control Register |
||
47 | REG_FCAL = 0x0028 ; Flow Control Address Low |
||
48 | REG_FCAH = 0x002C ; Flow Control Address High |
||
49 | REG_FCT = 0x0030 ; Flow Control Type |
||
50 | REG_VET = 0x0038 ; VLAN Ether Type |
||
51 | REG_ICR = 0x00C0 ; Interrupt Cause Read |
||
52 | REG_ITR = 0x00C4 ; Interrupt Throttling Register |
||
53 | REG_ICS = 0x00C8 ; Interrupt Cause Set Register |
||
54 | REG_IMS = 0x00D0 ; Interrupt Mask Set/Read Register |
||
55 | REG_IMC = 0x00D8 ; Interrupt Mask Clear Register |
||
56 | REG_RCTL = 0x0100 ; Receive Control Register |
||
57 | REG_FCTTV = 0x0170 ; Flow Control Transmit Timer Value |
||
58 | REG_TXCW = 0x0178 ; Transmit Configuration Word |
||
59 | REG_RXCW = 0x0180 ; Receive Configuration Word |
||
60 | REG_TCTL = 0x0400 ; Transmit Control Register |
||
61 | REG_TIPG = 0x0410 ; Transmit Inter Packet Gap |
||
62 | |||
63 | REG_LEDCTL = 0x0E00 ; LED Control |
||
64 | REG_PBA = 0x1000 ; Packet Buffer Allocation |
||
65 | |||
66 | REG_RDBAL = 0x2800 ; RX Descriptor Base Address Low |
||
67 | REG_RDBAH = 0x2804 ; RX Descriptor Base Address High |
||
68 | REG_RDLEN = 0x2808 ; RX Descriptor Length |
||
69 | REG_RDH = 0x2810 ; RX Descriptor Head |
||
70 | REG_RDT = 0x2818 ; RX Descriptor Tail |
||
71 | REG_RDTR = 0x2820 ; RX Delay Timer Register |
||
72 | REG_RXDCTL = 0x3828 ; RX Descriptor Control |
||
73 | REG_RADV = 0x282C ; RX Int. Absolute Delay Timer |
||
74 | REG_RSRPD = 0x2C00 ; RX Small Packet Detect Interrupt |
||
75 | |||
76 | REG_TXDMAC = 0x3000 ; TX DMA Control |
||
77 | REG_TDBAL = 0x3800 ; TX Descriptor Base Address Low |
||
78 | REG_TDBAH = 0x3804 ; TX Descriptor Base Address High |
||
79 | REG_TDLEN = 0x3808 ; TX Descriptor Length |
||
80 | REG_TDH = 0x3810 ; TX Descriptor Head |
||
81 | REG_TDT = 0x3818 ; TX Descriptor Tail |
||
82 | REG_TIDV = 0x3820 ; TX Interrupt Delay Value |
||
83 | REG_TXDCTL = 0x3828 ; TX Descriptor Control |
||
84 | REG_TADV = 0x382C ; TX Absolute Interrupt Delay Value |
||
85 | REG_TSPMT = 0x3830 ; TCP Segmentation Pad & Min Threshold |
||
86 | |||
87 | REG_RXCSUM = 0x5000 ; RX Checksum Control |
||
88 | |||
89 | ; Register list for i8254x |
||
90 | I82542_REG_RDTR = 0x0108 ; RX Delay Timer Register |
||
91 | I82542_REG_RDBAL = 0x0110 ; RX Descriptor Base Address Low |
||
92 | I82542_REG_RDBAH = 0x0114 ; RX Descriptor Base Address High |
||
93 | I82542_REG_RDLEN = 0x0118 ; RX Descriptor Length |
||
94 | I82542_REG_RDH = 0x0120 ; RDH for i82542 |
||
95 | I82542_REG_RDT = 0x0128 ; RDT for i82542 |
||
96 | I82542_REG_TDBAL = 0x0420 ; TX Descriptor Base Address Low |
||
97 | I82542_REG_TDBAH = 0x0424 ; TX Descriptor Base Address Low |
||
98 | I82542_REG_TDLEN = 0x0428 ; TX Descriptor Length |
||
99 | I82542_REG_TDH = 0x0430 ; TDH for i82542 |
||
100 | I82542_REG_TDT = 0x0438 ; TDT for i82542 |
||
101 | |||
102 | ; CTRL - Control Register (0x0000) |
||
103 | CTRL_FD = 0x00000001 ; Full Duplex |
||
104 | CTRL_LRST = 0x00000008 ; Link Reset |
||
105 | CTRL_ASDE = 0x00000020 ; Auto-speed detection |
||
106 | CTRL_SLU = 0x00000040 ; Set Link Up |
||
107 | CTRL_ILOS = 0x00000080 ; Invert Loss of Signal |
||
108 | CTRL_SPEED_MASK = 0x00000300 ; Speed selection |
||
109 | CTRL_SPEED_SHIFT = 8 |
||
110 | CTRL_FRCSPD = 0x00000800 ; Force Speed |
||
111 | CTRL_FRCDPLX = 0x00001000 ; Force Duplex |
||
112 | CTRL_SDP0_DATA = 0x00040000 ; SDP0 data |
||
113 | CTRL_SDP1_DATA = 0x00080000 ; SDP1 data |
||
114 | CTRL_SDP0_IODIR = 0x00400000 ; SDP0 direction |
||
115 | CTRL_SDP1_IODIR = 0x00800000 ; SDP1 direction |
||
116 | CTRL_RST = 0x04000000 ; Device Reset |
||
117 | CTRL_RFCE = 0x08000000 ; RX Flow Ctrl Enable |
||
118 | CTRL_TFCE = 0x10000000 ; TX Flow Ctrl Enable |
||
119 | CTRL_VME = 0x40000000 ; VLAN Mode Enable |
||
120 | CTRL_PHY_RST = 0x80000000 ; PHY reset |
||
121 | |||
122 | ; STATUS - Device Status Register (0x0008) |
||
123 | STATUS_FD = 0x00000001 ; Full Duplex |
||
124 | STATUS_LU = 0x00000002 ; Link Up |
||
125 | STATUS_TXOFF = 0x00000010 ; Transmit paused |
||
126 | STATUS_TBIMODE = 0x00000020 ; TBI Mode |
||
127 | STATUS_SPEED_MASK = 0x000000C0 ; Link Speed setting |
||
128 | STATUS_SPEED_SHIFT = 6 |
||
129 | STATUS_ASDV_MASK = 0x00000300 ; Auto Speed Detection |
||
130 | STATUS_ASDV_SHIFT = 8 |
||
131 | STATUS_PCI66 = 0x00000800 ; PCI bus speed |
||
132 | STATUS_BUS64 = 0x00001000 ; PCI bus width |
||
133 | STATUS_PCIX_MODE = 0x00002000 ; PCI-X mode |
||
134 | STATUS_PCIXSPD_MASK = 0x0000C000 ; PCI-X speed |
||
135 | STATUS_PCIXSPD_SHIFT = 14 |
||
136 | |||
137 | ; CTRL_EXT - Extended Device Control Register (0x0018) |
||
138 | CTRLEXT_PHY_INT = 0x00000020 ; PHY interrupt |
||
139 | CTRLEXT_SDP6_DATA = 0x00000040 ; SDP6 data |
||
140 | CTRLEXT_SDP7_DATA = 0x00000080 ; SDP7 data |
||
141 | CTRLEXT_SDP6_IODIR = 0x00000400 ; SDP6 direction |
||
142 | CTRLEXT_SDP7_IODIR = 0x00000800 ; SDP7 direction |
||
143 | CTRLEXT_ASDCHK = 0x00001000 ; Auto-Speed Detect Chk |
||
144 | CTRLEXT_EE_RST = 0x00002000 ; EEPROM reset |
||
145 | CTRLEXT_SPD_BYPS = 0x00008000 ; Speed Select Bypass |
||
146 | CTRLEXT_RO_DIS = 0x00020000 ; Relaxed Ordering Dis. |
||
147 | CTRLEXT_LNKMOD_MASK = 0x00C00000 ; Link Mode |
||
148 | CTRLEXT_LNKMOD_SHIFT = 22 |
||
149 | |||
150 | ; MDIC - MDI Control Register (0x0020) |
||
151 | MDIC_DATA_MASK = 0x0000FFFF ; Data |
||
152 | MDIC_REG_MASK = 0x001F0000 ; PHY Register |
||
153 | MDIC_REG_SHIFT = 16 |
||
154 | MDIC_PHY_MASK = 0x03E00000 ; PHY Address |
||
155 | MDIC_PHY_SHIFT = 21 |
||
156 | MDIC_OP_MASK = 0x0C000000 ; Opcode |
||
157 | MDIC_OP_SHIFT = 26 |
||
158 | MDIC_R = 0x10000000 ; Ready |
||
159 | MDIC_I = 0x20000000 ; Interrupt Enable |
||
160 | MDIC_E = 0x40000000 ; Error |
||
161 | |||
162 | ; ICR - Interrupt Cause Read (0x00c0) |
||
163 | ICR_TXDW = 0x00000001 ; TX Desc Written back |
||
164 | ICR_TXQE = 0x00000002 ; TX Queue Empty |
||
165 | ICR_LSC = 0x00000004 ; Link Status Change |
||
166 | ICR_RXSEQ = 0x00000008 ; RX Sence Error |
||
167 | ICR_RXDMT0 = 0x00000010 ; RX Desc min threshold reached |
||
168 | ICR_RXO = 0x00000040 ; RX Overrun |
||
169 | ICR_RXT0 = 0x00000080 ; RX Timer Interrupt |
||
170 | ICR_MDAC = 0x00000200 ; MDIO Access Complete |
||
171 | ICR_RXCFG = 0x00000400 |
||
172 | ICR_PHY_INT = 0x00001000 ; PHY Interrupt |
||
173 | ICR_GPI_SDP6 = 0x00002000 ; GPI on SDP6 |
||
174 | ICR_GPI_SDP7 = 0x00004000 ; GPI on SDP7 |
||
175 | ICR_TXD_LOW = 0x00008000 ; TX Desc low threshold hit |
||
176 | ICR_SRPD = 0x00010000 ; Small RX packet detected |
||
177 | |||
178 | ; RCTL - Receive Control Register (0x0100) |
||
179 | RCTL_EN = 0x00000002 ; Receiver Enable |
||
180 | RCTL_SBP = 0x00000004 ; Store Bad Packets |
||
181 | RCTL_UPE = 0x00000008 ; Unicast Promiscuous Enabled |
||
182 | RCTL_MPE = 0x00000010 ; Xcast Promiscuous Enabled |
||
183 | RCTL_LPE = 0x00000020 ; Long Packet Reception Enable |
||
184 | RCTL_LBM_MASK = 0x000000C0 ; Loopback Mode |
||
185 | RCTL_LBM_SHIFT = 6 |
||
186 | RCTL_RDMTS_MASK = 0x00000300 ; RX Desc Min Threshold Size |
||
187 | RCTL_RDMTS_SHIFT = 8 |
||
188 | RCTL_MO_MASK = 0x00003000 ; Multicast Offset |
||
189 | RCTL_MO_SHIFT = 12 |
||
190 | RCTL_BAM = 0x00008000 ; Broadcast Accept Mode |
||
191 | RCTL_BSIZE_MASK = 0x00030000 ; RX Buffer Size |
||
192 | RCTL_BSIZE_SHIFT = 16 |
||
193 | RCTL_VFE = 0x00040000 ; VLAN Filter Enable |
||
194 | RCTL_CFIEN = 0x00080000 ; CFI Enable |
||
195 | RCTL_CFI = 0x00100000 ; Canonical Form Indicator Bit |
||
196 | RCTL_DPF = 0x00400000 ; Discard Pause Frames |
||
197 | RCTL_PMCF = 0x00800000 ; Pass MAC Control Frames |
||
198 | RCTL_BSEX = 0x02000000 ; Buffer Size Extension |
||
199 | RCTL_SECRC = 0x04000000 ; Strip Ethernet CRC |
||
200 | |||
201 | ; TCTL - Transmit Control Register (0x0400) |
||
202 | TCTL_EN = 0x00000002 ; Transmit Enable |
||
203 | TCTL_PSP = 0x00000008 ; Pad short packets |
||
204 | TCTL_SWXOFF = 0x00400000 ; Software XOFF Transmission |
||
205 | |||
206 | ; PBA - Packet Buffer Allocation (0x1000) |
||
207 | PBA_RXA_MASK = 0x0000FFFF ; RX Packet Buffer |
||
208 | PBA_RXA_SHIFT = 0 |
||
209 | PBA_TXA_MASK = 0xFFFF0000 ; TX Packet Buffer |
||
210 | PBA_TXA_SHIFT = 16 |
||
211 | |||
212 | ; Flow Control Type |
||
213 | FCT_TYPE_DEFAULT = 0x8808 |
||
214 | |||
215 | |||
4519 | hidnplayr | 216 | |
217 | ; === TX Descriptor === |
||
218 | |||
219 | struct TDESC |
||
220 | addr_l dd ? |
||
221 | addr_h dd ? |
||
222 | length_cso_cmd dd ? ; 16 bits length + 8 bits cso + 8 bits cmd |
||
223 | status dd ? ; status, checksum start field, special |
||
224 | ends |
||
225 | |||
3545 | hidnplayr | 226 | ; TX Packet Length (word 2) |
227 | TXDESC_LEN_MASK = 0x0000ffff |
||
228 | |||
229 | ; TX Descriptor CMD field (word 2) |
||
230 | TXDESC_IDE = 0x80000000 ; Interrupt Delay Enable |
||
231 | TXDESC_VLE = 0x40000000 ; VLAN Packet Enable |
||
232 | TXDESC_DEXT = 0x20000000 ; Extension |
||
233 | TXDESC_RPS = 0x10000000 ; Report Packet Sent |
||
234 | TXDESC_RS = 0x08000000 ; Report Status |
||
235 | TXDESC_IC = 0x04000000 ; Insert Checksum |
||
236 | TXDESC_IFCS = 0x02000000 ; Insert FCS |
||
237 | TXDESC_EOP = 0x01000000 ; End Of Packet |
||
238 | |||
239 | ; TX Descriptor STA field (word 3) |
||
240 | TXDESC_TU = 0x00000008 ; Transmit Underrun |
||
241 | TXDESC_LC = 0x00000004 ; Late Collision |
||
242 | TXDESC_EC = 0x00000002 ; Excess Collisions |
||
243 | TXDESC_DD = 0x00000001 ; Descriptor Done |
||
244 | |||
245 | |||
4519 | hidnplayr | 246 | |
247 | ; === RX Descriptor === |
||
248 | |||
249 | struct RDESC |
||
250 | addr_l dd ? |
||
251 | addr_h dd ? |
||
252 | status_l dd ? |
||
253 | status_h dd ? |
||
254 | ends |
||
255 | |||
3545 | hidnplayr | 256 | ; RX Packet Length (word 2) |
257 | RXDESC_LEN_MASK = 0x0000ffff |
||
258 | |||
259 | ; RX Descriptor STA field (word 3) |
||
260 | RXDESC_PIF = 0x00000080 ; Passed In-exact Filter |
||
261 | RXDESC_IPCS = 0x00000040 ; IP cksum calculated |
||
262 | RXDESC_TCPCS = 0x00000020 ; TCP cksum calculated |
||
263 | RXDESC_VP = 0x00000008 ; Packet is 802.1Q |
||
264 | RXDESC_IXSM = 0x00000004 ; Ignore cksum indication |
||
265 | RXDESC_EOP = 0x00000002 ; End Of Packet |
||
266 | RXDESC_DD = 0x00000001 ; Descriptor Done |
||
267 | |||
4522 | hidnplayr | 268 | struct device ETH_DEVICE |
3545 | hidnplayr | 269 | |
4522 | hidnplayr | 270 | mmio_addr dd ? |
271 | pci_bus dd ? |
||
272 | pci_dev dd ? |
||
273 | irq_line db ? |
||
3545 | hidnplayr | 274 | |
4522 | hidnplayr | 275 | cur_rx dd ? |
276 | cur_tx dd ? |
||
277 | last_tx dd ? |
||
3545 | hidnplayr | 278 | |
4522 | hidnplayr | 279 | rb 0x100 - ($ and 0xff) ; align 256 |
280 | rx_desc rb RX_RING_SIZE*sizeof.RDESC*2 |
||
3545 | hidnplayr | 281 | |
4522 | hidnplayr | 282 | rb 0x100 - ($ and 0xff) ; align 256 |
283 | tx_desc rb TX_RING_SIZE*sizeof.TDESC*2 |
||
3545 | hidnplayr | 284 | |
4522 | hidnplayr | 285 | ends |
4512 | hidnplayr | 286 | |
3545 | hidnplayr | 287 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
288 | ;; ;; |
||
289 | ;; proc START ;; |
||
290 | ;; ;; |
||
291 | ;; (standard driver proc) ;; |
||
292 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
||
293 | |||
4524 | hidnplayr | 294 | proc START c, reason:dword, cmdline:dword |
3545 | hidnplayr | 295 | |
4522 | hidnplayr | 296 | cmp [reason], DRV_ENTRY |
297 | jne .fail |
||
3545 | hidnplayr | 298 | |
3855 | hidnplayr | 299 | DEBUGF 1,"Loading driver\n" |
4522 | hidnplayr | 300 | invoke RegService, my_service, service_proc |
3545 | hidnplayr | 301 | ret |
302 | |||
303 | .fail: |
||
4522 | hidnplayr | 304 | xor eax, eax |
3545 | hidnplayr | 305 | ret |
306 | |||
307 | endp |
||
308 | |||
309 | |||
310 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
||
311 | ;; ;; |
||
312 | ;; proc SERVICE_PROC ;; |
||
313 | ;; ;; |
||
314 | ;; (standard driver proc) ;; |
||
315 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
||
316 | |||
317 | align 4 |
||
318 | proc service_proc stdcall, ioctl:dword |
||
319 | |||
320 | mov edx, [ioctl] |
||
4470 | hidnplayr | 321 | mov eax, [edx + IOCTL.io_code] |
3545 | hidnplayr | 322 | |
323 | ;------------------------------------------------------ |
||
324 | |||
325 | cmp eax, 0 ;SRV_GETVERSION |
||
326 | jne @F |
||
327 | |||
4470 | hidnplayr | 328 | cmp [edx + IOCTL.out_size], 4 |
3545 | hidnplayr | 329 | jb .fail |
4470 | hidnplayr | 330 | mov eax, [edx + IOCTL.output] |
4522 | hidnplayr | 331 | mov dword[eax], API_VERSION |
3545 | hidnplayr | 332 | |
333 | xor eax, eax |
||
334 | ret |
||
335 | |||
336 | ;------------------------------------------------------ |
||
337 | @@: |
||
338 | cmp eax, 1 ;SRV_HOOK |
||
339 | jne .fail |
||
340 | |||
4522 | hidnplayr | 341 | cmp [edx + IOCTL.inp_size], 3 ; Data input must be at least 3 bytes |
3545 | hidnplayr | 342 | jb .fail |
343 | |||
4470 | hidnplayr | 344 | mov eax, [edx + IOCTL.input] |
4524 | hidnplayr | 345 | cmp byte[eax], 1 ; 1 means device number and bus number (pci) are given |
3545 | hidnplayr | 346 | jne .fail ; other types arent supported for this card yet |
347 | |||
348 | ; check if the device is already listed |
||
349 | |||
350 | mov esi, device_list |
||
351 | mov ecx, [devices] |
||
352 | test ecx, ecx |
||
353 | jz .firstdevice |
||
354 | |||
4522 | hidnplayr | 355 | ; mov eax, [edx + IOCTL.input] ; get the pci bus and device numbers |
3545 | hidnplayr | 356 | mov ax, [eax+1] ; |
357 | .nextdevice: |
||
358 | mov ebx, [esi] |
||
4522 | hidnplayr | 359 | cmp al, byte[ebx + device.pci_bus] |
3545 | hidnplayr | 360 | jne .next |
4522 | hidnplayr | 361 | cmp ah, byte[ebx + device.pci_dev] |
3545 | hidnplayr | 362 | je .find_devicenum ; Device is already loaded, let's find it's device number |
363 | .next: |
||
364 | add esi, 4 |
||
365 | loop .nextdevice |
||
366 | |||
367 | |||
368 | ; This device doesnt have its own eth_device structure yet, lets create one |
||
369 | .firstdevice: |
||
370 | cmp [devices], MAX_DEVICES ; First check if the driver can handle one more card |
||
371 | jae .fail |
||
372 | |||
4522 | hidnplayr | 373 | allocate_and_clear ebx, sizeof.device, .fail ; Allocate the buffer for device structure |
3545 | hidnplayr | 374 | |
375 | ; Fill in the direct call addresses into the struct |
||
376 | |||
4522 | hidnplayr | 377 | mov [ebx + device.reset], reset |
378 | mov [ebx + device.transmit], transmit |
||
379 | mov [ebx + device.unload], unload |
||
380 | mov [ebx + device.name], my_service |
||
3545 | hidnplayr | 381 | |
382 | ; save the pci bus and device numbers |
||
383 | |||
4470 | hidnplayr | 384 | mov eax, [edx + IOCTL.input] |
4524 | hidnplayr | 385 | movzx ecx, byte[eax+1] |
4522 | hidnplayr | 386 | mov [ebx + device.pci_bus], ecx |
4524 | hidnplayr | 387 | movzx ecx, byte[eax+2] |
4522 | hidnplayr | 388 | mov [ebx + device.pci_dev], ecx |
3545 | hidnplayr | 389 | |
390 | ; Now, it's time to find the base mmio addres of the PCI device |
||
391 | |||
4522 | hidnplayr | 392 | stdcall PCI_find_mmio32, [ebx + device.pci_bus], [ebx + device.pci_dev] ; returns in eax |
3545 | hidnplayr | 393 | |
394 | ; Create virtual mapping of the physical memory |
||
395 | |||
4522 | hidnplayr | 396 | invoke MapIoMem, eax, 10000h, PG_SW+PG_NOCACHE |
397 | mov [ebx + device.mmio_addr], eax |
||
3545 | hidnplayr | 398 | |
399 | ; We've found the mmio address, find IRQ now |
||
400 | |||
4522 | hidnplayr | 401 | invoke PciRead8, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.interrupt_line |
402 | mov [ebx + device.irq_line], al |
||
3545 | hidnplayr | 403 | |
404 | DEBUGF 1,"Hooking into device, dev:%x, bus:%x, irq:%x, addr:%x\n",\ |
||
4522 | hidnplayr | 405 | [ebx + device.pci_dev]:1,[ebx + device.pci_bus]:1,[ebx + device.irq_line]:1,[ebx + device.mmio_addr]:8 |
3545 | hidnplayr | 406 | |
407 | ; Ok, the eth_device structure is ready, let's probe the device |
||
4522 | hidnplayr | 408 | call probe ; this function will output in eax |
3545 | hidnplayr | 409 | test eax, eax |
4522 | hidnplayr | 410 | jnz .err ; If an error occured, exit |
3545 | hidnplayr | 411 | |
4522 | hidnplayr | 412 | mov eax, [devices] ; Add the device structure to our device list |
413 | mov [device_list+4*eax], ebx ; (IRQ handler uses this list to find device) |
||
414 | inc [devices] ; |
||
3545 | hidnplayr | 415 | |
416 | call start_i8254x |
||
5156 | hidnplayr | 417 | test eax, eax |
418 | jnz .destroy |
||
3545 | hidnplayr | 419 | |
4522 | hidnplayr | 420 | mov [ebx + device.type], NET_TYPE_ETH |
421 | invoke NetRegDev |
||
3545 | hidnplayr | 422 | cmp eax, -1 |
423 | je .destroy |
||
424 | |||
425 | ret |
||
426 | |||
427 | ; If the device was already loaded, find the device number and return it in eax |
||
428 | |||
429 | .find_devicenum: |
||
430 | DEBUGF 1,"Trying to find device number of already registered device\n" |
||
4522 | hidnplayr | 431 | invoke NetPtrToNum ; This kernel procedure converts a pointer to device struct in ebx |
432 | ; into a device number in edi |
||
433 | mov eax, edi ; Application wants it in eax instead |
||
3545 | hidnplayr | 434 | DEBUGF 1,"Kernel says: %u\n", eax |
435 | ret |
||
436 | |||
437 | ; If an error occured, remove all allocated data and exit (returning -1 in eax) |
||
438 | |||
439 | .destroy: |
||
440 | ; todo: reset device into virgin state |
||
441 | |||
442 | .err: |
||
4522 | hidnplayr | 443 | invoke KernelFree, ebx |
3545 | hidnplayr | 444 | |
445 | .fail: |
||
5156 | hidnplayr | 446 | DEBUGF 2,"Loading driver failed\n" |
3545 | hidnplayr | 447 | or eax, -1 |
448 | ret |
||
449 | |||
450 | ;------------------------------------------------------ |
||
451 | endp |
||
452 | |||
453 | |||
454 | ;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;; |
||
455 | ;; ;; |
||
456 | ;; Actual Hardware dependent code starts here ;; |
||
457 | ;; ;; |
||
458 | ;;/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\;; |
||
459 | |||
460 | |||
461 | align 4 |
||
462 | unload: |
||
5156 | hidnplayr | 463 | |
464 | DEBUGF 1,"Unload\n" |
||
465 | |||
3545 | hidnplayr | 466 | ; TODO: (in this particular order) |
467 | ; |
||
468 | ; - Stop the device |
||
469 | ; - Detach int handler |
||
470 | ; - Remove device from local list (device_list) |
||
471 | ; - call unregister function in kernel |
||
472 | ; - Remove all allocated structures and buffers the card used |
||
473 | |||
474 | or eax, -1 |
||
475 | |||
5156 | hidnplayr | 476 | ret |
3545 | hidnplayr | 477 | |
478 | |||
479 | |||
480 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
||
481 | ;; |
||
482 | ;; probe: enables the device (if it really is I8254X) |
||
483 | ;; |
||
484 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
||
485 | align 4 |
||
486 | probe: |
||
487 | |||
488 | DEBUGF 1,"Probe\n" |
||
489 | |||
4522 | hidnplayr | 490 | ; Make the device a bus master |
491 | invoke PciRead32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command |
||
492 | or al, PCI_CMD_MASTER |
||
493 | invoke PciWrite32, [ebx + device.pci_bus], [ebx + device.pci_dev], PCI_header00.command, eax |
||
3545 | hidnplayr | 494 | |
495 | ; TODO: validate the device |
||
496 | |||
497 | call read_mac |
||
498 | |||
4522 | hidnplayr | 499 | movzx eax, [ebx + device.irq_line] |
3545 | hidnplayr | 500 | DEBUGF 1,"Attaching int handler to irq %x\n", eax:1 |
4522 | hidnplayr | 501 | invoke AttachIntHandler, eax, int_handler, ebx |
3545 | hidnplayr | 502 | test eax, eax |
503 | jnz @f |
||
3855 | hidnplayr | 504 | DEBUGF 2,"Could not attach int handler!\n" |
4519 | hidnplayr | 505 | or eax, -1 |
506 | ret |
||
3545 | hidnplayr | 507 | @@: |
508 | |||
509 | |||
510 | reset_dontstart: |
||
511 | DEBUGF 1,"Reset\n" |
||
512 | |||
4522 | hidnplayr | 513 | mov esi, [ebx + device.mmio_addr] |
3545 | hidnplayr | 514 | |
4512 | hidnplayr | 515 | or dword[esi + REG_CTRL], CTRL_RST ; reset device |
3545 | hidnplayr | 516 | .loop: |
517 | push esi |
||
518 | xor esi, esi |
||
519 | inc esi |
||
4522 | hidnplayr | 520 | invoke Sleep |
3545 | hidnplayr | 521 | pop esi |
4512 | hidnplayr | 522 | test dword[esi + REG_CTRL], CTRL_RST |
3545 | hidnplayr | 523 | jnz .loop |
524 | |||
4519 | hidnplayr | 525 | mov dword[esi + REG_IMC], 0xffffffff ; Disable all interrupt causes |
3545 | hidnplayr | 526 | mov eax, dword [esi + REG_ICR] ; Clear any pending interrupts |
4519 | hidnplayr | 527 | mov dword[esi + REG_ITR], 0 ; Disable interrupt throttling logic |
3545 | hidnplayr | 528 | |
4519 | hidnplayr | 529 | mov dword[esi + REG_PBA], 0x00000004 ; PBA: set the RX buffer size to 4KB (TX buffer is calculated as 64-RX buffer) |
530 | mov dword[esi + REG_RDTR], 0 ; RDTR: set no delay |
||
3545 | hidnplayr | 531 | |
5140 | hidnplayr | 532 | mov dword[esi + REG_TXCW], 0x80008060 ; TXCW: set ANE, TxConfigWord (Half/Full duplex, Next Page Reqest) |
3545 | hidnplayr | 533 | |
534 | mov eax, [esi + REG_CTRL] |
||
535 | or eax, 1 shl 6 + 1 shl 5 |
||
536 | and eax, not (1 shl 3 + 1 shl 7 + 1 shl 30 + 1 shl 31) |
||
537 | mov dword [esi + REG_CTRL], eax ; CTRL: clear LRST, set SLU and ASDE, clear RSTPHY, VME, and ILOS |
||
538 | |||
539 | lea edi, [esi + 0x5200] ; MTA: reset |
||
540 | mov eax, 0xffffffff |
||
541 | stosd |
||
542 | stosd |
||
543 | stosd |
||
544 | stosd |
||
545 | |||
4512 | hidnplayr | 546 | call init_rx |
5156 | hidnplayr | 547 | test eax, eax |
548 | jnz .fail |
||
4512 | hidnplayr | 549 | call init_tx |
550 | |||
551 | xor eax, eax |
||
5156 | hidnplayr | 552 | .fail: |
4512 | hidnplayr | 553 | ret |
554 | |||
555 | |||
556 | |||
557 | align 4 |
||
558 | init_rx: |
||
559 | |||
4522 | hidnplayr | 560 | lea edi, [ebx + device.rx_desc] |
4512 | hidnplayr | 561 | mov ecx, RX_RING_SIZE |
562 | .loop: |
||
5156 | hidnplayr | 563 | push ecx edi |
4522 | hidnplayr | 564 | invoke KernelAlloc, MAX_PKT_SIZE |
5156 | hidnplayr | 565 | test eax, eax |
566 | jz .out_of_mem |
||
4512 | hidnplayr | 567 | DEBUGF 1,"RX buffer: 0x%x\n", eax |
568 | pop edi |
||
4519 | hidnplayr | 569 | mov dword[edi + RX_RING_SIZE*sizeof.RDESC], eax |
4512 | hidnplayr | 570 | push edi |
4522 | hidnplayr | 571 | invoke GetPhysAddr |
4512 | hidnplayr | 572 | pop edi |
4519 | hidnplayr | 573 | mov [edi + RDESC.addr_l], eax |
574 | mov [edi + RDESC.addr_h], 0 |
||
575 | mov [edi + RDESC.status_l], 0 |
||
576 | mov [edi + RDESC.status_h], 0 |
||
577 | add edi, sizeof.RDESC |
||
4512 | hidnplayr | 578 | pop ecx |
579 | dec ecx |
||
580 | jnz .loop |
||
3545 | hidnplayr | 581 | |
4522 | hidnplayr | 582 | mov [ebx + device.cur_rx], 0 |
4512 | hidnplayr | 583 | |
4522 | hidnplayr | 584 | lea eax, [ebx + device.rx_desc] |
585 | invoke GetPhysAddr |
||
4519 | hidnplayr | 586 | mov dword[esi + REG_RDBAL], eax ; Receive Descriptor Base Address Low |
587 | mov dword[esi + REG_RDBAH], 0 ; Receive Descriptor Base Address High |
||
588 | mov dword[esi + REG_RDLEN], RX_RING_SIZE*sizeof.RDESC ; Receive Descriptor Length |
||
589 | mov dword[esi + REG_RDH], 0 ; Receive Descriptor Head |
||
590 | mov dword[esi + REG_RDT], RX_RING_SIZE-1 ; Receive Descriptor Tail |
||
4512 | hidnplayr | 591 | mov dword[esi + REG_RCTL], RCTL_SBP or RCTL_BAM or RCTL_SECRC or RCTL_UPE or RCTL_MPE |
592 | ; Store Bad Packets, Broadcast Accept Mode, Strip Ethernet CRC from incoming packet, Promiscuous mode |
||
5156 | hidnplayr | 593 | xor eax, eax ; success! |
594 | ret |
||
3545 | hidnplayr | 595 | |
5156 | hidnplayr | 596 | .out_of_mem: |
597 | DEBUGF 2,"Out of memory!\n" |
||
598 | pop edi ecx |
||
599 | or eax, -1 ; error! |
||
4512 | hidnplayr | 600 | ret |
3545 | hidnplayr | 601 | |
4512 | hidnplayr | 602 | |
603 | |||
604 | align 4 |
||
605 | init_tx: |
||
606 | |||
4522 | hidnplayr | 607 | lea edi, [ebx + device.tx_desc] |
4519 | hidnplayr | 608 | mov ecx, TX_RING_SIZE |
609 | .loop: |
||
610 | mov [edi + TDESC.addr_l], eax |
||
611 | mov [edi + TDESC.addr_h], 0 |
||
612 | mov [edi + TDESC.length_cso_cmd], 0 |
||
613 | mov [edi + TDESC.status], 0 |
||
614 | add edi, sizeof.TDESC |
||
615 | dec ecx |
||
616 | jnz .loop |
||
4512 | hidnplayr | 617 | |
4522 | hidnplayr | 618 | mov [ebx + device.cur_tx], 0 |
619 | mov [ebx + device.last_tx], 0 |
||
4519 | hidnplayr | 620 | |
4522 | hidnplayr | 621 | lea eax, [ebx + device.tx_desc] |
622 | invoke GetPhysAddr |
||
4519 | hidnplayr | 623 | mov dword[esi + REG_TDBAL], eax ; Transmit Descriptor Base Address Low |
624 | mov dword[esi + REG_TDBAH], 0 ; Transmit Descriptor Base Address High |
||
625 | mov dword[esi + REG_TDLEN], RX_RING_SIZE*sizeof.TDESC ; Transmit Descriptor Length |
||
626 | mov dword[esi + REG_TDH], 0 ; Transmit Descriptor Head |
||
627 | mov dword[esi + REG_TDT], 0 ; Transmit Descriptor Tail |
||
628 | mov dword[esi + REG_TCTL], 0x010400fa ; Enabled, Pad Short Packets, 15 retrys, 64-byte COLD, Re-transmit on Late Collision |
||
629 | mov dword[esi + REG_TIPG], 0x0060200A ; IPGT 10, IPGR1 8, IPGR2 6 |
||
3545 | hidnplayr | 630 | |
631 | ret |
||
632 | |||
4512 | hidnplayr | 633 | |
3545 | hidnplayr | 634 | align 4 |
635 | reset: |
||
636 | call reset_dontstart |
||
5156 | hidnplayr | 637 | test eax, eax |
638 | je start_i8254x |
||
3545 | hidnplayr | 639 | |
5156 | hidnplayr | 640 | ret |
641 | |||
642 | align 4 |
||
3545 | hidnplayr | 643 | start_i8254x: |
644 | |||
4522 | hidnplayr | 645 | mov esi, [ebx + device.mmio_addr] |
4519 | hidnplayr | 646 | or dword[esi + REG_RCTL], RCTL_EN ; Enable the receiver |
4512 | hidnplayr | 647 | |
3545 | hidnplayr | 648 | xor eax, eax |
649 | mov [esi + REG_RDTR], eax ; Clear the Receive Delay Timer Register |
||
650 | mov [esi + REG_RADV], eax ; Clear the Receive Interrupt Absolute Delay Timer |
||
651 | mov [esi + REG_RSRPD], eax ; Clear the Receive Small Packet Detect Interrupt |
||
652 | |||
4512 | hidnplayr | 653 | mov dword[esi + REG_IMS], 0x1F6DC ; Enable interrupt types |
654 | mov eax, [esi + REG_ICR] ; Clear pending interrupts |
||
655 | |||
4522 | hidnplayr | 656 | mov [ebx + device.mtu], 1514 |
4580 | hidnplayr | 657 | mov [ebx + device.state], ETH_LINK_UNKNOWN ; Set link state to unknown |
3545 | hidnplayr | 658 | |
659 | xor eax, eax |
||
660 | ret |
||
661 | |||
662 | |||
663 | |||
664 | |||
665 | align 4 |
||
666 | read_mac: |
||
667 | |||
668 | DEBUGF 1,"Read MAC\n" |
||
669 | |||
4522 | hidnplayr | 670 | mov esi, [ebx + device.mmio_addr] |
3545 | hidnplayr | 671 | |
672 | mov eax, [esi+0x5400] ; RAL |
||
673 | test eax, eax |
||
674 | jz .try_eeprom |
||
675 | |||
4522 | hidnplayr | 676 | mov dword[ebx + device.mac], eax |
3545 | hidnplayr | 677 | mov eax, [esi+0x5404] ; RAH |
4522 | hidnplayr | 678 | mov word[ebx + device.mac+4], ax |
3545 | hidnplayr | 679 | |
680 | jmp .mac_ok |
||
681 | |||
682 | .try_eeprom: |
||
4519 | hidnplayr | 683 | mov dword[esi+0x14], 0x00000001 |
3545 | hidnplayr | 684 | mov eax, [esi+0x14] |
685 | shr eax, 16 |
||
4522 | hidnplayr | 686 | mov word[ebx + device.mac], ax |
3545 | hidnplayr | 687 | |
4519 | hidnplayr | 688 | mov dword[esi+0x14], 0x00000101 |
3545 | hidnplayr | 689 | mov eax, [esi+0x14] |
690 | shr eax, 16 |
||
4522 | hidnplayr | 691 | mov word[ebx + device.mac+2], ax |
3545 | hidnplayr | 692 | |
4519 | hidnplayr | 693 | mov dword[esi+0x14], 0x00000201 |
3545 | hidnplayr | 694 | mov eax, [esi+0x14] |
695 | shr eax, 16 |
||
4522 | hidnplayr | 696 | mov word[ebx + device.mac+4], ax |
3545 | hidnplayr | 697 | |
698 | .mac_ok: |
||
699 | DEBUGF 1,"MAC = %x-%x-%x-%x-%x-%x\n",\ |
||
4522 | hidnplayr | 700 | [ebx + device.mac+0]:2,[ebx + device.mac+1]:2,[ebx + device.mac+2]:2,\ |
701 | [ebx + device.mac+3]:2,[ebx + device.mac+4]:2,[ebx + device.mac+5]:2 |
||
3545 | hidnplayr | 702 | |
703 | ret |
||
704 | |||
705 | |||
706 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
||
707 | ;; ;; |
||
708 | ;; Transmit ;; |
||
709 | ;; ;; |
||
4512 | hidnplayr | 710 | ;; In: pointer to device structure in ebx ;; |
3545 | hidnplayr | 711 | ;; ;; |
712 | ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; |
||
4512 | hidnplayr | 713 | |
714 | proc transmit stdcall bufferptr, buffersize |
||
715 | |||
4519 | hidnplayr | 716 | pushf |
717 | cli |
||
718 | |||
4512 | hidnplayr | 719 | DEBUGF 1,"Transmitting packet, buffer:%x, size:%u\n", [bufferptr], [buffersize] |
720 | mov eax, [bufferptr] |
||
3788 | hidnplayr | 721 | DEBUGF 1,"To: %x-%x-%x-%x-%x-%x From: %x-%x-%x-%x-%x-%x Type:%x%x\n",\ |
3545 | hidnplayr | 722 | [eax+00]:2,[eax+01]:2,[eax+02]:2,[eax+03]:2,[eax+04]:2,[eax+05]:2,\ |
723 | [eax+06]:2,[eax+07]:2,[eax+08]:2,[eax+09]:2,[eax+10]:2,[eax+11]:2,\ |
||
724 | [eax+13]:2,[eax+12]:2 |
||
725 | |||
4512 | hidnplayr | 726 | cmp [buffersize], 1514 |
3545 | hidnplayr | 727 | ja .fail |
4512 | hidnplayr | 728 | cmp [buffersize], 60 |
3545 | hidnplayr | 729 | jb .fail |
730 | |||
731 | ; Program the descriptor (use legacy mode) |
||
4522 | hidnplayr | 732 | mov edi, [ebx + device.cur_tx] |
4519 | hidnplayr | 733 | DEBUGF 1, "Using TX desc: %u\n", edi |
734 | shl edi, 4 ; edi = edi * sizeof.TDESC |
||
4522 | hidnplayr | 735 | lea edi, [ebx + device.tx_desc + edi] |
4519 | hidnplayr | 736 | mov dword[edi + TX_RING_SIZE*sizeof.TDESC], eax ; Store the data location (for driver) |
4522 | hidnplayr | 737 | invoke GetPhysAddr |
4519 | hidnplayr | 738 | mov [edi + TDESC.addr_l], eax ; Data location (for hardware) |
739 | mov [edi + TDESC.addr_h], 0 |
||
3545 | hidnplayr | 740 | |
4512 | hidnplayr | 741 | mov ecx, [buffersize] |
4519 | hidnplayr | 742 | or ecx, TXDESC_EOP + TXDESC_IFCS + TXDESC_RS |
743 | mov [edi + TDESC.length_cso_cmd], ecx |
||
744 | mov [edi + TDESC.status], 0 |
||
3545 | hidnplayr | 745 | |
4522 | hidnplayr | 746 | ; Tell i8254x wich descriptor(s) we programmed, by moving the tail |
747 | mov edi, [ebx + device.mmio_addr] |
||
748 | mov eax, [ebx + device.cur_tx] |
||
4519 | hidnplayr | 749 | inc eax |
750 | and eax, TX_RING_SIZE-1 |
||
4522 | hidnplayr | 751 | mov [ebx + device.cur_tx], eax |
4519 | hidnplayr | 752 | mov dword[edi + REG_TDT], eax ; TDT - Transmit Descriptor Tail |
3545 | hidnplayr | 753 | |
754 | ; Update stats |
||
4522 | hidnplayr | 755 | inc [ebx + device.packets_tx] |
4512 | hidnplayr | 756 | mov eax, [buffersize] |
4522 | hidnplayr | 757 | add dword[ebx + device.bytes_tx], eax |
758 | adc dword[ebx + device.bytes_tx + 4], 0 |
||
3545 | hidnplayr | 759 | |
5140 | hidnplayr | 760 | call clean_tx |
761 | |||
4521 | hidnplayr | 762 | popf |
4334 | hidnplayr | 763 | xor eax, eax |
4512 | hidnplayr | 764 | ret |
3545 | hidnplayr | 765 | |
766 | .fail: |
||
5140 | hidnplayr | 767 | call clean_tx |
768 | |||
3788 | hidnplayr | 769 | DEBUGF 2,"Send failed\n" |
4522 | hidnplayr | 770 | invoke KernelFree, [bufferptr] |
4521 | hidnplayr | 771 | popf |
4334 | hidnplayr | 772 | or eax, -1 |
4512 | hidnplayr | 773 | ret |
3545 | hidnplayr | 774 | |
4512 | hidnplayr | 775 | endp |
3545 | hidnplayr | 776 | |
4512 | hidnplayr | 777 | |
3545 | hidnplayr | 778 | ;;;;;;;;;;;;;;;;;;;;;;; |
779 | ;; ;; |
||
780 | ;; Interrupt handler ;; |
||
781 | ;; ;; |
||
782 | ;;;;;;;;;;;;;;;;;;;;;;; |
||
783 | |||
784 | align 4 |
||
785 | int_handler: |
||
786 | |||
787 | push ebx esi edi |
||
788 | |||
3855 | hidnplayr | 789 | DEBUGF 1,"INT\n" |
3545 | hidnplayr | 790 | ;------------------------------------------- |
791 | ; Find pointer of device wich made IRQ occur |
||
792 | |||
793 | mov ecx, [devices] |
||
794 | test ecx, ecx |
||
795 | jz .nothing |
||
796 | mov esi, device_list |
||
797 | .nextdevice: |
||
798 | mov ebx, [esi] |
||
4522 | hidnplayr | 799 | mov edi, [ebx + device.mmio_addr] |
3545 | hidnplayr | 800 | mov eax, [edi + REG_ICR] |
801 | test eax, eax |
||
802 | jnz .got_it |
||
803 | .continue: |
||
804 | add esi, 4 |
||
805 | dec ecx |
||
806 | jnz .nextdevice |
||
807 | .nothing: |
||
808 | pop edi esi ebx |
||
809 | xor eax, eax |
||
810 | |||
811 | ret |
||
812 | |||
813 | .got_it: |
||
4512 | hidnplayr | 814 | DEBUGF 1,"Device: %x Status: %x\n", ebx, eax |
3545 | hidnplayr | 815 | |
816 | ;--------- |
||
817 | ; RX done? |
||
818 | |||
4512 | hidnplayr | 819 | test eax, ICR_RXDMT0 + ICR_RXT0 |
3545 | hidnplayr | 820 | jz .no_rx |
821 | |||
822 | push eax ebx |
||
4512 | hidnplayr | 823 | .retaddr: |
824 | pop ebx eax |
||
3545 | hidnplayr | 825 | ; Get last descriptor addr |
4522 | hidnplayr | 826 | mov esi, [ebx + device.cur_rx] |
4519 | hidnplayr | 827 | shl esi, 4 ; esi = esi * sizeof.RDESC |
4522 | hidnplayr | 828 | lea esi, [ebx + device.rx_desc + esi] |
4519 | hidnplayr | 829 | cmp byte[esi + RDESC.status_h], 0 ; Check status field |
4512 | hidnplayr | 830 | je .no_rx |
3545 | hidnplayr | 831 | |
4512 | hidnplayr | 832 | push eax ebx |
833 | push .retaddr |
||
834 | movzx ecx, word[esi + 8] ; Get the packet length |
||
3788 | hidnplayr | 835 | DEBUGF 1,"got %u bytes\n", ecx |
3545 | hidnplayr | 836 | push ecx |
4519 | hidnplayr | 837 | push dword[esi + RX_RING_SIZE*sizeof.RDESC] ; Get packet pointer |
3545 | hidnplayr | 838 | |
839 | ; Update stats |
||
4522 | hidnplayr | 840 | add dword[ebx + device.bytes_rx], ecx |
841 | adc dword[ebx + device.bytes_rx + 4], 0 |
||
842 | inc [ebx + device.packets_rx] |
||
3545 | hidnplayr | 843 | |
4512 | hidnplayr | 844 | ; Allocate new descriptor |
845 | push esi |
||
4522 | hidnplayr | 846 | invoke KernelAlloc, MAX_PKT_SIZE |
4512 | hidnplayr | 847 | pop esi |
5156 | hidnplayr | 848 | test eax, eax |
849 | jz .out_of_mem |
||
4519 | hidnplayr | 850 | mov dword[esi + RX_RING_SIZE*sizeof.RDESC], eax |
4522 | hidnplayr | 851 | invoke GetPhysAddr |
4519 | hidnplayr | 852 | mov [esi + RDESC.addr_l], eax |
853 | mov [esi + RDESC.status_l], 0 |
||
854 | mov [esi + RDESC.status_h], 0 |
||
3545 | hidnplayr | 855 | |
4512 | hidnplayr | 856 | ; Move the receive descriptor tail |
4522 | hidnplayr | 857 | mov esi, [ebx + device.mmio_addr] |
858 | mov eax, [ebx + device.cur_rx] |
||
4512 | hidnplayr | 859 | mov [esi + REG_RDT], eax |
3545 | hidnplayr | 860 | |
4512 | hidnplayr | 861 | ; Move to next rx desc |
4522 | hidnplayr | 862 | inc [ebx + device.cur_rx] |
863 | and [ebx + device.cur_rx], RX_RING_SIZE-1 |
||
4512 | hidnplayr | 864 | |
4522 | hidnplayr | 865 | jmp [Eth_input] |
5156 | hidnplayr | 866 | |
867 | .out_of_mem: |
||
868 | DEBUGF 2,"Out of memory!\n" |
||
869 | |||
870 | ; Move to next rx desc |
||
871 | inc [ebx + device.cur_rx] |
||
872 | and [ebx + device.cur_rx], RX_RING_SIZE-1 |
||
873 | |||
874 | jmp [Eth_input] |
||
3545 | hidnplayr | 875 | .no_rx: |
876 | |||
877 | ;-------------- |
||
878 | ; Link Changed? |
||
879 | |||
880 | test eax, ICR_LSC |
||
881 | jz .no_link |
||
882 | |||
4512 | hidnplayr | 883 | DEBUGF 2,"Link Changed\n" |
3545 | hidnplayr | 884 | |
885 | .no_link: |
||
886 | |||
887 | ;--------------- |
||
888 | ; Transmit done? |
||
889 | |||
890 | test eax, ICR_TXDW |
||
891 | jz .no_tx |
||
892 | |||
3788 | hidnplayr | 893 | DEBUGF 1,"Transmit done\n" |
3545 | hidnplayr | 894 | |
5140 | hidnplayr | 895 | ; call clean_tx |
896 | |||
897 | .no_tx: |
||
898 | pop edi esi ebx |
||
899 | xor eax, eax |
||
900 | inc eax |
||
901 | ret |
||
902 | |||
903 | |||
904 | |||
905 | clean_tx: |
||
906 | |||
4519 | hidnplayr | 907 | .txdesc_loop: |
4522 | hidnplayr | 908 | mov edi, [ebx + device.last_tx] |
4519 | hidnplayr | 909 | shl edi, 4 ; edi = edi * sizeof.TDESC |
4522 | hidnplayr | 910 | lea edi, [ebx + device.tx_desc + edi] |
4519 | hidnplayr | 911 | test [edi + TDESC.status], TXDESC_DD ; Descriptor done? |
912 | jz .no_tx |
||
913 | cmp dword[edi + TX_RING_SIZE*sizeof.TDESC], 0 |
||
914 | je .no_tx |
||
915 | |||
916 | DEBUGF 1,"Cleaning up TX desc: 0x%x\n", edi |
||
917 | |||
918 | push ebx |
||
919 | push dword[edi + TX_RING_SIZE*sizeof.TDESC] |
||
920 | mov dword[edi + TX_RING_SIZE*sizeof.TDESC], 0 |
||
4522 | hidnplayr | 921 | invoke KernelFree |
4519 | hidnplayr | 922 | pop ebx |
3545 | hidnplayr | 923 | |
4522 | hidnplayr | 924 | inc [ebx + device.last_tx] |
925 | and [ebx + device.last_tx], TX_RING_SIZE-1 |
||
4519 | hidnplayr | 926 | jmp .txdesc_loop |
927 | |||
3545 | hidnplayr | 928 | .no_tx: |
5140 | hidnplayr | 929 | |
3545 | hidnplayr | 930 | ret |
931 | |||
932 | |||
933 | |||
934 | |||
935 | ; End of code |
||
936 | |||
4524 | hidnplayr | 937 | data fixups |
938 | end data |
||
939 | |||
4522 | hidnplayr | 940 | include '../peimport.inc' |
941 | |||
942 | include_debug_strings |
||
943 | my_service db 'I8254X', 0 ; max 16 chars include zero |
||
944 | |||
3545 | hidnplayr | 945 | align 4 |
946 | devices dd 0 |
||
4522 | hidnplayr | 947 | device_list rd MAX_DEVICES ; This list contains all pointers to device structures the driver is handling |
3545 | hidnplayr | 948 |