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5221 | serge | 1 | /* Declarations for Intel 80386 opcode table |
2 | Copyright 2007, 2008, 2009, 2010, 2012 |
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3 | Free Software Foundation, Inc. |
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4 | |||
5 | This file is part of the GNU opcodes library. |
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6 | |||
7 | This library is free software; you can redistribute it and/or modify |
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8 | it under the terms of the GNU General Public License as published by |
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9 | the Free Software Foundation; either version 3, or (at your option) |
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10 | any later version. |
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11 | |||
12 | It is distributed in the hope that it will be useful, but WITHOUT |
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13 | ANY WARRANTY; without even the implied warranty of MERCHANTABILITY |
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14 | or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public |
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15 | License for more details. |
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16 | |||
17 | You should have received a copy of the GNU General Public License |
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18 | along with GAS; see the file COPYING. If not, write to the Free |
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19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA |
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20 | 02110-1301, USA. */ |
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21 | |||
22 | #include "opcode/i386.h" |
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23 | #ifdef HAVE_LIMITS_H |
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24 | #include |
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25 | #endif |
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26 | |||
27 | #ifndef CHAR_BIT |
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28 | #define CHAR_BIT 8 |
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29 | #endif |
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30 | |||
31 | /* Position of cpu flags bitfiled. */ |
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32 | |||
33 | enum |
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34 | { |
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35 | /* i186 or better required */ |
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36 | Cpu186 = 0, |
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37 | /* i286 or better required */ |
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38 | Cpu286, |
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39 | /* i386 or better required */ |
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40 | Cpu386, |
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41 | /* i486 or better required */ |
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42 | Cpu486, |
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43 | /* i585 or better required */ |
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44 | Cpu586, |
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45 | /* i686 or better required */ |
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46 | Cpu686, |
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47 | /* CLFLUSH Instruction support required */ |
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48 | CpuClflush, |
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49 | /* NOP Instruction support required */ |
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50 | CpuNop, |
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51 | /* SYSCALL Instructions support required */ |
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52 | CpuSYSCALL, |
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53 | /* Floating point support required */ |
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54 | Cpu8087, |
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55 | /* i287 support required */ |
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56 | Cpu287, |
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57 | /* i387 support required */ |
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58 | Cpu387, |
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59 | /* i686 and floating point support required */ |
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60 | Cpu687, |
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61 | /* SSE3 and floating point support required */ |
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62 | CpuFISTTP, |
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63 | /* MMX support required */ |
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64 | CpuMMX, |
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65 | /* SSE support required */ |
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66 | CpuSSE, |
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67 | /* SSE2 support required */ |
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68 | CpuSSE2, |
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69 | /* 3dnow! support required */ |
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70 | Cpu3dnow, |
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71 | /* 3dnow! Extensions support required */ |
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72 | Cpu3dnowA, |
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73 | /* SSE3 support required */ |
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74 | CpuSSE3, |
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75 | /* VIA PadLock required */ |
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76 | CpuPadLock, |
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77 | /* AMD Secure Virtual Machine Ext-s required */ |
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78 | CpuSVME, |
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79 | /* VMX Instructions required */ |
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80 | CpuVMX, |
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81 | /* SMX Instructions required */ |
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82 | CpuSMX, |
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83 | /* SSSE3 support required */ |
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84 | CpuSSSE3, |
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85 | /* SSE4a support required */ |
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86 | CpuSSE4a, |
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87 | /* ABM New Instructions required */ |
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88 | CpuABM, |
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89 | /* SSE4.1 support required */ |
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90 | CpuSSE4_1, |
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91 | /* SSE4.2 support required */ |
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92 | CpuSSE4_2, |
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93 | /* AVX support required */ |
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94 | CpuAVX, |
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95 | /* AVX2 support required */ |
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96 | CpuAVX2, |
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97 | /* Intel AVX-512 Foundation Instructions support required */ |
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98 | CpuAVX512F, |
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99 | /* Intel AVX-512 Conflict Detection Instructions support required */ |
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100 | CpuAVX512CD, |
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101 | /* Intel AVX-512 Exponential and Reciprocal Instructions support |
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102 | required */ |
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103 | CpuAVX512ER, |
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104 | /* Intel AVX-512 Prefetch Instructions support required */ |
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105 | CpuAVX512PF, |
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106 | /* Intel L1OM support required */ |
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107 | CpuL1OM, |
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108 | /* Intel K1OM support required */ |
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109 | CpuK1OM, |
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110 | /* Xsave/xrstor New Instructions support required */ |
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111 | CpuXsave, |
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112 | /* Xsaveopt New Instructions support required */ |
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113 | CpuXsaveopt, |
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114 | /* AES support required */ |
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115 | CpuAES, |
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116 | /* PCLMUL support required */ |
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117 | CpuPCLMUL, |
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118 | /* FMA support required */ |
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119 | CpuFMA, |
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120 | /* FMA4 support required */ |
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121 | CpuFMA4, |
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122 | /* XOP support required */ |
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123 | CpuXOP, |
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124 | /* LWP support required */ |
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125 | CpuLWP, |
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126 | /* BMI support required */ |
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127 | CpuBMI, |
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128 | /* TBM support required */ |
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129 | CpuTBM, |
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130 | /* MOVBE Instruction support required */ |
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131 | CpuMovbe, |
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132 | /* CMPXCHG16B instruction support required. */ |
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133 | CpuCX16, |
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134 | /* EPT Instructions required */ |
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135 | CpuEPT, |
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136 | /* RDTSCP Instruction support required */ |
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137 | CpuRdtscp, |
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138 | /* FSGSBASE Instructions required */ |
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139 | CpuFSGSBase, |
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140 | /* RDRND Instructions required */ |
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141 | CpuRdRnd, |
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142 | /* F16C Instructions required */ |
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143 | CpuF16C, |
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144 | /* Intel BMI2 support required */ |
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145 | CpuBMI2, |
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146 | /* LZCNT support required */ |
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147 | CpuLZCNT, |
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148 | /* HLE support required */ |
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149 | CpuHLE, |
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150 | /* RTM support required */ |
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151 | CpuRTM, |
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152 | /* INVPCID Instructions required */ |
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153 | CpuINVPCID, |
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154 | /* VMFUNC Instruction required */ |
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155 | CpuVMFUNC, |
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156 | /* Intel MPX Instructions required */ |
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157 | CpuMPX, |
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158 | /* 64bit support available, used by -march= in assembler. */ |
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159 | CpuLM, |
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160 | /* RDRSEED instruction required. */ |
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161 | CpuRDSEED, |
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162 | /* Multi-presisionn add-carry instructions are required. */ |
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163 | CpuADX, |
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164 | /* Supports prefetchw and prefetch instructions. */ |
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165 | CpuPRFCHW, |
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166 | /* SMAP instructions required. */ |
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167 | CpuSMAP, |
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168 | /* SHA instructions required. */ |
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169 | CpuSHA, |
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170 | /* VREX support required */ |
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171 | CpuVREX, |
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172 | /* 64bit support required */ |
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173 | Cpu64, |
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174 | /* Not supported in the 64bit mode */ |
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175 | CpuNo64, |
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176 | /* The last bitfield in i386_cpu_flags. */ |
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177 | CpuMax = CpuNo64 |
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178 | }; |
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179 | |||
180 | #define CpuNumOfUints \ |
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181 | (CpuMax / sizeof (unsigned int) / CHAR_BIT + 1) |
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182 | #define CpuNumOfBits \ |
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183 | (CpuNumOfUints * sizeof (unsigned int) * CHAR_BIT) |
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184 | |||
185 | /* If you get a compiler error for zero width of the unused field, |
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186 | comment it out. */ |
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187 | #define CpuUnused (CpuMax + 1) |
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188 | |||
189 | /* We can check if an instruction is available with array instead |
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190 | of bitfield. */ |
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191 | typedef union i386_cpu_flags |
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192 | { |
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193 | struct |
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194 | { |
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195 | unsigned int cpui186:1; |
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196 | unsigned int cpui286:1; |
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197 | unsigned int cpui386:1; |
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198 | unsigned int cpui486:1; |
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199 | unsigned int cpui586:1; |
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200 | unsigned int cpui686:1; |
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201 | unsigned int cpuclflush:1; |
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202 | unsigned int cpunop:1; |
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203 | unsigned int cpusyscall:1; |
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204 | unsigned int cpu8087:1; |
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205 | unsigned int cpu287:1; |
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206 | unsigned int cpu387:1; |
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207 | unsigned int cpu687:1; |
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208 | unsigned int cpufisttp:1; |
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209 | unsigned int cpummx:1; |
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210 | unsigned int cpusse:1; |
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211 | unsigned int cpusse2:1; |
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212 | unsigned int cpua3dnow:1; |
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213 | unsigned int cpua3dnowa:1; |
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214 | unsigned int cpusse3:1; |
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215 | unsigned int cpupadlock:1; |
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216 | unsigned int cpusvme:1; |
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217 | unsigned int cpuvmx:1; |
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218 | unsigned int cpusmx:1; |
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219 | unsigned int cpussse3:1; |
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220 | unsigned int cpusse4a:1; |
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221 | unsigned int cpuabm:1; |
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222 | unsigned int cpusse4_1:1; |
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223 | unsigned int cpusse4_2:1; |
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224 | unsigned int cpuavx:1; |
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225 | unsigned int cpuavx2:1; |
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226 | unsigned int cpuavx512f:1; |
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227 | unsigned int cpuavx512cd:1; |
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228 | unsigned int cpuavx512er:1; |
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229 | unsigned int cpuavx512pf:1; |
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230 | unsigned int cpul1om:1; |
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231 | unsigned int cpuk1om:1; |
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232 | unsigned int cpuxsave:1; |
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233 | unsigned int cpuxsaveopt:1; |
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234 | unsigned int cpuaes:1; |
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235 | unsigned int cpupclmul:1; |
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236 | unsigned int cpufma:1; |
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237 | unsigned int cpufma4:1; |
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238 | unsigned int cpuxop:1; |
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239 | unsigned int cpulwp:1; |
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240 | unsigned int cpubmi:1; |
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241 | unsigned int cputbm:1; |
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242 | unsigned int cpumovbe:1; |
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243 | unsigned int cpucx16:1; |
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244 | unsigned int cpuept:1; |
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245 | unsigned int cpurdtscp:1; |
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246 | unsigned int cpufsgsbase:1; |
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247 | unsigned int cpurdrnd:1; |
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248 | unsigned int cpuf16c:1; |
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249 | unsigned int cpubmi2:1; |
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250 | unsigned int cpulzcnt:1; |
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251 | unsigned int cpuhle:1; |
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252 | unsigned int cpurtm:1; |
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253 | unsigned int cpuinvpcid:1; |
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254 | unsigned int cpuvmfunc:1; |
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255 | unsigned int cpumpx:1; |
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256 | unsigned int cpulm:1; |
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257 | unsigned int cpurdseed:1; |
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258 | unsigned int cpuadx:1; |
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259 | unsigned int cpuprfchw:1; |
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260 | unsigned int cpusmap:1; |
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261 | unsigned int cpusha:1; |
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262 | unsigned int cpuvrex:1; |
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263 | unsigned int cpu64:1; |
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264 | unsigned int cpuno64:1; |
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265 | #ifdef CpuUnused |
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266 | unsigned int unused:(CpuNumOfBits - CpuUnused); |
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267 | #endif |
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268 | } bitfield; |
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269 | unsigned int array[CpuNumOfUints]; |
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270 | } i386_cpu_flags; |
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271 | |||
272 | /* Position of opcode_modifier bits. */ |
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273 | |||
274 | enum |
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275 | { |
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276 | /* has direction bit. */ |
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277 | D = 0, |
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278 | /* set if operands can be words or dwords encoded the canonical way */ |
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279 | W, |
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280 | /* Skip the current insn and use the next insn in i386-opc.tbl to swap |
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281 | operand in encoding. */ |
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282 | S, |
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283 | /* insn has a modrm byte. */ |
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284 | Modrm, |
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285 | /* register is in low 3 bits of opcode */ |
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286 | ShortForm, |
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287 | /* special case for jump insns. */ |
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288 | Jump, |
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289 | /* call and jump */ |
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290 | JumpDword, |
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291 | /* loop and jecxz */ |
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292 | JumpByte, |
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293 | /* special case for intersegment leaps/calls */ |
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294 | JumpInterSegment, |
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295 | /* FP insn memory format bit, sized by 0x4 */ |
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296 | FloatMF, |
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297 | /* src/dest swap for floats. */ |
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298 | FloatR, |
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299 | /* has float insn direction bit. */ |
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300 | FloatD, |
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301 | /* needs size prefix if in 32-bit mode */ |
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302 | Size16, |
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303 | /* needs size prefix if in 16-bit mode */ |
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304 | Size32, |
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305 | /* needs size prefix if in 64-bit mode */ |
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306 | Size64, |
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307 | /* check register size. */ |
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308 | CheckRegSize, |
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309 | /* instruction ignores operand size prefix and in Intel mode ignores |
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310 | mnemonic size suffix check. */ |
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311 | IgnoreSize, |
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312 | /* default insn size depends on mode */ |
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313 | DefaultSize, |
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314 | /* b suffix on instruction illegal */ |
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315 | No_bSuf, |
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316 | /* w suffix on instruction illegal */ |
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317 | No_wSuf, |
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318 | /* l suffix on instruction illegal */ |
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319 | No_lSuf, |
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320 | /* s suffix on instruction illegal */ |
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321 | No_sSuf, |
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322 | /* q suffix on instruction illegal */ |
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323 | No_qSuf, |
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324 | /* long double suffix on instruction illegal */ |
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325 | No_ldSuf, |
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326 | /* instruction needs FWAIT */ |
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327 | FWait, |
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328 | /* quick test for string instructions */ |
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329 | IsString, |
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330 | /* quick test if branch instruction is MPX supported */ |
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331 | BNDPrefixOk, |
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332 | /* quick test for lockable instructions */ |
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333 | IsLockable, |
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334 | /* fake an extra reg operand for clr, imul and special register |
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335 | processing for some instructions. */ |
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336 | RegKludge, |
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337 | /* The first operand must be xmm0 */ |
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338 | FirstXmm0, |
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339 | /* An implicit xmm0 as the first operand */ |
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340 | Implicit1stXmm0, |
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341 | /* The HLE prefix is OK: |
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342 | 1. With a LOCK prefix. |
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343 | 2. With or without a LOCK prefix. |
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344 | 3. With a RELEASE (0xf3) prefix. |
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345 | */ |
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346 | #define HLEPrefixNone 0 |
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347 | #define HLEPrefixLock 1 |
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348 | #define HLEPrefixAny 2 |
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349 | #define HLEPrefixRelease 3 |
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350 | HLEPrefixOk, |
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351 | /* An instruction on which a "rep" prefix is acceptable. */ |
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352 | RepPrefixOk, |
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353 | /* Convert to DWORD */ |
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354 | ToDword, |
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355 | /* Convert to QWORD */ |
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356 | ToQword, |
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357 | /* Address prefix changes operand 0 */ |
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358 | AddrPrefixOp0, |
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359 | /* opcode is a prefix */ |
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360 | IsPrefix, |
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361 | /* instruction has extension in 8 bit imm */ |
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362 | ImmExt, |
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363 | /* instruction don't need Rex64 prefix. */ |
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364 | NoRex64, |
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365 | /* instruction require Rex64 prefix. */ |
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366 | Rex64, |
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367 | /* deprecated fp insn, gets a warning */ |
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368 | Ugh, |
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369 | /* insn has VEX prefix: |
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370 | 1: 128bit VEX prefix. |
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371 | 2: 256bit VEX prefix. |
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372 | 3: Scalar VEX prefix. |
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373 | */ |
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374 | #define VEX128 1 |
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375 | #define VEX256 2 |
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376 | #define VEXScalar 3 |
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377 | Vex, |
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378 | /* How to encode VEX.vvvv: |
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379 | 0: VEX.vvvv must be 1111b. |
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380 | 1: VEX.NDS. Register-only source is encoded in VEX.vvvv where |
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381 | the content of source registers will be preserved. |
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382 | VEX.DDS. The second register operand is encoded in VEX.vvvv |
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383 | where the content of first source register will be overwritten |
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384 | by the result. |
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385 | VEX.NDD2. The second destination register operand is encoded in |
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386 | VEX.vvvv for instructions with 2 destination register operands. |
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387 | For assembler, there are no difference between VEX.NDS, VEX.DDS |
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388 | and VEX.NDD2. |
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389 | 2. VEX.NDD. Register destination is encoded in VEX.vvvv for |
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390 | instructions with 1 destination register operand. |
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391 | 3. VEX.LWP. Register destination is encoded in VEX.vvvv and one |
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392 | of the operands can access a memory location. |
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393 | */ |
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394 | #define VEXXDS 1 |
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395 | #define VEXNDD 2 |
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396 | #define VEXLWP 3 |
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397 | VexVVVV, |
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398 | /* How the VEX.W bit is used: |
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399 | 0: Set by the REX.W bit. |
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400 | 1: VEX.W0. Should always be 0. |
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401 | 2: VEX.W1. Should always be 1. |
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402 | */ |
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403 | #define VEXW0 1 |
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404 | #define VEXW1 2 |
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405 | VexW, |
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406 | /* VEX opcode prefix: |
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407 | 0: VEX 0x0F opcode prefix. |
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408 | 1: VEX 0x0F38 opcode prefix. |
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409 | 2: VEX 0x0F3A opcode prefix |
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410 | 3: XOP 0x08 opcode prefix. |
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411 | 4: XOP 0x09 opcode prefix |
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412 | 5: XOP 0x0A opcode prefix. |
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413 | */ |
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414 | #define VEX0F 0 |
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415 | #define VEX0F38 1 |
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416 | #define VEX0F3A 2 |
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417 | #define XOP08 3 |
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418 | #define XOP09 4 |
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419 | #define XOP0A 5 |
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420 | VexOpcode, |
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421 | /* number of VEX source operands: |
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422 | 0: <= 2 source operands. |
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423 | 1: 2 XOP source operands. |
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424 | 2: 3 source operands. |
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425 | */ |
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426 | #define XOP2SOURCES 1 |
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427 | #define VEX3SOURCES 2 |
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428 | VexSources, |
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429 | /* instruction has VEX 8 bit imm */ |
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430 | VexImmExt, |
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431 | /* Instruction with vector SIB byte: |
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432 | 1: 128bit vector register. |
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433 | 2: 256bit vector register. |
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434 | 3: 512bit vector register. |
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435 | */ |
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436 | #define VecSIB128 1 |
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437 | #define VecSIB256 2 |
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438 | #define VecSIB512 3 |
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439 | VecSIB, |
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440 | /* SSE to AVX support required */ |
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441 | SSE2AVX, |
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442 | /* No AVX equivalent */ |
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443 | NoAVX, |
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444 | |||
445 | /* insn has EVEX prefix: |
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446 | 1: 512bit EVEX prefix. |
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447 | 2: 128bit EVEX prefix. |
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448 | 3: 256bit EVEX prefix. |
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449 | 4: Length-ignored (LIG) EVEX prefix. |
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450 | */ |
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451 | #define EVEX512 1 |
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452 | #define EVEX128 2 |
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453 | #define EVEX256 3 |
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454 | #define EVEXLIG 4 |
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455 | EVex, |
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456 | |||
457 | /* AVX512 masking support: |
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458 | 1: Zeroing-masking. |
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459 | 2: Merging-masking. |
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460 | 3: Both zeroing and merging masking. |
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461 | */ |
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462 | #define ZEROING_MASKING 1 |
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463 | #define MERGING_MASKING 2 |
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464 | #define BOTH_MASKING 3 |
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465 | Masking, |
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466 | |||
467 | /* Input element size of vector insn: |
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468 | 0: 32bit. |
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469 | 1: 64bit. |
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470 | */ |
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471 | VecESize, |
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472 | |||
473 | /* Broadcast factor. |
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474 | 0: No broadcast. |
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475 | 1: 1to16 broadcast. |
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476 | 2: 1to8 broadcast. |
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477 | */ |
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478 | #define NO_BROADCAST 0 |
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479 | #define BROADCAST_1TO16 1 |
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480 | #define BROADCAST_1TO8 2 |
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481 | Broadcast, |
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482 | |||
483 | /* Static rounding control is supported. */ |
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484 | StaticRounding, |
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485 | |||
486 | /* Supress All Exceptions is supported. */ |
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487 | SAE, |
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488 | |||
489 | /* Copressed Disp8*N attribute. */ |
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490 | Disp8MemShift, |
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491 | |||
492 | /* Default mask isn't allowed. */ |
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493 | NoDefMask, |
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494 | |||
495 | /* Compatible with old (<= 2.8.1) versions of gcc */ |
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496 | OldGcc, |
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497 | /* AT&T mnemonic. */ |
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498 | ATTMnemonic, |
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499 | /* AT&T syntax. */ |
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500 | ATTSyntax, |
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501 | /* Intel syntax. */ |
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502 | IntelSyntax, |
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503 | /* The last bitfield in i386_opcode_modifier. */ |
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504 | Opcode_Modifier_Max |
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505 | }; |
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506 | |||
507 | typedef struct i386_opcode_modifier |
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508 | { |
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509 | unsigned int d:1; |
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510 | unsigned int w:1; |
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511 | unsigned int s:1; |
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512 | unsigned int modrm:1; |
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513 | unsigned int shortform:1; |
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514 | unsigned int jump:1; |
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515 | unsigned int jumpdword:1; |
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516 | unsigned int jumpbyte:1; |
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517 | unsigned int jumpintersegment:1; |
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518 | unsigned int floatmf:1; |
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519 | unsigned int floatr:1; |
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520 | unsigned int floatd:1; |
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521 | unsigned int size16:1; |
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522 | unsigned int size32:1; |
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523 | unsigned int size64:1; |
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524 | unsigned int checkregsize:1; |
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525 | unsigned int ignoresize:1; |
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526 | unsigned int defaultsize:1; |
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527 | unsigned int no_bsuf:1; |
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528 | unsigned int no_wsuf:1; |
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529 | unsigned int no_lsuf:1; |
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530 | unsigned int no_ssuf:1; |
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531 | unsigned int no_qsuf:1; |
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532 | unsigned int no_ldsuf:1; |
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533 | unsigned int fwait:1; |
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534 | unsigned int isstring:1; |
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535 | unsigned int bndprefixok:1; |
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536 | unsigned int islockable:1; |
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537 | unsigned int regkludge:1; |
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538 | unsigned int firstxmm0:1; |
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539 | unsigned int implicit1stxmm0:1; |
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540 | unsigned int hleprefixok:2; |
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541 | unsigned int repprefixok:1; |
||
542 | unsigned int todword:1; |
||
543 | unsigned int toqword:1; |
||
544 | unsigned int addrprefixop0:1; |
||
545 | unsigned int isprefix:1; |
||
546 | unsigned int immext:1; |
||
547 | unsigned int norex64:1; |
||
548 | unsigned int rex64:1; |
||
549 | unsigned int ugh:1; |
||
550 | unsigned int vex:2; |
||
551 | unsigned int vexvvvv:2; |
||
552 | unsigned int vexw:2; |
||
553 | unsigned int vexopcode:3; |
||
554 | unsigned int vexsources:2; |
||
555 | unsigned int veximmext:1; |
||
556 | unsigned int vecsib:2; |
||
557 | unsigned int sse2avx:1; |
||
558 | unsigned int noavx:1; |
||
559 | unsigned int evex:3; |
||
560 | unsigned int masking:2; |
||
561 | unsigned int vecesize:1; |
||
562 | unsigned int broadcast:3; |
||
563 | unsigned int staticrounding:1; |
||
564 | unsigned int sae:1; |
||
565 | unsigned int disp8memshift:3; |
||
566 | unsigned int nodefmask:1; |
||
567 | unsigned int oldgcc:1; |
||
568 | unsigned int attmnemonic:1; |
||
569 | unsigned int attsyntax:1; |
||
570 | unsigned int intelsyntax:1; |
||
571 | } i386_opcode_modifier; |
||
572 | |||
573 | /* Position of operand_type bits. */ |
||
574 | |||
575 | enum |
||
576 | { |
||
577 | /* 8bit register */ |
||
578 | Reg8 = 0, |
||
579 | /* 16bit register */ |
||
580 | Reg16, |
||
581 | /* 32bit register */ |
||
582 | Reg32, |
||
583 | /* 64bit register */ |
||
584 | Reg64, |
||
585 | /* Floating pointer stack register */ |
||
586 | FloatReg, |
||
587 | /* MMX register */ |
||
588 | RegMMX, |
||
589 | /* SSE register */ |
||
590 | RegXMM, |
||
591 | /* AVX registers */ |
||
592 | RegYMM, |
||
593 | /* AVX512 registers */ |
||
594 | RegZMM, |
||
595 | /* Vector Mask registers */ |
||
596 | RegMask, |
||
597 | /* Control register */ |
||
598 | Control, |
||
599 | /* Debug register */ |
||
600 | Debug, |
||
601 | /* Test register */ |
||
602 | Test, |
||
603 | /* 2 bit segment register */ |
||
604 | SReg2, |
||
605 | /* 3 bit segment register */ |
||
606 | SReg3, |
||
607 | /* 1 bit immediate */ |
||
608 | Imm1, |
||
609 | /* 8 bit immediate */ |
||
610 | Imm8, |
||
611 | /* 8 bit immediate sign extended */ |
||
612 | Imm8S, |
||
613 | /* 16 bit immediate */ |
||
614 | Imm16, |
||
615 | /* 32 bit immediate */ |
||
616 | Imm32, |
||
617 | /* 32 bit immediate sign extended */ |
||
618 | Imm32S, |
||
619 | /* 64 bit immediate */ |
||
620 | Imm64, |
||
621 | /* 8bit/16bit/32bit displacements are used in different ways, |
||
622 | depending on the instruction. For jumps, they specify the |
||
623 | size of the PC relative displacement, for instructions with |
||
624 | memory operand, they specify the size of the offset relative |
||
625 | to the base register, and for instructions with memory offset |
||
626 | such as `mov 1234,%al' they specify the size of the offset |
||
627 | relative to the segment base. */ |
||
628 | /* 8 bit displacement */ |
||
629 | Disp8, |
||
630 | /* 16 bit displacement */ |
||
631 | Disp16, |
||
632 | /* 32 bit displacement */ |
||
633 | Disp32, |
||
634 | /* 32 bit signed displacement */ |
||
635 | Disp32S, |
||
636 | /* 64 bit displacement */ |
||
637 | Disp64, |
||
638 | /* Accumulator %al/%ax/%eax/%rax */ |
||
639 | Acc, |
||
640 | /* Floating pointer top stack register %st(0) */ |
||
641 | FloatAcc, |
||
642 | /* Register which can be used for base or index in memory operand. */ |
||
643 | BaseIndex, |
||
644 | /* Register to hold in/out port addr = dx */ |
||
645 | InOutPortReg, |
||
646 | /* Register to hold shift count = cl */ |
||
647 | ShiftCount, |
||
648 | /* Absolute address for jump. */ |
||
649 | JumpAbsolute, |
||
650 | /* String insn operand with fixed es segment */ |
||
651 | EsSeg, |
||
652 | /* RegMem is for instructions with a modrm byte where the register |
||
653 | destination operand should be encoded in the mod and regmem fields. |
||
654 | Normally, it will be encoded in the reg field. We add a RegMem |
||
655 | flag to the destination register operand to indicate that it should |
||
656 | be encoded in the regmem field. */ |
||
657 | RegMem, |
||
658 | /* Memory. */ |
||
659 | Mem, |
||
660 | /* BYTE memory. */ |
||
661 | Byte, |
||
662 | /* WORD memory. 2 byte */ |
||
663 | Word, |
||
664 | /* DWORD memory. 4 byte */ |
||
665 | Dword, |
||
666 | /* FWORD memory. 6 byte */ |
||
667 | Fword, |
||
668 | /* QWORD memory. 8 byte */ |
||
669 | Qword, |
||
670 | /* TBYTE memory. 10 byte */ |
||
671 | Tbyte, |
||
672 | /* XMMWORD memory. */ |
||
673 | Xmmword, |
||
674 | /* YMMWORD memory. */ |
||
675 | Ymmword, |
||
676 | /* ZMMWORD memory. */ |
||
677 | Zmmword, |
||
678 | /* Unspecified memory size. */ |
||
679 | Unspecified, |
||
680 | /* Any memory size. */ |
||
681 | Anysize, |
||
682 | |||
683 | /* Vector 4 bit immediate. */ |
||
684 | Vec_Imm4, |
||
685 | |||
686 | /* Bound register. */ |
||
687 | RegBND, |
||
688 | |||
689 | /* Vector 8bit displacement */ |
||
690 | Vec_Disp8, |
||
691 | |||
692 | /* The last bitfield in i386_operand_type. */ |
||
693 | OTMax |
||
694 | }; |
||
695 | |||
696 | #define OTNumOfUints \ |
||
697 | (OTMax / sizeof (unsigned int) / CHAR_BIT + 1) |
||
698 | #define OTNumOfBits \ |
||
699 | (OTNumOfUints * sizeof (unsigned int) * CHAR_BIT) |
||
700 | |||
701 | /* If you get a compiler error for zero width of the unused field, |
||
702 | comment it out. */ |
||
703 | #define OTUnused (OTMax + 1) |
||
704 | |||
705 | typedef union i386_operand_type |
||
706 | { |
||
707 | struct |
||
708 | { |
||
709 | unsigned int reg8:1; |
||
710 | unsigned int reg16:1; |
||
711 | unsigned int reg32:1; |
||
712 | unsigned int reg64:1; |
||
713 | unsigned int floatreg:1; |
||
714 | unsigned int regmmx:1; |
||
715 | unsigned int regxmm:1; |
||
716 | unsigned int regymm:1; |
||
717 | unsigned int regzmm:1; |
||
718 | unsigned int regmask:1; |
||
719 | unsigned int control:1; |
||
720 | unsigned int debug:1; |
||
721 | unsigned int test:1; |
||
722 | unsigned int sreg2:1; |
||
723 | unsigned int sreg3:1; |
||
724 | unsigned int imm1:1; |
||
725 | unsigned int imm8:1; |
||
726 | unsigned int imm8s:1; |
||
727 | unsigned int imm16:1; |
||
728 | unsigned int imm32:1; |
||
729 | unsigned int imm32s:1; |
||
730 | unsigned int imm64:1; |
||
731 | unsigned int disp8:1; |
||
732 | unsigned int disp16:1; |
||
733 | unsigned int disp32:1; |
||
734 | unsigned int disp32s:1; |
||
735 | unsigned int disp64:1; |
||
736 | unsigned int acc:1; |
||
737 | unsigned int floatacc:1; |
||
738 | unsigned int baseindex:1; |
||
739 | unsigned int inoutportreg:1; |
||
740 | unsigned int shiftcount:1; |
||
741 | unsigned int jumpabsolute:1; |
||
742 | unsigned int esseg:1; |
||
743 | unsigned int regmem:1; |
||
744 | unsigned int mem:1; |
||
745 | unsigned int byte:1; |
||
746 | unsigned int word:1; |
||
747 | unsigned int dword:1; |
||
748 | unsigned int fword:1; |
||
749 | unsigned int qword:1; |
||
750 | unsigned int tbyte:1; |
||
751 | unsigned int xmmword:1; |
||
752 | unsigned int ymmword:1; |
||
753 | unsigned int zmmword:1; |
||
754 | unsigned int unspecified:1; |
||
755 | unsigned int anysize:1; |
||
756 | unsigned int vec_imm4:1; |
||
757 | unsigned int regbnd:1; |
||
758 | unsigned int vec_disp8:1; |
||
759 | #ifdef OTUnused |
||
760 | unsigned int unused:(OTNumOfBits - OTUnused); |
||
761 | #endif |
||
762 | } bitfield; |
||
763 | unsigned int array[OTNumOfUints]; |
||
764 | } i386_operand_type; |
||
765 | |||
766 | typedef struct insn_template |
||
767 | { |
||
768 | /* instruction name sans width suffix ("mov" for movl insns) */ |
||
769 | char *name; |
||
770 | |||
771 | /* how many operands */ |
||
772 | unsigned int operands; |
||
773 | |||
774 | /* base_opcode is the fundamental opcode byte without optional |
||
775 | prefix(es). */ |
||
776 | unsigned int base_opcode; |
||
777 | #define Opcode_D 0x2 /* Direction bit: |
||
778 | set if Reg --> Regmem; |
||
779 | unset if Regmem --> Reg. */ |
||
780 | #define Opcode_FloatR 0x8 /* Bit to swap src/dest for float insns. */ |
||
781 | #define Opcode_FloatD 0x400 /* Direction bit for float insns. */ |
||
782 | |||
783 | /* extension_opcode is the 3 bit extension for group |
||
784 | This field is also used to store the 8-bit opcode suffix for the |
||
785 | AMD 3DNow! instructions. |
||
786 | If this template has no extension opcode (the usual case) use None |
||
787 | Instructions */ |
||
788 | unsigned int extension_opcode; |
||
789 | #define None 0xffff /* If no extension_opcode is possible. */ |
||
790 | |||
791 | /* Opcode length. */ |
||
792 | unsigned char opcode_length; |
||
793 | |||
794 | /* cpu feature flags */ |
||
795 | i386_cpu_flags cpu_flags; |
||
796 | |||
797 | /* the bits in opcode_modifier are used to generate the final opcode from |
||
798 | the base_opcode. These bits also are used to detect alternate forms of |
||
799 | the same instruction */ |
||
800 | i386_opcode_modifier opcode_modifier; |
||
801 | |||
802 | /* operand_types[i] describes the type of operand i. This is made |
||
803 | by OR'ing together all of the possible type masks. (e.g. |
||
804 | 'operand_types[i] = Reg|Imm' specifies that operand i can be |
||
805 | either a register or an immediate operand. */ |
||
806 | i386_operand_type operand_types[MAX_OPERANDS]; |
||
807 | } |
||
808 | insn_template; |
||
809 | |||
810 | extern const insn_template i386_optab[]; |
||
811 | |||
812 | /* these are for register name --> number & type hash lookup */ |
||
813 | typedef struct |
||
814 | { |
||
815 | char *reg_name; |
||
816 | i386_operand_type reg_type; |
||
817 | unsigned char reg_flags; |
||
818 | #define RegRex 0x1 /* Extended register. */ |
||
819 | #define RegRex64 0x2 /* Extended 8 bit register. */ |
||
820 | #define RegVRex 0x4 /* Extended vector register. */ |
||
821 | unsigned char reg_num; |
||
822 | #define RegRip ((unsigned char ) ~0) |
||
823 | #define RegEip (RegRip - 1) |
||
824 | /* EIZ and RIZ are fake index registers. */ |
||
825 | #define RegEiz (RegEip - 1) |
||
826 | #define RegRiz (RegEiz - 1) |
||
827 | /* FLAT is a fake segment register (Intel mode). */ |
||
828 | #define RegFlat ((unsigned char) ~0) |
||
829 | signed char dw2_regnum[2]; |
||
830 | #define Dw2Inval (-1) |
||
831 | } |
||
832 | reg_entry; |
||
833 | |||
834 | /* Entries in i386_regtab. */ |
||
835 | #define REGNAM_AL 1 |
||
836 | #define REGNAM_AX 25 |
||
837 | #define REGNAM_EAX 41 |
||
838 | |||
839 | extern const reg_entry i386_regtab[]; |
||
840 | extern const unsigned int i386_regtab_size; |
||
841 | |||
842 | typedef struct |
||
843 | { |
||
844 | char *seg_name; |
||
845 | unsigned int seg_prefix; |
||
846 | } |
||
847 | seg_entry; |
||
848 | |||
849 | extern const seg_entry cs; |
||
850 | extern const seg_entry ds; |
||
851 | extern const seg_entry ss; |
||
852 | extern const seg_entry es; |
||
853 | extern const seg_entry fs; |
||
854 | extern const seg_entry gs;=>=> |