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6324 | serge | 1 | /* Nios II R2 opcode list for GAS, the GNU assembler. |
2 | Copyright (C) 2013-2015 Free Software Foundation, Inc. |
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3 | Contributed by Mentor Graphics, Inc. |
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4 | |||
5 | This file is part of GAS, the GNU Assembler, and GDB, the GNU disassembler. |
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6 | |||
7 | GAS/GDB is free software; you can redistribute it and/or modify |
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8 | it under the terms of the GNU General Public License as published by |
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9 | the Free Software Foundation; either version 3, or (at your option) |
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10 | any later version. |
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11 | |||
12 | GAS/GDB is distributed in the hope that it will be useful, |
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13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 | GNU General Public License for more details. |
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16 | |||
17 | You should have received a copy of the GNU General Public License |
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18 | along with GAS or GDB; see the file COPYING3. If not, write to |
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19 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, |
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20 | Boston, MA 02110-1301, USA. */ |
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21 | |||
22 | #ifndef _NIOS2R2_H_ |
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23 | #define _NIOS2R2_H_ |
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24 | |||
25 | /* Fields for 32-bit R2 instructions. */ |
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26 | |||
27 | #define IW_R2_OP_LSB 0 |
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28 | #define IW_R2_OP_SIZE 6 |
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29 | #define IW_R2_OP_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R2_OP_SIZE)) |
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30 | #define IW_R2_OP_SHIFTED_MASK (IW_R2_OP_UNSHIFTED_MASK << IW_R2_OP_LSB) |
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31 | #define GET_IW_R2_OP(W) (((W) >> IW_R2_OP_LSB) & IW_R2_OP_UNSHIFTED_MASK) |
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32 | #define SET_IW_R2_OP(V) (((V) & IW_R2_OP_UNSHIFTED_MASK) << IW_R2_OP_LSB) |
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33 | |||
34 | #define IW_L26_IMM26_LSB 6 |
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35 | #define IW_L26_IMM26_SIZE 26 |
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36 | #define IW_L26_IMM26_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L26_IMM26_SIZE)) |
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37 | #define IW_L26_IMM26_SHIFTED_MASK (IW_L26_IMM26_UNSHIFTED_MASK << IW_L26_IMM26_LSB) |
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38 | #define GET_IW_L26_IMM26(W) (((W) >> IW_L26_IMM26_LSB) & IW_L26_IMM26_UNSHIFTED_MASK) |
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39 | #define SET_IW_L26_IMM26(V) (((V) & IW_L26_IMM26_UNSHIFTED_MASK) << IW_L26_IMM26_LSB) |
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40 | |||
41 | #define IW_F2I16_A_LSB 6 |
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42 | #define IW_F2I16_A_SIZE 5 |
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43 | #define IW_F2I16_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2I16_A_SIZE)) |
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44 | #define IW_F2I16_A_SHIFTED_MASK (IW_F2I16_A_UNSHIFTED_MASK << IW_F2I16_A_LSB) |
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45 | #define GET_IW_F2I16_A(W) (((W) >> IW_F2I16_A_LSB) & IW_F2I16_A_UNSHIFTED_MASK) |
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46 | #define SET_IW_F2I16_A(V) (((V) & IW_F2I16_A_UNSHIFTED_MASK) << IW_F2I16_A_LSB) |
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47 | |||
48 | #define IW_F2I16_B_LSB 11 |
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49 | #define IW_F2I16_B_SIZE 5 |
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50 | #define IW_F2I16_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2I16_B_SIZE)) |
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51 | #define IW_F2I16_B_SHIFTED_MASK (IW_F2I16_B_UNSHIFTED_MASK << IW_F2I16_B_LSB) |
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52 | #define GET_IW_F2I16_B(W) (((W) >> IW_F2I16_B_LSB) & IW_F2I16_B_UNSHIFTED_MASK) |
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53 | #define SET_IW_F2I16_B(V) (((V) & IW_F2I16_B_UNSHIFTED_MASK) << IW_F2I16_B_LSB) |
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54 | |||
55 | #define IW_F2I16_IMM16_LSB 16 |
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56 | #define IW_F2I16_IMM16_SIZE 16 |
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57 | #define IW_F2I16_IMM16_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2I16_IMM16_SIZE)) |
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58 | #define IW_F2I16_IMM16_SHIFTED_MASK (IW_F2I16_IMM16_UNSHIFTED_MASK << IW_F2I16_IMM16_LSB) |
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59 | #define GET_IW_F2I16_IMM16(W) (((W) >> IW_F2I16_IMM16_LSB) & IW_F2I16_IMM16_UNSHIFTED_MASK) |
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60 | #define SET_IW_F2I16_IMM16(V) (((V) & IW_F2I16_IMM16_UNSHIFTED_MASK) << IW_F2I16_IMM16_LSB) |
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61 | |||
62 | /* Common to all three I12-group formats F2X4I12, F1X4I12, F1X4L17. */ |
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63 | #define IW_I12_X_LSB 28 |
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64 | #define IW_I12_X_SIZE 4 |
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65 | #define IW_I12_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_I12_X_SIZE)) |
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66 | #define IW_I12_X_SHIFTED_MASK (IW_I12_X_UNSHIFTED_MASK << IW_I12_X_LSB) |
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67 | #define GET_IW_I12_X(W) (((W) >> IW_I12_X_LSB) & IW_I12_X_UNSHIFTED_MASK) |
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68 | #define SET_IW_I12_X(V) (((V) & IW_I12_X_UNSHIFTED_MASK) << IW_I12_X_LSB) |
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69 | |||
70 | #define IW_F2X4I12_A_LSB 6 |
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71 | #define IW_F2X4I12_A_SIZE 5 |
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72 | #define IW_F2X4I12_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X4I12_A_SIZE)) |
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73 | #define IW_F2X4I12_A_SHIFTED_MASK (IW_F2X4I12_A_UNSHIFTED_MASK << IW_F2X4I12_A_LSB) |
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74 | #define GET_IW_F2X4I12_A(W) (((W) >> IW_F2X4I12_A_LSB) & IW_F2X4I12_A_UNSHIFTED_MASK) |
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75 | #define SET_IW_F2X4I12_A(V) (((V) & IW_F2X4I12_A_UNSHIFTED_MASK) << IW_F2X4I12_A_LSB) |
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76 | |||
77 | #define IW_F2X4I12_B_LSB 11 |
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78 | #define IW_F2X4I12_B_SIZE 5 |
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79 | #define IW_F2X4I12_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X4I12_B_SIZE)) |
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80 | #define IW_F2X4I12_B_SHIFTED_MASK (IW_F2X4I12_B_UNSHIFTED_MASK << IW_F2X4I12_B_LSB) |
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81 | #define GET_IW_F2X4I12_B(W) (((W) >> IW_F2X4I12_B_LSB) & IW_F2X4I12_B_UNSHIFTED_MASK) |
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82 | #define SET_IW_F2X4I12_B(V) (((V) & IW_F2X4I12_B_UNSHIFTED_MASK) << IW_F2X4I12_B_LSB) |
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83 | |||
84 | #define IW_F2X4I12_IMM12_LSB 16 |
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85 | #define IW_F2X4I12_IMM12_SIZE 12 |
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86 | #define IW_F2X4I12_IMM12_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X4I12_IMM12_SIZE)) |
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87 | #define IW_F2X4I12_IMM12_SHIFTED_MASK (IW_F2X4I12_IMM12_UNSHIFTED_MASK << IW_F2X4I12_IMM12_LSB) |
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88 | #define GET_IW_F2X4I12_IMM12(W) (((W) >> IW_F2X4I12_IMM12_LSB) & IW_F2X4I12_IMM12_UNSHIFTED_MASK) |
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89 | #define SET_IW_F2X4I12_IMM12(V) (((V) & IW_F2X4I12_IMM12_UNSHIFTED_MASK) << IW_F2X4I12_IMM12_LSB) |
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90 | |||
91 | #define IW_F1X4I12_A_LSB 6 |
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92 | #define IW_F1X4I12_A_SIZE 5 |
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93 | #define IW_F1X4I12_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4I12_A_SIZE)) |
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94 | #define IW_F1X4I12_A_SHIFTED_MASK (IW_F1X4I12_A_UNSHIFTED_MASK << IW_F1X4I12_A_LSB) |
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95 | #define GET_IW_F1X4I12_A(W) (((W) >> IW_F1X4I12_A_LSB) & IW_F1X4I12_A_UNSHIFTED_MASK) |
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96 | #define SET_IW_F1X4I12_A(V) (((V) & IW_F1X4I12_A_UNSHIFTED_MASK) << IW_F1X4I12_A_LSB) |
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97 | |||
98 | #define IW_F1X4I12_X_LSB 11 |
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99 | #define IW_F1X4I12_X_SIZE 5 |
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100 | #define IW_F1X4I12_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4I12_X_SIZE)) |
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101 | #define IW_F1X4I12_X_SHIFTED_MASK (IW_F1X4I12_X_UNSHIFTED_MASK << IW_F1X4I12_X_LSB) |
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102 | #define GET_IW_F1X4I12_X(W) (((W) >> IW_F1X4I12_X_LSB) & IW_F1X4I12_X_UNSHIFTED_MASK) |
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103 | #define SET_IW_F1X4I12_X(V) (((V) & IW_F1X4I12_X_UNSHIFTED_MASK) << IW_F1X4I12_X_LSB) |
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104 | |||
105 | #define IW_F1X4I12_IMM12_LSB 16 |
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106 | #define IW_F1X4I12_IMM12_SIZE 12 |
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107 | #define IW_F1X4I12_IMM12_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4I12_IMM12_SIZE)) |
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108 | #define IW_F1X4I12_IMM12_SHIFTED_MASK (IW_F1X4I12_IMM12_UNSHIFTED_MASK << IW_F1X4I12_IMM12_LSB) |
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109 | #define GET_IW_F1X4I12_IMM12(W) (((W) >> IW_F1X4I12_IMM12_LSB) & IW_F1X4I12_IMM12_UNSHIFTED_MASK) |
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110 | #define SET_IW_F1X4I12_IMM12(V) (((V) & IW_F1X4I12_IMM12_UNSHIFTED_MASK) << IW_F1X4I12_IMM12_LSB) |
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111 | |||
112 | #define IW_F1X4L17_A_LSB 6 |
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113 | #define IW_F1X4L17_A_SIZE 5 |
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114 | #define IW_F1X4L17_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_A_SIZE)) |
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115 | #define IW_F1X4L17_A_SHIFTED_MASK (IW_F1X4L17_A_UNSHIFTED_MASK << IW_F1X4L17_A_LSB) |
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116 | #define GET_IW_F1X4L17_A(W) (((W) >> IW_F1X4L17_A_LSB) & IW_F1X4L17_A_UNSHIFTED_MASK) |
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117 | #define SET_IW_F1X4L17_A(V) (((V) & IW_F1X4L17_A_UNSHIFTED_MASK) << IW_F1X4L17_A_LSB) |
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118 | |||
119 | #define IW_F1X4L17_ID_LSB 11 |
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120 | #define IW_F1X4L17_ID_SIZE 1 |
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121 | #define IW_F1X4L17_ID_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_ID_SIZE)) |
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122 | #define IW_F1X4L17_ID_SHIFTED_MASK (IW_F1X4L17_ID_UNSHIFTED_MASK << IW_F1X4L17_ID_LSB) |
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123 | #define GET_IW_F1X4L17_ID(W) (((W) >> IW_F1X4L17_ID_LSB) & IW_F1X4L17_ID_UNSHIFTED_MASK) |
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124 | #define SET_IW_F1X4L17_ID(V) (((V) & IW_F1X4L17_ID_UNSHIFTED_MASK) << IW_F1X4L17_ID_LSB) |
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125 | |||
126 | #define IW_F1X4L17_WB_LSB 12 |
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127 | #define IW_F1X4L17_WB_SIZE 1 |
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128 | #define IW_F1X4L17_WB_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_WB_SIZE)) |
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129 | #define IW_F1X4L17_WB_SHIFTED_MASK (IW_F1X4L17_WB_UNSHIFTED_MASK << IW_F1X4L17_WB_LSB) |
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130 | #define GET_IW_F1X4L17_WB(W) (((W) >> IW_F1X4L17_WB_LSB) & IW_F1X4L17_WB_UNSHIFTED_MASK) |
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131 | #define SET_IW_F1X4L17_WB(V) (((V) & IW_F1X4L17_WB_UNSHIFTED_MASK) << IW_F1X4L17_WB_LSB) |
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132 | |||
133 | #define IW_F1X4L17_RS_LSB 13 |
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134 | #define IW_F1X4L17_RS_SIZE 1 |
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135 | #define IW_F1X4L17_RS_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_RS_SIZE)) |
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136 | #define IW_F1X4L17_RS_SHIFTED_MASK (IW_F1X4L17_RS_UNSHIFTED_MASK << IW_F1X4L17_RS_LSB) |
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137 | #define GET_IW_F1X4L17_RS(W) (((W) >> IW_F1X4L17_RS_LSB) & IW_F1X4L17_RS_UNSHIFTED_MASK) |
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138 | #define SET_IW_F1X4L17_RS(V) (((V) & IW_F1X4L17_RS_UNSHIFTED_MASK) << IW_F1X4L17_RS_LSB) |
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139 | |||
140 | #define IW_F1X4L17_PC_LSB 14 |
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141 | #define IW_F1X4L17_PC_SIZE 1 |
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142 | #define IW_F1X4L17_PC_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_PC_SIZE)) |
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143 | #define IW_F1X4L17_PC_SHIFTED_MASK (IW_F1X4L17_PC_UNSHIFTED_MASK << IW_F1X4L17_PC_LSB) |
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144 | #define GET_IW_F1X4L17_PC(W) (((W) >> IW_F1X4L17_PC_LSB) & IW_F1X4L17_PC_UNSHIFTED_MASK) |
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145 | #define SET_IW_F1X4L17_PC(V) (((V) & IW_F1X4L17_PC_UNSHIFTED_MASK) << IW_F1X4L17_PC_LSB) |
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146 | |||
147 | #define IW_F1X4L17_RSV_LSB 15 |
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148 | #define IW_F1X4L17_RSV_SIZE 1 |
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149 | #define IW_F1X4L17_RSV_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_RSV_SIZE)) |
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150 | #define IW_F1X4L17_RSV_SHIFTED_MASK (IW_F1X4L17_RSV_UNSHIFTED_MASK << IW_F1X4L17_RSV_LSB) |
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151 | #define GET_IW_F1X4L17_RSV(W) (((W) >> IW_F1X4L17_RSV_LSB) & IW_F1X4L17_RSV_UNSHIFTED_MASK) |
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152 | #define SET_IW_F1X4L17_RSV(V) (((V) & IW_F1X4L17_RSV_UNSHIFTED_MASK) << IW_F1X4L17_RSV_LSB) |
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153 | |||
154 | #define IW_F1X4L17_REGMASK_LSB 16 |
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155 | #define IW_F1X4L17_REGMASK_SIZE 12 |
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156 | #define IW_F1X4L17_REGMASK_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X4L17_REGMASK_SIZE)) |
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157 | #define IW_F1X4L17_REGMASK_SHIFTED_MASK (IW_F1X4L17_REGMASK_UNSHIFTED_MASK << IW_F1X4L17_REGMASK_LSB) |
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158 | #define GET_IW_F1X4L17_REGMASK(W) (((W) >> IW_F1X4L17_REGMASK_LSB) & IW_F1X4L17_REGMASK_UNSHIFTED_MASK) |
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159 | #define SET_IW_F1X4L17_REGMASK(V) (((V) & IW_F1X4L17_REGMASK_UNSHIFTED_MASK) << IW_F1X4L17_REGMASK_LSB) |
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160 | |||
161 | /* Shared by OPX-group formats F3X6L5, F2X6L10, F3X6. */ |
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162 | #define IW_OPX_X_LSB 26 |
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163 | #define IW_OPX_X_SIZE 6 |
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164 | #define IW_OPX_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_OPX_X_SIZE)) |
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165 | #define IW_OPX_X_SHIFTED_MASK (IW_OPX_X_UNSHIFTED_MASK << IW_OPX_X_LSB) |
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166 | #define GET_IW_OPX_X(W) (((W) >> IW_OPX_X_LSB) & IW_OPX_X_UNSHIFTED_MASK) |
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167 | #define SET_IW_OPX_X(V) (((V) & IW_OPX_X_UNSHIFTED_MASK) << IW_OPX_X_LSB) |
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168 | |||
169 | /* F3X6L5 accessors are also used for F3X6 formats. */ |
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170 | #define IW_F3X6L5_A_LSB 6 |
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171 | #define IW_F3X6L5_A_SIZE 5 |
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172 | #define IW_F3X6L5_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X6L5_A_SIZE)) |
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173 | #define IW_F3X6L5_A_SHIFTED_MASK (IW_F3X6L5_A_UNSHIFTED_MASK << IW_F3X6L5_A_LSB) |
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174 | #define GET_IW_F3X6L5_A(W) (((W) >> IW_F3X6L5_A_LSB) & IW_F3X6L5_A_UNSHIFTED_MASK) |
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175 | #define SET_IW_F3X6L5_A(V) (((V) & IW_F3X6L5_A_UNSHIFTED_MASK) << IW_F3X6L5_A_LSB) |
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176 | |||
177 | #define IW_F3X6L5_B_LSB 11 |
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178 | #define IW_F3X6L5_B_SIZE 5 |
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179 | #define IW_F3X6L5_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X6L5_B_SIZE)) |
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180 | #define IW_F3X6L5_B_SHIFTED_MASK (IW_F3X6L5_B_UNSHIFTED_MASK << IW_F3X6L5_B_LSB) |
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181 | #define GET_IW_F3X6L5_B(W) (((W) >> IW_F3X6L5_B_LSB) & IW_F3X6L5_B_UNSHIFTED_MASK) |
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182 | #define SET_IW_F3X6L5_B(V) (((V) & IW_F3X6L5_B_UNSHIFTED_MASK) << IW_F3X6L5_B_LSB) |
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183 | |||
184 | #define IW_F3X6L5_C_LSB 16 |
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185 | #define IW_F3X6L5_C_SIZE 5 |
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186 | #define IW_F3X6L5_C_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X6L5_C_SIZE)) |
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187 | #define IW_F3X6L5_C_SHIFTED_MASK (IW_F3X6L5_C_UNSHIFTED_MASK << IW_F3X6L5_C_LSB) |
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188 | #define GET_IW_F3X6L5_C(W) (((W) >> IW_F3X6L5_C_LSB) & IW_F3X6L5_C_UNSHIFTED_MASK) |
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189 | #define SET_IW_F3X6L5_C(V) (((V) & IW_F3X6L5_C_UNSHIFTED_MASK) << IW_F3X6L5_C_LSB) |
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190 | |||
191 | #define IW_F3X6L5_IMM5_LSB 21 |
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192 | #define IW_F3X6L5_IMM5_SIZE 5 |
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193 | #define IW_F3X6L5_IMM5_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X6L5_IMM5_SIZE)) |
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194 | #define IW_F3X6L5_IMM5_SHIFTED_MASK (IW_F3X6L5_IMM5_UNSHIFTED_MASK << IW_F3X6L5_IMM5_LSB) |
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195 | #define GET_IW_F3X6L5_IMM5(W) (((W) >> IW_F3X6L5_IMM5_LSB) & IW_F3X6L5_IMM5_UNSHIFTED_MASK) |
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196 | #define SET_IW_F3X6L5_IMM5(V) (((V) & IW_F3X6L5_IMM5_UNSHIFTED_MASK) << IW_F3X6L5_IMM5_LSB) |
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197 | |||
198 | #define IW_F2X6L10_A_LSB 6 |
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199 | #define IW_F2X6L10_A_SIZE 5 |
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200 | #define IW_F2X6L10_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X6L10_A_SIZE)) |
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201 | #define IW_F2X6L10_A_SHIFTED_MASK (IW_F2X6L10_A_UNSHIFTED_MASK << IW_F2X6L10_A_LSB) |
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202 | #define GET_IW_F2X6L10_A(W) (((W) >> IW_F2X6L10_A_LSB) & IW_F2X6L10_A_UNSHIFTED_MASK) |
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203 | #define SET_IW_F2X6L10_A(V) (((V) & IW_F2X6L10_A_UNSHIFTED_MASK) << IW_F2X6L10_A_LSB) |
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204 | |||
205 | #define IW_F2X6L10_B_LSB 11 |
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206 | #define IW_F2X6L10_B_SIZE 5 |
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207 | #define IW_F2X6L10_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X6L10_B_SIZE)) |
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208 | #define IW_F2X6L10_B_SHIFTED_MASK (IW_F2X6L10_B_UNSHIFTED_MASK << IW_F2X6L10_B_LSB) |
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209 | #define GET_IW_F2X6L10_B(W) (((W) >> IW_F2X6L10_B_LSB) & IW_F2X6L10_B_UNSHIFTED_MASK) |
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210 | #define SET_IW_F2X6L10_B(V) (((V) & IW_F2X6L10_B_UNSHIFTED_MASK) << IW_F2X6L10_B_LSB) |
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211 | |||
212 | #define IW_F2X6L10_LSB_LSB 16 |
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213 | #define IW_F2X6L10_LSB_SIZE 5 |
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214 | #define IW_F2X6L10_LSB_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X6L10_LSB_SIZE)) |
||
215 | #define IW_F2X6L10_LSB_SHIFTED_MASK (IW_F2X6L10_LSB_UNSHIFTED_MASK << IW_F2X6L10_LSB_LSB) |
||
216 | #define GET_IW_F2X6L10_LSB(W) (((W) >> IW_F2X6L10_LSB_LSB) & IW_F2X6L10_LSB_UNSHIFTED_MASK) |
||
217 | #define SET_IW_F2X6L10_LSB(V) (((V) & IW_F2X6L10_LSB_UNSHIFTED_MASK) << IW_F2X6L10_LSB_LSB) |
||
218 | |||
219 | #define IW_F2X6L10_MSB_LSB 21 |
||
220 | #define IW_F2X6L10_MSB_SIZE 5 |
||
221 | #define IW_F2X6L10_MSB_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2X6L10_MSB_SIZE)) |
||
222 | #define IW_F2X6L10_MSB_SHIFTED_MASK (IW_F2X6L10_MSB_UNSHIFTED_MASK << IW_F2X6L10_MSB_LSB) |
||
223 | #define GET_IW_F2X6L10_MSB(W) (((W) >> IW_F2X6L10_MSB_LSB) & IW_F2X6L10_MSB_UNSHIFTED_MASK) |
||
224 | #define SET_IW_F2X6L10_MSB(V) (((V) & IW_F2X6L10_MSB_UNSHIFTED_MASK) << IW_F2X6L10_MSB_LSB) |
||
225 | |||
226 | #define IW_F3X8_A_LSB 6 |
||
227 | #define IW_F3X8_A_SIZE 5 |
||
228 | #define IW_F3X8_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_A_SIZE)) |
||
229 | #define IW_F3X8_A_SHIFTED_MASK (IW_F3X8_A_UNSHIFTED_MASK << IW_F3X8_A_LSB) |
||
230 | #define GET_IW_F3X8_A(W) (((W) >> IW_F3X8_A_LSB) & IW_F3X8_A_UNSHIFTED_MASK) |
||
231 | #define SET_IW_F3X8_A(V) (((V) & IW_F3X8_A_UNSHIFTED_MASK) << IW_F3X8_A_LSB) |
||
232 | |||
233 | #define IW_F3X8_B_LSB 11 |
||
234 | #define IW_F3X8_B_SIZE 5 |
||
235 | #define IW_F3X8_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_B_SIZE)) |
||
236 | #define IW_F3X8_B_SHIFTED_MASK (IW_F3X8_B_UNSHIFTED_MASK << IW_F3X8_B_LSB) |
||
237 | #define GET_IW_F3X8_B(W) (((W) >> IW_F3X8_B_LSB) & IW_F3X8_B_UNSHIFTED_MASK) |
||
238 | #define SET_IW_F3X8_B(V) (((V) & IW_F3X8_B_UNSHIFTED_MASK) << IW_F3X8_B_LSB) |
||
239 | |||
240 | #define IW_F3X8_C_LSB 16 |
||
241 | #define IW_F3X8_C_SIZE 5 |
||
242 | #define IW_F3X8_C_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_C_SIZE)) |
||
243 | #define IW_F3X8_C_SHIFTED_MASK (IW_F3X8_C_UNSHIFTED_MASK << IW_F3X8_C_LSB) |
||
244 | #define GET_IW_F3X8_C(W) (((W) >> IW_F3X8_C_LSB) & IW_F3X8_C_UNSHIFTED_MASK) |
||
245 | #define SET_IW_F3X8_C(V) (((V) & IW_F3X8_C_UNSHIFTED_MASK) << IW_F3X8_C_LSB) |
||
246 | |||
247 | #define IW_F3X8_READA_LSB 21 |
||
248 | #define IW_F3X8_READA_SIZE 1 |
||
249 | #define IW_F3X8_READA_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_READA_SIZE)) |
||
250 | #define IW_F3X8_READA_SHIFTED_MASK (IW_F3X8_READA_UNSHIFTED_MASK << IW_F3X8_READA_LSB) |
||
251 | #define GET_IW_F3X8_READA(W) (((W) >> IW_F3X8_READA_LSB) & IW_F3X8_READA_UNSHIFTED_MASK) |
||
252 | #define SET_IW_F3X8_READA(V) (((V) & IW_F3X8_READA_UNSHIFTED_MASK) << IW_F3X8_READA_LSB) |
||
253 | |||
254 | #define IW_F3X8_READB_LSB 22 |
||
255 | #define IW_F3X8_READB_SIZE 1 |
||
256 | #define IW_F3X8_READB_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_READB_SIZE)) |
||
257 | #define IW_F3X8_READB_SHIFTED_MASK (IW_F3X8_READB_UNSHIFTED_MASK << IW_F3X8_READB_LSB) |
||
258 | #define GET_IW_F3X8_READB(W) (((W) >> IW_F3X8_READB_LSB) & IW_F3X8_READB_UNSHIFTED_MASK) |
||
259 | #define SET_IW_F3X8_READB(V) (((V) & IW_F3X8_READB_UNSHIFTED_MASK) << IW_F3X8_READB_LSB) |
||
260 | |||
261 | #define IW_F3X8_READC_LSB 23 |
||
262 | #define IW_F3X8_READC_SIZE 1 |
||
263 | #define IW_F3X8_READC_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_READC_SIZE)) |
||
264 | #define IW_F3X8_READC_SHIFTED_MASK (IW_F3X8_READC_UNSHIFTED_MASK << IW_F3X8_READC_LSB) |
||
265 | #define GET_IW_F3X8_READC(W) (((W) >> IW_F3X8_READC_LSB) & IW_F3X8_READC_UNSHIFTED_MASK) |
||
266 | #define SET_IW_F3X8_READC(V) (((V) & IW_F3X8_READC_UNSHIFTED_MASK) << IW_F3X8_READC_LSB) |
||
267 | |||
268 | #define IW_F3X8_N_LSB 24 |
||
269 | #define IW_F3X8_N_SIZE 8 |
||
270 | #define IW_F3X8_N_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F3X8_N_SIZE)) |
||
271 | #define IW_F3X8_N_SHIFTED_MASK (IW_F3X8_N_UNSHIFTED_MASK << IW_F3X8_N_LSB) |
||
272 | #define GET_IW_F3X8_N(W) (((W) >> IW_F3X8_N_LSB) & IW_F3X8_N_UNSHIFTED_MASK) |
||
273 | #define SET_IW_F3X8_N(V) (((V) & IW_F3X8_N_UNSHIFTED_MASK) << IW_F3X8_N_LSB) |
||
274 | |||
275 | /* 16-bit R2 fields. */ |
||
276 | |||
277 | #define IW_I10_IMM10_LSB 6 |
||
278 | #define IW_I10_IMM10_SIZE 10 |
||
279 | #define IW_I10_IMM10_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_I10_IMM10_SIZE)) |
||
280 | #define IW_I10_IMM10_SHIFTED_MASK (IW_I10_IMM10_UNSHIFTED_MASK << IW_I10_IMM10_LSB) |
||
281 | #define GET_IW_I10_IMM10(W) (((W) >> IW_I10_IMM10_LSB) & IW_I10_IMM10_UNSHIFTED_MASK) |
||
282 | #define SET_IW_I10_IMM10(V) (((V) & IW_I10_IMM10_UNSHIFTED_MASK) << IW_I10_IMM10_LSB) |
||
283 | |||
284 | #define IW_T1I7_A3_LSB 6 |
||
285 | #define IW_T1I7_A3_SIZE 3 |
||
286 | #define IW_T1I7_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T1I7_A3_SIZE)) |
||
287 | #define IW_T1I7_A3_SHIFTED_MASK (IW_T1I7_A3_UNSHIFTED_MASK << IW_T1I7_A3_LSB) |
||
288 | #define GET_IW_T1I7_A3(W) (((W) >> IW_T1I7_A3_LSB) & IW_T1I7_A3_UNSHIFTED_MASK) |
||
289 | #define SET_IW_T1I7_A3(V) (((V) & IW_T1I7_A3_UNSHIFTED_MASK) << IW_T1I7_A3_LSB) |
||
290 | |||
291 | #define IW_T1I7_IMM7_LSB 9 |
||
292 | #define IW_T1I7_IMM7_SIZE 7 |
||
293 | #define IW_T1I7_IMM7_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T1I7_IMM7_SIZE)) |
||
294 | #define IW_T1I7_IMM7_SHIFTED_MASK (IW_T1I7_IMM7_UNSHIFTED_MASK << IW_T1I7_IMM7_LSB) |
||
295 | #define GET_IW_T1I7_IMM7(W) (((W) >> IW_T1I7_IMM7_LSB) & IW_T1I7_IMM7_UNSHIFTED_MASK) |
||
296 | #define SET_IW_T1I7_IMM7(V) (((V) & IW_T1I7_IMM7_UNSHIFTED_MASK) << IW_T1I7_IMM7_LSB) |
||
297 | |||
298 | #define IW_T2I4_A3_LSB 6 |
||
299 | #define IW_T2I4_A3_SIZE 3 |
||
300 | #define IW_T2I4_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2I4_A3_SIZE)) |
||
301 | #define IW_T2I4_A3_SHIFTED_MASK (IW_T2I4_A3_UNSHIFTED_MASK << IW_T2I4_A3_LSB) |
||
302 | #define GET_IW_T2I4_A3(W) (((W) >> IW_T2I4_A3_LSB) & IW_T2I4_A3_UNSHIFTED_MASK) |
||
303 | #define SET_IW_T2I4_A3(V) (((V) & IW_T2I4_A3_UNSHIFTED_MASK) << IW_T2I4_A3_LSB) |
||
304 | |||
305 | #define IW_T2I4_B3_LSB 9 |
||
306 | #define IW_T2I4_B3_SIZE 3 |
||
307 | #define IW_T2I4_B3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2I4_B3_SIZE)) |
||
308 | #define IW_T2I4_B3_SHIFTED_MASK (IW_T2I4_B3_UNSHIFTED_MASK << IW_T2I4_B3_LSB) |
||
309 | #define GET_IW_T2I4_B3(W) (((W) >> IW_T2I4_B3_LSB) & IW_T2I4_B3_UNSHIFTED_MASK) |
||
310 | #define SET_IW_T2I4_B3(V) (((V) & IW_T2I4_B3_UNSHIFTED_MASK) << IW_T2I4_B3_LSB) |
||
311 | |||
312 | #define IW_T2I4_IMM4_LSB 12 |
||
313 | #define IW_T2I4_IMM4_SIZE 4 |
||
314 | #define IW_T2I4_IMM4_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2I4_IMM4_SIZE)) |
||
315 | #define IW_T2I4_IMM4_SHIFTED_MASK (IW_T2I4_IMM4_UNSHIFTED_MASK << IW_T2I4_IMM4_LSB) |
||
316 | #define GET_IW_T2I4_IMM4(W) (((W) >> IW_T2I4_IMM4_LSB) & IW_T2I4_IMM4_UNSHIFTED_MASK) |
||
317 | #define SET_IW_T2I4_IMM4(V) (((V) & IW_T2I4_IMM4_UNSHIFTED_MASK) << IW_T2I4_IMM4_LSB) |
||
318 | |||
319 | #define IW_T1X1I6_A3_LSB 6 |
||
320 | #define IW_T1X1I6_A3_SIZE 3 |
||
321 | #define IW_T1X1I6_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T1X1I6_A3_SIZE)) |
||
322 | #define IW_T1X1I6_A3_SHIFTED_MASK (IW_T1X1I6_A3_UNSHIFTED_MASK << IW_T1X1I6_A3_LSB) |
||
323 | #define GET_IW_T1X1I6_A3(W) (((W) >> IW_T1X1I6_A3_LSB) & IW_T1X1I6_A3_UNSHIFTED_MASK) |
||
324 | #define SET_IW_T1X1I6_A3(V) (((V) & IW_T1X1I6_A3_UNSHIFTED_MASK) << IW_T1X1I6_A3_LSB) |
||
325 | |||
326 | #define IW_T1X1I6_IMM6_LSB 9 |
||
327 | #define IW_T1X1I6_IMM6_SIZE 6 |
||
328 | #define IW_T1X1I6_IMM6_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T1X1I6_IMM6_SIZE)) |
||
329 | #define IW_T1X1I6_IMM6_SHIFTED_MASK (IW_T1X1I6_IMM6_UNSHIFTED_MASK << IW_T1X1I6_IMM6_LSB) |
||
330 | #define GET_IW_T1X1I6_IMM6(W) (((W) >> IW_T1X1I6_IMM6_LSB) & IW_T1X1I6_IMM6_UNSHIFTED_MASK) |
||
331 | #define SET_IW_T1X1I6_IMM6(V) (((V) & IW_T1X1I6_IMM6_UNSHIFTED_MASK) << IW_T1X1I6_IMM6_LSB) |
||
332 | |||
333 | #define IW_T1X1I6_X_LSB 15 |
||
334 | #define IW_T1X1I6_X_SIZE 1 |
||
335 | #define IW_T1X1I6_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T1X1I6_X_SIZE)) |
||
336 | #define IW_T1X1I6_X_SHIFTED_MASK (IW_T1X1I6_X_UNSHIFTED_MASK << IW_T1X1I6_X_LSB) |
||
337 | #define GET_IW_T1X1I6_X(W) (((W) >> IW_T1X1I6_X_LSB) & IW_T1X1I6_X_UNSHIFTED_MASK) |
||
338 | #define SET_IW_T1X1I6_X(V) (((V) & IW_T1X1I6_X_UNSHIFTED_MASK) << IW_T1X1I6_X_LSB) |
||
339 | |||
340 | #define IW_X1I7_IMM7_LSB 6 |
||
341 | #define IW_X1I7_IMM7_SIZE 7 |
||
342 | #define IW_X1I7_IMM7_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_X1I7_IMM7_SIZE)) |
||
343 | #define IW_X1I7_IMM7_SHIFTED_MASK (IW_X1I7_IMM7_UNSHIFTED_MASK << IW_X1I7_IMM7_LSB) |
||
344 | #define GET_IW_X1I7_IMM7(W) (((W) >> IW_X1I7_IMM7_LSB) & IW_X1I7_IMM7_UNSHIFTED_MASK) |
||
345 | #define SET_IW_X1I7_IMM7(V) (((V) & IW_X1I7_IMM7_UNSHIFTED_MASK) << IW_X1I7_IMM7_LSB) |
||
346 | |||
347 | #define IW_X1I7_RSV_LSB 13 |
||
348 | #define IW_X1I7_RSV_SIZE 2 |
||
349 | #define IW_X1I7_RSV_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_X1I7_RSV_SIZE)) |
||
350 | #define IW_X1I7_RSV_SHIFTED_MASK (IW_X1I7_RSV_UNSHIFTED_MASK << IW_X1I7_RSV_LSB) |
||
351 | #define GET_IW_X1I7_RSV(W) (((W) >> IW_X1I7_RSV_LSB) & IW_X1I7_RSV_UNSHIFTED_MASK) |
||
352 | #define SET_IW_X1I7_RSV(V) (((V) & IW_X1I7_RSV_UNSHIFTED_MASK) << IW_X1I7_RSV_LSB) |
||
353 | |||
354 | #define IW_X1I7_X_LSB 15 |
||
355 | #define IW_X1I7_X_SIZE 1 |
||
356 | #define IW_X1I7_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_X1I7_X_SIZE)) |
||
357 | #define IW_X1I7_X_SHIFTED_MASK (IW_X1I7_X_UNSHIFTED_MASK << IW_X1I7_X_LSB) |
||
358 | #define GET_IW_X1I7_X(W) (((W) >> IW_X1I7_X_LSB) & IW_X1I7_X_UNSHIFTED_MASK) |
||
359 | #define SET_IW_X1I7_X(V) (((V) & IW_X1I7_X_UNSHIFTED_MASK) << IW_X1I7_X_LSB) |
||
360 | |||
361 | #define IW_L5I4X1_IMM4_LSB 6 |
||
362 | #define IW_L5I4X1_IMM4_SIZE 4 |
||
363 | #define IW_L5I4X1_IMM4_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L5I4X1_IMM4_SIZE)) |
||
364 | #define IW_L5I4X1_IMM4_SHIFTED_MASK (IW_L5I4X1_IMM4_UNSHIFTED_MASK << IW_L5I4X1_IMM4_LSB) |
||
365 | #define GET_IW_L5I4X1_IMM4(W) (((W) >> IW_L5I4X1_IMM4_LSB) & IW_L5I4X1_IMM4_UNSHIFTED_MASK) |
||
366 | #define SET_IW_L5I4X1_IMM4(V) (((V) & IW_L5I4X1_IMM4_UNSHIFTED_MASK) << IW_L5I4X1_IMM4_LSB) |
||
367 | |||
368 | #define IW_L5I4X1_REGRANGE_LSB 10 |
||
369 | #define IW_L5I4X1_REGRANGE_SIZE 3 |
||
370 | #define IW_L5I4X1_REGRANGE_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L5I4X1_REGRANGE_SIZE)) |
||
371 | #define IW_L5I4X1_REGRANGE_SHIFTED_MASK (IW_L5I4X1_REGRANGE_UNSHIFTED_MASK << IW_L5I4X1_REGRANGE_LSB) |
||
372 | #define GET_IW_L5I4X1_REGRANGE(W) (((W) >> IW_L5I4X1_REGRANGE_LSB) & IW_L5I4X1_REGRANGE_UNSHIFTED_MASK) |
||
373 | #define SET_IW_L5I4X1_REGRANGE(V) (((V) & IW_L5I4X1_REGRANGE_UNSHIFTED_MASK) << IW_L5I4X1_REGRANGE_LSB) |
||
374 | |||
375 | #define IW_L5I4X1_FP_LSB 13 |
||
376 | #define IW_L5I4X1_FP_SIZE 1 |
||
377 | #define IW_L5I4X1_FP_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L5I4X1_FP_SIZE)) |
||
378 | #define IW_L5I4X1_FP_SHIFTED_MASK (IW_L5I4X1_FP_UNSHIFTED_MASK << IW_L5I4X1_FP_LSB) |
||
379 | #define GET_IW_L5I4X1_FP(W) (((W) >> IW_L5I4X1_FP_LSB) & IW_L5I4X1_FP_UNSHIFTED_MASK) |
||
380 | #define SET_IW_L5I4X1_FP(V) (((V) & IW_L5I4X1_FP_UNSHIFTED_MASK) << IW_L5I4X1_FP_LSB) |
||
381 | |||
382 | #define IW_L5I4X1_CS_LSB 14 |
||
383 | #define IW_L5I4X1_CS_SIZE 1 |
||
384 | #define IW_L5I4X1_CS_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L5I4X1_CS_SIZE)) |
||
385 | #define IW_L5I4X1_CS_SHIFTED_MASK (IW_L5I4X1_CS_UNSHIFTED_MASK << IW_L5I4X1_CS_LSB) |
||
386 | #define GET_IW_L5I4X1_CS(W) (((W) >> IW_L5I4X1_CS_LSB) & IW_L5I4X1_CS_UNSHIFTED_MASK) |
||
387 | #define SET_IW_L5I4X1_CS(V) (((V) & IW_L5I4X1_CS_UNSHIFTED_MASK) << IW_L5I4X1_CS_LSB) |
||
388 | |||
389 | #define IW_L5I4X1_X_LSB 15 |
||
390 | #define IW_L5I4X1_X_SIZE 1 |
||
391 | #define IW_L5I4X1_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_L5I4X1_X_SIZE)) |
||
392 | #define IW_L5I4X1_X_SHIFTED_MASK (IW_L5I4X1_X_UNSHIFTED_MASK << IW_L5I4X1_X_LSB) |
||
393 | #define GET_IW_L5I4X1_X(W) (((W) >> IW_L5I4X1_X_LSB) & IW_L5I4X1_X_UNSHIFTED_MASK) |
||
394 | #define SET_IW_L5I4X1_X(V) (((V) & IW_L5I4X1_X_UNSHIFTED_MASK) << IW_L5I4X1_X_LSB) |
||
395 | |||
396 | #define IW_T2X1L3_A3_LSB 6 |
||
397 | #define IW_T2X1L3_A3_SIZE 3 |
||
398 | #define IW_T2X1L3_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1L3_A3_SIZE)) |
||
399 | #define IW_T2X1L3_A3_SHIFTED_MASK (IW_T2X1L3_A3_UNSHIFTED_MASK << IW_T2X1L3_A3_LSB) |
||
400 | #define GET_IW_T2X1L3_A3(W) (((W) >> IW_T2X1L3_A3_LSB) & IW_T2X1L3_A3_UNSHIFTED_MASK) |
||
401 | #define SET_IW_T2X1L3_A3(V) (((V) & IW_T2X1L3_A3_UNSHIFTED_MASK) << IW_T2X1L3_A3_LSB) |
||
402 | |||
403 | #define IW_T2X1L3_B3_LSB 9 |
||
404 | #define IW_T2X1L3_B3_SIZE 3 |
||
405 | #define IW_T2X1L3_B3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1L3_B3_SIZE)) |
||
406 | #define IW_T2X1L3_B3_SHIFTED_MASK (IW_T2X1L3_B3_UNSHIFTED_MASK << IW_T2X1L3_B3_LSB) |
||
407 | #define GET_IW_T2X1L3_B3(W) (((W) >> IW_T2X1L3_B3_LSB) & IW_T2X1L3_B3_UNSHIFTED_MASK) |
||
408 | #define SET_IW_T2X1L3_B3(V) (((V) & IW_T2X1L3_B3_UNSHIFTED_MASK) << IW_T2X1L3_B3_LSB) |
||
409 | |||
410 | #define IW_T2X1L3_SHAMT_LSB 12 |
||
411 | #define IW_T2X1L3_SHAMT_SIZE 3 |
||
412 | #define IW_T2X1L3_SHAMT_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1L3_SHAMT_SIZE)) |
||
413 | #define IW_T2X1L3_SHAMT_SHIFTED_MASK (IW_T2X1L3_SHAMT_UNSHIFTED_MASK << IW_T2X1L3_SHAMT_LSB) |
||
414 | #define GET_IW_T2X1L3_SHAMT(W) (((W) >> IW_T2X1L3_SHAMT_LSB) & IW_T2X1L3_SHAMT_UNSHIFTED_MASK) |
||
415 | #define SET_IW_T2X1L3_SHAMT(V) (((V) & IW_T2X1L3_SHAMT_UNSHIFTED_MASK) << IW_T2X1L3_SHAMT_LSB) |
||
416 | |||
417 | #define IW_T2X1L3_X_LSB 15 |
||
418 | #define IW_T2X1L3_X_SIZE 1 |
||
419 | #define IW_T2X1L3_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1L3_X_SIZE)) |
||
420 | #define IW_T2X1L3_X_SHIFTED_MASK (IW_T2X1L3_X_UNSHIFTED_MASK << IW_T2X1L3_X_LSB) |
||
421 | #define GET_IW_T2X1L3_X(W) (((W) >> IW_T2X1L3_X_LSB) & IW_T2X1L3_X_UNSHIFTED_MASK) |
||
422 | #define SET_IW_T2X1L3_X(V) (((V) & IW_T2X1L3_X_UNSHIFTED_MASK) << IW_T2X1L3_X_LSB) |
||
423 | |||
424 | #define IW_T2X1I3_A3_LSB 6 |
||
425 | #define IW_T2X1I3_A3_SIZE 3 |
||
426 | #define IW_T2X1I3_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1I3_A3_SIZE)) |
||
427 | #define IW_T2X1I3_A3_SHIFTED_MASK (IW_T2X1I3_A3_UNSHIFTED_MASK << IW_T2X1I3_A3_LSB) |
||
428 | #define GET_IW_T2X1I3_A3(W) (((W) >> IW_T2X1I3_A3_LSB) & IW_T2X1I3_A3_UNSHIFTED_MASK) |
||
429 | #define SET_IW_T2X1I3_A3(V) (((V) & IW_T2X1I3_A3_UNSHIFTED_MASK) << IW_T2X1I3_A3_LSB) |
||
430 | |||
431 | #define IW_T2X1I3_B3_LSB 9 |
||
432 | #define IW_T2X1I3_B3_SIZE 3 |
||
433 | #define IW_T2X1I3_B3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1I3_B3_SIZE)) |
||
434 | #define IW_T2X1I3_B3_SHIFTED_MASK (IW_T2X1I3_B3_UNSHIFTED_MASK << IW_T2X1I3_B3_LSB) |
||
435 | #define GET_IW_T2X1I3_B3(W) (((W) >> IW_T2X1I3_B3_LSB) & IW_T2X1I3_B3_UNSHIFTED_MASK) |
||
436 | #define SET_IW_T2X1I3_B3(V) (((V) & IW_T2X1I3_B3_UNSHIFTED_MASK) << IW_T2X1I3_B3_LSB) |
||
437 | |||
438 | #define IW_T2X1I3_IMM3_LSB 12 |
||
439 | #define IW_T2X1I3_IMM3_SIZE 3 |
||
440 | #define IW_T2X1I3_IMM3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1I3_IMM3_SIZE)) |
||
441 | #define IW_T2X1I3_IMM3_SHIFTED_MASK (IW_T2X1I3_IMM3_UNSHIFTED_MASK << IW_T2X1I3_IMM3_LSB) |
||
442 | #define GET_IW_T2X1I3_IMM3(W) (((W) >> IW_T2X1I3_IMM3_LSB) & IW_T2X1I3_IMM3_UNSHIFTED_MASK) |
||
443 | #define SET_IW_T2X1I3_IMM3(V) (((V) & IW_T2X1I3_IMM3_UNSHIFTED_MASK) << IW_T2X1I3_IMM3_LSB) |
||
444 | |||
445 | #define IW_T2X1I3_X_LSB 15 |
||
446 | #define IW_T2X1I3_X_SIZE 1 |
||
447 | #define IW_T2X1I3_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X1I3_X_SIZE)) |
||
448 | #define IW_T2X1I3_X_SHIFTED_MASK (IW_T2X1I3_X_UNSHIFTED_MASK << IW_T2X1I3_X_LSB) |
||
449 | #define GET_IW_T2X1I3_X(W) (((W) >> IW_T2X1I3_X_LSB) & IW_T2X1I3_X_UNSHIFTED_MASK) |
||
450 | #define SET_IW_T2X1I3_X(V) (((V) & IW_T2X1I3_X_UNSHIFTED_MASK) << IW_T2X1I3_X_LSB) |
||
451 | |||
452 | #define IW_T3X1_A3_LSB 6 |
||
453 | #define IW_T3X1_A3_SIZE 3 |
||
454 | #define IW_T3X1_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T3X1_A3_SIZE)) |
||
455 | #define IW_T3X1_A3_SHIFTED_MASK (IW_T3X1_A3_UNSHIFTED_MASK << IW_T3X1_A3_LSB) |
||
456 | #define GET_IW_T3X1_A3(W) (((W) >> IW_T3X1_A3_LSB) & IW_T3X1_A3_UNSHIFTED_MASK) |
||
457 | #define SET_IW_T3X1_A3(V) (((V) & IW_T3X1_A3_UNSHIFTED_MASK) << IW_T3X1_A3_LSB) |
||
458 | |||
459 | #define IW_T3X1_B3_LSB 9 |
||
460 | #define IW_T3X1_B3_SIZE 3 |
||
461 | #define IW_T3X1_B3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T3X1_B3_SIZE)) |
||
462 | #define IW_T3X1_B3_SHIFTED_MASK (IW_T3X1_B3_UNSHIFTED_MASK << IW_T3X1_B3_LSB) |
||
463 | #define GET_IW_T3X1_B3(W) (((W) >> IW_T3X1_B3_LSB) & IW_T3X1_B3_UNSHIFTED_MASK) |
||
464 | #define SET_IW_T3X1_B3(V) (((V) & IW_T3X1_B3_UNSHIFTED_MASK) << IW_T3X1_B3_LSB) |
||
465 | |||
466 | #define IW_T3X1_C3_LSB 12 |
||
467 | #define IW_T3X1_C3_SIZE 3 |
||
468 | #define IW_T3X1_C3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T3X1_C3_SIZE)) |
||
469 | #define IW_T3X1_C3_SHIFTED_MASK (IW_T3X1_C3_UNSHIFTED_MASK << IW_T3X1_C3_LSB) |
||
470 | #define GET_IW_T3X1_C3(W) (((W) >> IW_T3X1_C3_LSB) & IW_T3X1_C3_UNSHIFTED_MASK) |
||
471 | #define SET_IW_T3X1_C3(V) (((V) & IW_T3X1_C3_UNSHIFTED_MASK) << IW_T3X1_C3_LSB) |
||
472 | |||
473 | #define IW_T3X1_X_LSB 15 |
||
474 | #define IW_T3X1_X_SIZE 1 |
||
475 | #define IW_T3X1_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T3X1_X_SIZE)) |
||
476 | #define IW_T3X1_X_SHIFTED_MASK (IW_T3X1_X_UNSHIFTED_MASK << IW_T3X1_X_LSB) |
||
477 | #define GET_IW_T3X1_X(W) (((W) >> IW_T3X1_X_LSB) & IW_T3X1_X_UNSHIFTED_MASK) |
||
478 | #define SET_IW_T3X1_X(V) (((V) & IW_T3X1_X_UNSHIFTED_MASK) << IW_T3X1_X_LSB) |
||
479 | |||
480 | /* The X field for all three R.N-class instruction formats is represented |
||
481 | here as 4 bits, including the bits defined as constant 0 or 1 that |
||
482 | determine which of the formats T2X3, F1X1, or X2L5 it is. */ |
||
483 | #define IW_R_N_X_LSB 12 |
||
484 | #define IW_R_N_X_SIZE 4 |
||
485 | #define IW_R_N_X_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_R_N_X_SIZE)) |
||
486 | #define IW_R_N_X_SHIFTED_MASK (IW_R_N_X_UNSHIFTED_MASK << IW_R_N_X_LSB) |
||
487 | #define GET_IW_R_N_X(W) (((W) >> IW_R_N_X_LSB) & IW_R_N_X_UNSHIFTED_MASK) |
||
488 | #define SET_IW_R_N_X(V) (((V) & IW_R_N_X_UNSHIFTED_MASK) << IW_R_N_X_LSB) |
||
489 | |||
490 | #define IW_T2X3_A3_LSB 6 |
||
491 | #define IW_T2X3_A3_SIZE 3 |
||
492 | #define IW_T2X3_A3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X3_A3_SIZE)) |
||
493 | #define IW_T2X3_A3_SHIFTED_MASK (IW_T2X3_A3_UNSHIFTED_MASK << IW_T2X3_A3_LSB) |
||
494 | #define GET_IW_T2X3_A3(W) (((W) >> IW_T2X3_A3_LSB) & IW_T2X3_A3_UNSHIFTED_MASK) |
||
495 | #define SET_IW_T2X3_A3(V) (((V) & IW_T2X3_A3_UNSHIFTED_MASK) << IW_T2X3_A3_LSB) |
||
496 | |||
497 | #define IW_T2X3_B3_LSB 9 |
||
498 | #define IW_T2X3_B3_SIZE 3 |
||
499 | #define IW_T2X3_B3_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_T2X3_B3_SIZE)) |
||
500 | #define IW_T2X3_B3_SHIFTED_MASK (IW_T2X3_B3_UNSHIFTED_MASK << IW_T2X3_B3_LSB) |
||
501 | #define GET_IW_T2X3_B3(W) (((W) >> IW_T2X3_B3_LSB) & IW_T2X3_B3_UNSHIFTED_MASK) |
||
502 | #define SET_IW_T2X3_B3(V) (((V) & IW_T2X3_B3_UNSHIFTED_MASK) << IW_T2X3_B3_LSB) |
||
503 | |||
504 | #define IW_F1X1_A_LSB 6 |
||
505 | #define IW_F1X1_A_SIZE 5 |
||
506 | #define IW_F1X1_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X1_A_SIZE)) |
||
507 | #define IW_F1X1_A_SHIFTED_MASK (IW_F1X1_A_UNSHIFTED_MASK << IW_F1X1_A_LSB) |
||
508 | #define GET_IW_F1X1_A(W) (((W) >> IW_F1X1_A_LSB) & IW_F1X1_A_UNSHIFTED_MASK) |
||
509 | #define SET_IW_F1X1_A(V) (((V) & IW_F1X1_A_UNSHIFTED_MASK) << IW_F1X1_A_LSB) |
||
510 | |||
511 | #define IW_F1X1_RSV_LSB 11 |
||
512 | #define IW_F1X1_RSV_SIZE 1 |
||
513 | #define IW_F1X1_RSV_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1X1_RSV_SIZE)) |
||
514 | #define IW_F1X1_RSV_SHIFTED_MASK (IW_F1X1_RSV_UNSHIFTED_MASK << IW_F1X1_RSV_LSB) |
||
515 | #define GET_IW_F1X1_RSV(W) (((W) >> IW_F1X1_RSV_LSB) & IW_F1X1_RSV_UNSHIFTED_MASK) |
||
516 | #define SET_IW_F1X1_RSV(V) (((V) & IW_F1X1_RSV_UNSHIFTED_MASK) << IW_F1X1_RSV_LSB) |
||
517 | |||
518 | #define IW_X2L5_IMM5_LSB 6 |
||
519 | #define IW_X2L5_IMM5_SIZE 5 |
||
520 | #define IW_X2L5_IMM5_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_X2L5_IMM5_SIZE)) |
||
521 | #define IW_X2L5_IMM5_SHIFTED_MASK (IW_X2L5_IMM5_UNSHIFTED_MASK << IW_X2L5_IMM5_LSB) |
||
522 | #define GET_IW_X2L5_IMM5(W) (((W) >> IW_X2L5_IMM5_LSB) & IW_X2L5_IMM5_UNSHIFTED_MASK) |
||
523 | #define SET_IW_X2L5_IMM5(V) (((V) & IW_X2L5_IMM5_UNSHIFTED_MASK) << IW_X2L5_IMM5_LSB) |
||
524 | |||
525 | #define IW_X2L5_RSV_LSB 11 |
||
526 | #define IW_X2L5_RSV_SIZE 1 |
||
527 | #define IW_X2L5_RSV_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_X2L5_RSV_SIZE)) |
||
528 | #define IW_X2L5_RSV_SHIFTED_MASK (IW_X2L5_RSV_UNSHIFTED_MASK << IW_X2L5_RSV_LSB) |
||
529 | #define GET_IW_X2L5_RSV(W) (((W) >> IW_X2L5_RSV_LSB) & IW_X2L5_RSV_UNSHIFTED_MASK) |
||
530 | #define SET_IW_X2L5_RSV(V) (((V) & IW_X2L5_RSV_UNSHIFTED_MASK) << IW_X2L5_RSV_LSB) |
||
531 | |||
532 | #define IW_F1I5_IMM5_LSB 6 |
||
533 | #define IW_F1I5_IMM5_SIZE 5 |
||
534 | #define IW_F1I5_IMM5_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1I5_IMM5_SIZE)) |
||
535 | #define IW_F1I5_IMM5_SHIFTED_MASK (IW_F1I5_IMM5_UNSHIFTED_MASK << IW_F1I5_IMM5_LSB) |
||
536 | #define GET_IW_F1I5_IMM5(W) (((W) >> IW_F1I5_IMM5_LSB) & IW_F1I5_IMM5_UNSHIFTED_MASK) |
||
537 | #define SET_IW_F1I5_IMM5(V) (((V) & IW_F1I5_IMM5_UNSHIFTED_MASK) << IW_F1I5_IMM5_LSB) |
||
538 | |||
539 | #define IW_F1I5_B_LSB 11 |
||
540 | #define IW_F1I5_B_SIZE 5 |
||
541 | #define IW_F1I5_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F1I5_B_SIZE)) |
||
542 | #define IW_F1I5_B_SHIFTED_MASK (IW_F1I5_B_UNSHIFTED_MASK << IW_F1I5_B_LSB) |
||
543 | #define GET_IW_F1I5_B(W) (((W) >> IW_F1I5_B_LSB) & IW_F1I5_B_UNSHIFTED_MASK) |
||
544 | #define SET_IW_F1I5_B(V) (((V) & IW_F1I5_B_UNSHIFTED_MASK) << IW_F1I5_B_LSB) |
||
545 | |||
546 | #define IW_F2_A_LSB 6 |
||
547 | #define IW_F2_A_SIZE 5 |
||
548 | #define IW_F2_A_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2_A_SIZE)) |
||
549 | #define IW_F2_A_SHIFTED_MASK (IW_F2_A_UNSHIFTED_MASK << IW_F2_A_LSB) |
||
550 | #define GET_IW_F2_A(W) (((W) >> IW_F2_A_LSB) & IW_F2_A_UNSHIFTED_MASK) |
||
551 | #define SET_IW_F2_A(V) (((V) & IW_F2_A_UNSHIFTED_MASK) << IW_F2_A_LSB) |
||
552 | |||
553 | #define IW_F2_B_LSB 11 |
||
554 | #define IW_F2_B_SIZE 5 |
||
555 | #define IW_F2_B_UNSHIFTED_MASK (0xffffffffu >> (32 - IW_F2_B_SIZE)) |
||
556 | #define IW_F2_B_SHIFTED_MASK (IW_F2_B_UNSHIFTED_MASK << IW_F2_B_LSB) |
||
557 | #define GET_IW_F2_B(W) (((W) >> IW_F2_B_LSB) & IW_F2_B_UNSHIFTED_MASK) |
||
558 | #define SET_IW_F2_B(V) (((V) & IW_F2_B_UNSHIFTED_MASK) << IW_F2_B_LSB) |
||
559 | |||
560 | /* R2 opcodes. */ |
||
561 | #define R2_OP_CALL 0 |
||
562 | #define R2_OP_AS_N 1 |
||
563 | #define R2_OP_BR 2 |
||
564 | #define R2_OP_BR_N 3 |
||
565 | #define R2_OP_ADDI 4 |
||
566 | #define R2_OP_LDBU_N 5 |
||
567 | #define R2_OP_LDBU 6 |
||
568 | #define R2_OP_LDB 7 |
||
569 | #define R2_OP_JMPI 8 |
||
570 | #define R2_OP_R_N 9 |
||
571 | #define R2_OP_ANDI_N 11 |
||
572 | #define R2_OP_ANDI 12 |
||
573 | #define R2_OP_LDHU_N 13 |
||
574 | #define R2_OP_LDHU 14 |
||
575 | #define R2_OP_LDH 15 |
||
576 | #define R2_OP_ASI_N 17 |
||
577 | #define R2_OP_BGE 18 |
||
578 | #define R2_OP_LDWSP_N 19 |
||
579 | #define R2_OP_ORI 20 |
||
580 | #define R2_OP_LDW_N 21 |
||
581 | #define R2_OP_CMPGEI 22 |
||
582 | #define R2_OP_LDW 23 |
||
583 | #define R2_OP_SHI_N 25 |
||
584 | #define R2_OP_BLT 26 |
||
585 | #define R2_OP_MOVI_N 27 |
||
586 | #define R2_OP_XORI 28 |
||
587 | #define R2_OP_STZ_N 29 |
||
588 | #define R2_OP_CMPLTI 30 |
||
589 | #define R2_OP_ANDCI 31 |
||
590 | #define R2_OP_OPX 32 |
||
591 | #define R2_OP_PP_N 33 |
||
592 | #define R2_OP_BNE 34 |
||
593 | #define R2_OP_BNEZ_N 35 |
||
594 | #define R2_OP_MULI 36 |
||
595 | #define R2_OP_STB_N 37 |
||
596 | #define R2_OP_CMPNEI 38 |
||
597 | #define R2_OP_STB 39 |
||
598 | #define R2_OP_I12 40 |
||
599 | #define R2_OP_SPI_N 41 |
||
600 | #define R2_OP_BEQ 42 |
||
601 | #define R2_OP_BEQZ_N 43 |
||
602 | #define R2_OP_ANDHI 44 |
||
603 | #define R2_OP_STH_N 45 |
||
604 | #define R2_OP_CMPEQI 46 |
||
605 | #define R2_OP_STH 47 |
||
606 | #define R2_OP_CUSTOM 48 |
||
607 | #define R2_OP_BGEU 50 |
||
608 | #define R2_OP_STWSP_N 51 |
||
609 | #define R2_OP_ORHI 52 |
||
610 | #define R2_OP_STW_N 53 |
||
611 | #define R2_OP_CMPGEUI 54 |
||
612 | #define R2_OP_STW 55 |
||
613 | #define R2_OP_BLTU 58 |
||
614 | #define R2_OP_MOV_N 59 |
||
615 | #define R2_OP_XORHI 60 |
||
616 | #define R2_OP_SPADDI_N 61 |
||
617 | #define R2_OP_CMPLTUI 62 |
||
618 | #define R2_OP_ANDCHI 63 |
||
619 | |||
620 | #define R2_OPX_WRPIE 0 |
||
621 | #define R2_OPX_ERET 1 |
||
622 | #define R2_OPX_ROLI 2 |
||
623 | #define R2_OPX_ROL 3 |
||
624 | #define R2_OPX_FLUSHP 4 |
||
625 | #define R2_OPX_RET 5 |
||
626 | #define R2_OPX_NOR 6 |
||
627 | #define R2_OPX_MULXUU 7 |
||
628 | #define R2_OPX_ENI 8 |
||
629 | #define R2_OPX_BRET 9 |
||
630 | #define R2_OPX_ROR 11 |
||
631 | #define R2_OPX_FLUSHI 12 |
||
632 | #define R2_OPX_JMP 13 |
||
633 | #define R2_OPX_AND 14 |
||
634 | #define R2_OPX_CMPGE 16 |
||
635 | #define R2_OPX_SLLI 18 |
||
636 | #define R2_OPX_SLL 19 |
||
637 | #define R2_OPX_WRPRS 20 |
||
638 | #define R2_OPX_OR 22 |
||
639 | #define R2_OPX_MULXSU 23 |
||
640 | #define R2_OPX_CMPLT 24 |
||
641 | #define R2_OPX_SRLI 26 |
||
642 | #define R2_OPX_SRL 27 |
||
643 | #define R2_OPX_NEXTPC 28 |
||
644 | #define R2_OPX_CALLR 29 |
||
645 | #define R2_OPX_XOR 30 |
||
646 | #define R2_OPX_MULXSS 31 |
||
647 | #define R2_OPX_CMPNE 32 |
||
648 | #define R2_OPX_INSERT 35 |
||
649 | #define R2_OPX_DIVU 36 |
||
650 | #define R2_OPX_DIV 37 |
||
651 | #define R2_OPX_RDCTL 38 |
||
652 | #define R2_OPX_MUL 39 |
||
653 | #define R2_OPX_CMPEQ 40 |
||
654 | #define R2_OPX_INITI 41 |
||
655 | #define R2_OPX_MERGE 43 |
||
656 | #define R2_OPX_HBREAK 44 |
||
657 | #define R2_OPX_TRAP 45 |
||
658 | #define R2_OPX_WRCTL 46 |
||
659 | #define R2_OPX_CMPGEU 48 |
||
660 | #define R2_OPX_ADD 49 |
||
661 | #define R2_OPX_EXTRACT 51 |
||
662 | #define R2_OPX_BREAK 52 |
||
663 | #define R2_OPX_LDEX 53 |
||
664 | #define R2_OPX_SYNC 54 |
||
665 | #define R2_OPX_LDSEX 55 |
||
666 | #define R2_OPX_CMPLTU 56 |
||
667 | #define R2_OPX_SUB 57 |
||
668 | #define R2_OPX_SRAI 58 |
||
669 | #define R2_OPX_SRA 59 |
||
670 | #define R2_OPX_STEX 61 |
||
671 | #define R2_OPX_STSEX 63 |
||
672 | |||
673 | #define R2_I12_LDBIO 0 |
||
674 | #define R2_I12_STBIO 1 |
||
675 | #define R2_I12_LDBUIO 2 |
||
676 | #define R2_I12_DCACHE 3 |
||
677 | #define R2_I12_LDHIO 4 |
||
678 | #define R2_I12_STHIO 5 |
||
679 | #define R2_I12_LDHUIO 6 |
||
680 | #define R2_I12_RDPRS 7 |
||
681 | #define R2_I12_LDWIO 8 |
||
682 | #define R2_I12_STWIO 9 |
||
683 | #define R2_I12_LDWM 12 |
||
684 | #define R2_I12_STWM 13 |
||
685 | |||
686 | #define R2_DCACHE_INITD 0 |
||
687 | #define R2_DCACHE_INITDA 1 |
||
688 | #define R2_DCACHE_FLUSHD 2 |
||
689 | #define R2_DCACHE_FLUSHDA 3 |
||
690 | |||
691 | #define R2_AS_N_ADD_N 0 |
||
692 | #define R2_AS_N_SUB_N 1 |
||
693 | |||
694 | #define R2_R_N_AND_N 0 |
||
695 | #define R2_R_N_OR_N 2 |
||
696 | #define R2_R_N_XOR_N 3 |
||
697 | #define R2_R_N_SLL_N 4 |
||
698 | #define R2_R_N_SRL_N 5 |
||
699 | #define R2_R_N_NOT_N 6 |
||
700 | #define R2_R_N_NEG_N 7 |
||
701 | #define R2_R_N_CALLR_N 8 |
||
702 | #define R2_R_N_JMPR_N 10 |
||
703 | #define R2_R_N_BREAK_N 12 |
||
704 | #define R2_R_N_TRAP_N 13 |
||
705 | #define R2_R_N_RET_N 14 |
||
706 | |||
707 | #define R2_SPI_N_SPINCI_N 0 |
||
708 | #define R2_SPI_N_SPDECI_N 1 |
||
709 | |||
710 | #define R2_ASI_N_ADDI_N 0 |
||
711 | #define R2_ASI_N_SUBI_N 1 |
||
712 | |||
713 | #define R2_SHI_N_SLLI_N 0 |
||
714 | #define R2_SHI_N_SRLI_N 1 |
||
715 | |||
716 | #define R2_PP_N_POP_N 0 |
||
717 | #define R2_PP_N_PUSH_N 1 |
||
718 | |||
719 | #define R2_STZ_N_STWZ_N 0 |
||
720 | #define R2_STZ_N_STBZ_N 1 |
||
721 | |||
722 | /* Convenience macros for R2 encodings. */ |
||
723 | |||
724 | #define MATCH_R2_OP(NAME) \ |
||
725 | (SET_IW_R2_OP (R2_OP_##NAME)) |
||
726 | #define MASK_R2_OP \ |
||
727 | IW_R2_OP_SHIFTED_MASK |
||
728 | |||
729 | #define MATCH_R2_OPX0(NAME) \ |
||
730 | (SET_IW_R2_OP (R2_OP_OPX) | SET_IW_OPX_X (R2_OPX_##NAME)) |
||
731 | #define MASK_R2_OPX0 \ |
||
732 | (IW_R2_OP_SHIFTED_MASK | IW_OPX_X_SHIFTED_MASK \ |
||
733 | | IW_F3X6L5_IMM5_SHIFTED_MASK) |
||
734 | |||
735 | #define MATCH_R2_OPX(NAME, A, B, C) \ |
||
736 | (MATCH_R2_OPX0 (NAME) | SET_IW_F3X6L5_A (A) | SET_IW_F3X6L5_B (B) \ |
||
737 | | SET_IW_F3X6L5_C (C)) |
||
738 | #define MASK_R2_OPX(A, B, C, N) \ |
||
739 | (IW_R2_OP_SHIFTED_MASK | IW_OPX_X_SHIFTED_MASK \ |
||
740 | | (A ? IW_F3X6L5_A_SHIFTED_MASK : 0) \ |
||
741 | | (B ? IW_F3X6L5_B_SHIFTED_MASK : 0) \ |
||
742 | | (C ? IW_F3X6L5_C_SHIFTED_MASK : 0) \ |
||
743 | | (N ? IW_F3X6L5_IMM5_SHIFTED_MASK : 0)) |
||
744 | |||
745 | #define MATCH_R2_I12(NAME) \ |
||
746 | (SET_IW_R2_OP (R2_OP_I12) | SET_IW_I12_X (R2_I12_##NAME)) |
||
747 | #define MASK_R2_I12 \ |
||
748 | (IW_R2_OP_SHIFTED_MASK | IW_I12_X_SHIFTED_MASK ) |
||
749 | |||
750 | #define MATCH_R2_DCACHE(NAME) \ |
||
751 | (MATCH_R2_I12(DCACHE) | SET_IW_F1X4I12_X (R2_DCACHE_##NAME)) |
||
752 | #define MASK_R2_DCACHE \ |
||
753 | (MASK_R2_I12 | IW_F1X4I12_X_SHIFTED_MASK) |
||
754 | |||
755 | #define MATCH_R2_R_N(NAME) \ |
||
756 | (SET_IW_R2_OP (R2_OP_R_N) | SET_IW_R_N_X (R2_R_N_##NAME)) |
||
757 | #define MASK_R2_R_N \ |
||
758 | (IW_R2_OP_SHIFTED_MASK | IW_R_N_X_SHIFTED_MASK ) |
||
759 | |||
760 | /* Match/mask macros for R2 instructions. */ |
||
761 | |||
762 | #define MATCH_R2_ADD MATCH_R2_OPX0 (ADD) |
||
763 | #define MASK_R2_ADD MASK_R2_OPX0 |
||
764 | #define MATCH_R2_ADDI MATCH_R2_OP (ADDI) |
||
765 | #define MASK_R2_ADDI MASK_R2_OP |
||
766 | #define MATCH_R2_ADD_N (MATCH_R2_OP (AS_N) | SET_IW_T3X1_X (R2_AS_N_ADD_N)) |
||
767 | #define MASK_R2_ADD_N (MASK_R2_OP | IW_T3X1_X_SHIFTED_MASK) |
||
768 | #define MATCH_R2_ADDI_N (MATCH_R2_OP (ASI_N) | SET_IW_T2X1I3_X (R2_ASI_N_ADDI_N)) |
||
769 | #define MASK_R2_ADDI_N (MASK_R2_OP | IW_T2X1I3_X_SHIFTED_MASK) |
||
770 | #define MATCH_R2_AND MATCH_R2_OPX0 (AND) |
||
771 | #define MASK_R2_AND MASK_R2_OPX0 |
||
772 | #define MATCH_R2_ANDCHI MATCH_R2_OP (ANDCHI) |
||
773 | #define MASK_R2_ANDCHI MASK_R2_OP |
||
774 | #define MATCH_R2_ANDCI MATCH_R2_OP (ANDCI) |
||
775 | #define MASK_R2_ANDCI MASK_R2_OP |
||
776 | #define MATCH_R2_ANDHI MATCH_R2_OP (ANDHI) |
||
777 | #define MASK_R2_ANDHI MASK_R2_OP |
||
778 | #define MATCH_R2_ANDI MATCH_R2_OP (ANDI) |
||
779 | #define MASK_R2_ANDI MASK_R2_OP |
||
780 | #define MATCH_R2_ANDI_N MATCH_R2_OP (ANDI_N) |
||
781 | #define MASK_R2_ANDI_N MASK_R2_OP |
||
782 | #define MATCH_R2_AND_N MATCH_R2_R_N (AND_N) |
||
783 | #define MASK_R2_AND_N MASK_R2_R_N |
||
784 | #define MATCH_R2_BEQ MATCH_R2_OP (BEQ) |
||
785 | #define MASK_R2_BEQ MASK_R2_OP |
||
786 | #define MATCH_R2_BEQZ_N MATCH_R2_OP (BEQZ_N) |
||
787 | #define MASK_R2_BEQZ_N MASK_R2_OP |
||
788 | #define MATCH_R2_BGE MATCH_R2_OP (BGE) |
||
789 | #define MASK_R2_BGE MASK_R2_OP |
||
790 | #define MATCH_R2_BGEU MATCH_R2_OP (BGEU) |
||
791 | #define MASK_R2_BGEU MASK_R2_OP |
||
792 | #define MATCH_R2_BGT MATCH_R2_OP (BLT) |
||
793 | #define MASK_R2_BGT MASK_R2_OP |
||
794 | #define MATCH_R2_BGTU MATCH_R2_OP (BLTU) |
||
795 | #define MASK_R2_BGTU MASK_R2_OP |
||
796 | #define MATCH_R2_BLE MATCH_R2_OP (BGE) |
||
797 | #define MASK_R2_BLE MASK_R2_OP |
||
798 | #define MATCH_R2_BLEU MATCH_R2_OP (BGEU) |
||
799 | #define MASK_R2_BLEU MASK_R2_OP |
||
800 | #define MATCH_R2_BLT MATCH_R2_OP (BLT) |
||
801 | #define MASK_R2_BLT MASK_R2_OP |
||
802 | #define MATCH_R2_BLTU MATCH_R2_OP (BLTU) |
||
803 | #define MASK_R2_BLTU MASK_R2_OP |
||
804 | #define MATCH_R2_BNE MATCH_R2_OP (BNE) |
||
805 | #define MASK_R2_BNE MASK_R2_OP |
||
806 | #define MATCH_R2_BNEZ_N MATCH_R2_OP (BNEZ_N) |
||
807 | #define MASK_R2_BNEZ_N MASK_R2_OP |
||
808 | #define MATCH_R2_BR MATCH_R2_OP (BR) |
||
809 | #define MASK_R2_BR MASK_R2_OP | IW_F2I16_A_SHIFTED_MASK | IW_F2I16_B_SHIFTED_MASK |
||
810 | #define MATCH_R2_BREAK MATCH_R2_OPX (BREAK, 0, 0, 0x1e) |
||
811 | #define MASK_R2_BREAK MASK_R2_OPX (1, 1, 1, 0) |
||
812 | #define MATCH_R2_BREAK_N MATCH_R2_R_N (BREAK_N) |
||
813 | #define MASK_R2_BREAK_N MASK_R2_R_N |
||
814 | #define MATCH_R2_BRET MATCH_R2_OPX (BRET, 0x1e, 0, 0) |
||
815 | #define MASK_R2_BRET MASK_R2_OPX (1, 1, 1, 1) |
||
816 | #define MATCH_R2_BR_N MATCH_R2_OP (BR_N) |
||
817 | #define MASK_R2_BR_N MASK_R2_OP |
||
818 | #define MATCH_R2_CALL MATCH_R2_OP (CALL) |
||
819 | #define MASK_R2_CALL MASK_R2_OP |
||
820 | #define MATCH_R2_CALLR MATCH_R2_OPX (CALLR, 0, 0, 0x1f) |
||
821 | #define MASK_R2_CALLR MASK_R2_OPX (0, 1, 1, 1) |
||
822 | #define MATCH_R2_CALLR_N MATCH_R2_R_N (CALLR_N) |
||
823 | #define MASK_R2_CALLR_N MASK_R2_R_N |
||
824 | #define MATCH_R2_CMPEQ MATCH_R2_OPX0 (CMPEQ) |
||
825 | #define MASK_R2_CMPEQ MASK_R2_OPX0 |
||
826 | #define MATCH_R2_CMPEQI MATCH_R2_OP (CMPEQI) |
||
827 | #define MASK_R2_CMPEQI MASK_R2_OP |
||
828 | #define MATCH_R2_CMPGE MATCH_R2_OPX0 (CMPGE) |
||
829 | #define MASK_R2_CMPGE MASK_R2_OPX0 |
||
830 | #define MATCH_R2_CMPGEI MATCH_R2_OP (CMPGEI) |
||
831 | #define MASK_R2_CMPGEI MASK_R2_OP |
||
832 | #define MATCH_R2_CMPGEU MATCH_R2_OPX0 (CMPGEU) |
||
833 | #define MASK_R2_CMPGEU MASK_R2_OPX0 |
||
834 | #define MATCH_R2_CMPGEUI MATCH_R2_OP (CMPGEUI) |
||
835 | #define MASK_R2_CMPGEUI MASK_R2_OP |
||
836 | #define MATCH_R2_CMPGT MATCH_R2_OPX0 (CMPLT) |
||
837 | #define MASK_R2_CMPGT MASK_R2_OPX0 |
||
838 | #define MATCH_R2_CMPGTI MATCH_R2_OP (CMPGEI) |
||
839 | #define MASK_R2_CMPGTI MASK_R2_OP |
||
840 | #define MATCH_R2_CMPGTU MATCH_R2_OPX0 (CMPLTU) |
||
841 | #define MASK_R2_CMPGTU MASK_R2_OPX0 |
||
842 | #define MATCH_R2_CMPGTUI MATCH_R2_OP (CMPGEUI) |
||
843 | #define MASK_R2_CMPGTUI MASK_R2_OP |
||
844 | #define MATCH_R2_CMPLE MATCH_R2_OPX0 (CMPGE) |
||
845 | #define MASK_R2_CMPLE MASK_R2_OPX0 |
||
846 | #define MATCH_R2_CMPLEI MATCH_R2_OP (CMPLTI) |
||
847 | #define MASK_R2_CMPLEI MASK_R2_OP |
||
848 | #define MATCH_R2_CMPLEU MATCH_R2_OPX0 (CMPGEU) |
||
849 | #define MASK_R2_CMPLEU MASK_R2_OPX0 |
||
850 | #define MATCH_R2_CMPLEUI MATCH_R2_OP (CMPLTUI) |
||
851 | #define MASK_R2_CMPLEUI MASK_R2_OP |
||
852 | #define MATCH_R2_CMPLT MATCH_R2_OPX0 (CMPLT) |
||
853 | #define MASK_R2_CMPLT MASK_R2_OPX0 |
||
854 | #define MATCH_R2_CMPLTI MATCH_R2_OP (CMPLTI) |
||
855 | #define MASK_R2_CMPLTI MASK_R2_OP |
||
856 | #define MATCH_R2_CMPLTU MATCH_R2_OPX0 (CMPLTU) |
||
857 | #define MASK_R2_CMPLTU MASK_R2_OPX0 |
||
858 | #define MATCH_R2_CMPLTUI MATCH_R2_OP (CMPLTUI) |
||
859 | #define MASK_R2_CMPLTUI MASK_R2_OP |
||
860 | #define MATCH_R2_CMPNE MATCH_R2_OPX0 (CMPNE) |
||
861 | #define MASK_R2_CMPNE MASK_R2_OPX0 |
||
862 | #define MATCH_R2_CMPNEI MATCH_R2_OP (CMPNEI) |
||
863 | #define MASK_R2_CMPNEI MASK_R2_OP |
||
864 | #define MATCH_R2_CUSTOM MATCH_R2_OP (CUSTOM) |
||
865 | #define MASK_R2_CUSTOM MASK_R2_OP |
||
866 | #define MATCH_R2_DIV MATCH_R2_OPX0 (DIV) |
||
867 | #define MASK_R2_DIV MASK_R2_OPX0 |
||
868 | #define MATCH_R2_DIVU MATCH_R2_OPX0 (DIVU) |
||
869 | #define MASK_R2_DIVU MASK_R2_OPX0 |
||
870 | #define MATCH_R2_ENI MATCH_R2_OPX (ENI, 0, 0, 0) |
||
871 | #define MASK_R2_ENI MASK_R2_OPX (1, 1, 1, 0) |
||
872 | #define MATCH_R2_ERET MATCH_R2_OPX (ERET, 0x1d, 0x1e, 0) |
||
873 | #define MASK_R2_ERET MASK_R2_OPX (1, 1, 1, 1) |
||
874 | #define MATCH_R2_EXTRACT MATCH_R2_OPX (EXTRACT, 0, 0, 0) |
||
875 | #define MASK_R2_EXTRACT MASK_R2_OPX (0, 0, 0, 0) |
||
876 | #define MATCH_R2_FLUSHD MATCH_R2_DCACHE (FLUSHD) |
||
877 | #define MASK_R2_FLUSHD MASK_R2_DCACHE |
||
878 | #define MATCH_R2_FLUSHDA MATCH_R2_DCACHE (FLUSHDA) |
||
879 | #define MASK_R2_FLUSHDA MASK_R2_DCACHE |
||
880 | #define MATCH_R2_FLUSHI MATCH_R2_OPX (FLUSHI, 0, 0, 0) |
||
881 | #define MASK_R2_FLUSHI MASK_R2_OPX (0, 1, 1, 1) |
||
882 | #define MATCH_R2_FLUSHP MATCH_R2_OPX (FLUSHP, 0, 0, 0) |
||
883 | #define MASK_R2_FLUSHP MASK_R2_OPX (1, 1, 1, 1) |
||
884 | #define MATCH_R2_INITD MATCH_R2_DCACHE (INITD) |
||
885 | #define MASK_R2_INITD MASK_R2_DCACHE |
||
886 | #define MATCH_R2_INITDA MATCH_R2_DCACHE (INITDA) |
||
887 | #define MASK_R2_INITDA MASK_R2_DCACHE |
||
888 | #define MATCH_R2_INITI MATCH_R2_OPX (INITI, 0, 0, 0) |
||
889 | #define MASK_R2_INITI MASK_R2_OPX (0, 1, 1, 1) |
||
890 | #define MATCH_R2_INSERT MATCH_R2_OPX (INSERT, 0, 0, 0) |
||
891 | #define MASK_R2_INSERT MASK_R2_OPX (0, 0, 0, 0) |
||
892 | #define MATCH_R2_JMP MATCH_R2_OPX (JMP, 0, 0, 0) |
||
893 | #define MASK_R2_JMP MASK_R2_OPX (0, 1, 1, 1) |
||
894 | #define MATCH_R2_JMPI MATCH_R2_OP (JMPI) |
||
895 | #define MASK_R2_JMPI MASK_R2_OP |
||
896 | #define MATCH_R2_JMPR_N MATCH_R2_R_N (JMPR_N) |
||
897 | #define MASK_R2_JMPR_N MASK_R2_R_N |
||
898 | #define MATCH_R2_LDB MATCH_R2_OP (LDB) |
||
899 | #define MASK_R2_LDB MASK_R2_OP |
||
900 | #define MATCH_R2_LDBIO MATCH_R2_I12 (LDBIO) |
||
901 | #define MASK_R2_LDBIO MASK_R2_I12 |
||
902 | #define MATCH_R2_LDBU MATCH_R2_OP (LDBU) |
||
903 | #define MASK_R2_LDBU MASK_R2_OP |
||
904 | #define MATCH_R2_LDBUIO MATCH_R2_I12 (LDBUIO) |
||
905 | #define MASK_R2_LDBUIO MASK_R2_I12 |
||
906 | #define MATCH_R2_LDBU_N MATCH_R2_OP (LDBU_N) |
||
907 | #define MASK_R2_LDBU_N MASK_R2_OP |
||
908 | #define MATCH_R2_LDEX MATCH_R2_OPX (LDEX, 0, 0, 0) |
||
909 | #define MASK_R2_LDEX MASK_R2_OPX (0, 1, 0, 1) |
||
910 | #define MATCH_R2_LDH MATCH_R2_OP (LDH) |
||
911 | #define MASK_R2_LDH MASK_R2_OP |
||
912 | #define MATCH_R2_LDHIO MATCH_R2_I12 (LDHIO) |
||
913 | #define MASK_R2_LDHIO MASK_R2_I12 |
||
914 | #define MATCH_R2_LDHU MATCH_R2_OP (LDHU) |
||
915 | #define MASK_R2_LDHU MASK_R2_OP |
||
916 | #define MATCH_R2_LDHUIO MATCH_R2_I12 (LDHUIO) |
||
917 | #define MASK_R2_LDHUIO MASK_R2_I12 |
||
918 | #define MATCH_R2_LDHU_N MATCH_R2_OP (LDHU_N) |
||
919 | #define MASK_R2_LDHU_N MASK_R2_OP |
||
920 | #define MATCH_R2_LDSEX MATCH_R2_OPX (LDSEX, 0, 0, 0) |
||
921 | #define MASK_R2_LDSEX MASK_R2_OPX (0, 1, 0, 1) |
||
922 | #define MATCH_R2_LDW MATCH_R2_OP (LDW) |
||
923 | #define MASK_R2_LDW MASK_R2_OP |
||
924 | #define MATCH_R2_LDWIO MATCH_R2_I12 (LDWIO) |
||
925 | #define MASK_R2_LDWIO MASK_R2_I12 |
||
926 | #define MATCH_R2_LDWM MATCH_R2_I12 (LDWM) |
||
927 | #define MASK_R2_LDWM MASK_R2_I12 |
||
928 | #define MATCH_R2_LDWSP_N MATCH_R2_OP (LDWSP_N) |
||
929 | #define MASK_R2_LDWSP_N MASK_R2_OP |
||
930 | #define MATCH_R2_LDW_N MATCH_R2_OP (LDW_N) |
||
931 | #define MASK_R2_LDW_N MASK_R2_OP |
||
932 | #define MATCH_R2_MERGE MATCH_R2_OPX (MERGE, 0, 0, 0) |
||
933 | #define MASK_R2_MERGE MASK_R2_OPX (0, 0, 0, 0) |
||
934 | #define MATCH_R2_MOV MATCH_R2_OPX (ADD, 0, 0, 0) |
||
935 | #define MASK_R2_MOV MASK_R2_OPX (0, 1, 0, 1) |
||
936 | #define MATCH_R2_MOVHI MATCH_R2_OP (ORHI) | SET_IW_F2I16_A (0) |
||
937 | #define MASK_R2_MOVHI MASK_R2_OP | IW_F2I16_A_SHIFTED_MASK |
||
938 | #define MATCH_R2_MOVI MATCH_R2_OP (ADDI) | SET_IW_F2I16_A (0) |
||
939 | #define MASK_R2_MOVI MASK_R2_OP | IW_F2I16_A_SHIFTED_MASK |
||
940 | #define MATCH_R2_MOVUI MATCH_R2_OP (ORI) | SET_IW_F2I16_A (0) |
||
941 | #define MASK_R2_MOVUI MASK_R2_OP | IW_F2I16_A_SHIFTED_MASK |
||
942 | #define MATCH_R2_MOV_N MATCH_R2_OP (MOV_N) |
||
943 | #define MASK_R2_MOV_N MASK_R2_OP |
||
944 | #define MATCH_R2_MOVI_N MATCH_R2_OP (MOVI_N) |
||
945 | #define MASK_R2_MOVI_N MASK_R2_OP |
||
946 | #define MATCH_R2_MUL MATCH_R2_OPX0 (MUL) |
||
947 | #define MASK_R2_MUL MASK_R2_OPX0 |
||
948 | #define MATCH_R2_MULI MATCH_R2_OP (MULI) |
||
949 | #define MASK_R2_MULI MASK_R2_OP |
||
950 | #define MATCH_R2_MULXSS MATCH_R2_OPX0 (MULXSS) |
||
951 | #define MASK_R2_MULXSS MASK_R2_OPX0 |
||
952 | #define MATCH_R2_MULXSU MATCH_R2_OPX0 (MULXSU) |
||
953 | #define MASK_R2_MULXSU MASK_R2_OPX0 |
||
954 | #define MATCH_R2_MULXUU MATCH_R2_OPX0 (MULXUU) |
||
955 | #define MASK_R2_MULXUU MASK_R2_OPX0 |
||
956 | #define MATCH_R2_NEG_N MATCH_R2_R_N (NEG_N) |
||
957 | #define MASK_R2_NEG_N MASK_R2_R_N |
||
958 | #define MATCH_R2_NEXTPC MATCH_R2_OPX (NEXTPC, 0, 0, 0) |
||
959 | #define MASK_R2_NEXTPC MASK_R2_OPX (1, 1, 0, 1) |
||
960 | #define MATCH_R2_NOP MATCH_R2_OPX (ADD, 0, 0, 0) |
||
961 | #define MASK_R2_NOP MASK_R2_OPX (1, 1, 1, 1) |
||
962 | #define MATCH_R2_NOP_N (MATCH_R2_OP (MOV_N) | SET_IW_F2_A (0) | SET_IW_F2_B (0)) |
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963 | #define MASK_R2_NOP_N (MASK_R2_OP | IW_F2_A_SHIFTED_MASK | IW_F2_B_SHIFTED_MASK) |
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964 | #define MATCH_R2_NOR MATCH_R2_OPX0 (NOR) |
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965 | #define MASK_R2_NOR MASK_R2_OPX0 |
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966 | #define MATCH_R2_NOT_N MATCH_R2_R_N (NOT_N) |
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967 | #define MASK_R2_NOT_N MASK_R2_R_N |
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968 | #define MATCH_R2_OR MATCH_R2_OPX0 (OR) |
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969 | #define MASK_R2_OR MASK_R2_OPX0 |
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970 | #define MATCH_R2_OR_N MATCH_R2_R_N (OR_N) |
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971 | #define MASK_R2_OR_N MASK_R2_R_N |
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972 | #define MATCH_R2_ORHI MATCH_R2_OP (ORHI) |
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973 | #define MASK_R2_ORHI MASK_R2_OP |
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974 | #define MATCH_R2_ORI MATCH_R2_OP (ORI) |
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975 | #define MASK_R2_ORI MASK_R2_OP |
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976 | #define MATCH_R2_POP_N (MATCH_R2_OP (PP_N) | SET_IW_L5I4X1_X (R2_PP_N_POP_N)) |
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977 | #define MASK_R2_POP_N (MASK_R2_OP | IW_L5I4X1_X_SHIFTED_MASK) |
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978 | #define MATCH_R2_PUSH_N (MATCH_R2_OP (PP_N) | SET_IW_L5I4X1_X (R2_PP_N_PUSH_N)) |
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979 | #define MASK_R2_PUSH_N (MASK_R2_OP | IW_L5I4X1_X_SHIFTED_MASK) |
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980 | #define MATCH_R2_RDCTL MATCH_R2_OPX (RDCTL, 0, 0, 0) |
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981 | #define MASK_R2_RDCTL MASK_R2_OPX (1, 1, 0, 0) |
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982 | #define MATCH_R2_RDPRS MATCH_R2_I12 (RDPRS) |
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983 | #define MASK_R2_RDPRS MASK_R2_I12 |
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984 | #define MATCH_R2_RET MATCH_R2_OPX (RET, 0x1f, 0, 0) |
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985 | #define MASK_R2_RET MASK_R2_OPX (1, 1, 1, 1) |
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986 | #define MATCH_R2_RET_N (MATCH_R2_R_N (RET_N) | SET_IW_X2L5_IMM5 (0)) |
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987 | #define MASK_R2_RET_N (MASK_R2_R_N | IW_X2L5_IMM5_SHIFTED_MASK) |
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988 | #define MATCH_R2_ROL MATCH_R2_OPX0 (ROL) |
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989 | #define MASK_R2_ROL MASK_R2_OPX0 |
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990 | #define MATCH_R2_ROLI MATCH_R2_OPX (ROLI, 0, 0, 0) |
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991 | #define MASK_R2_ROLI MASK_R2_OPX (0, 1, 0, 0) |
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992 | #define MATCH_R2_ROR MATCH_R2_OPX0 (ROR) |
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993 | #define MASK_R2_ROR MASK_R2_OPX0 |
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994 | #define MATCH_R2_SLL MATCH_R2_OPX0 (SLL) |
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995 | #define MASK_R2_SLL MASK_R2_OPX0 |
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996 | #define MATCH_R2_SLLI MATCH_R2_OPX (SLLI, 0, 0, 0) |
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997 | #define MASK_R2_SLLI MASK_R2_OPX (0, 1, 0, 0) |
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998 | #define MATCH_R2_SLL_N MATCH_R2_R_N (SLL_N) |
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999 | #define MASK_R2_SLL_N MASK_R2_R_N |
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1000 | #define MATCH_R2_SLLI_N (MATCH_R2_OP (SHI_N) | SET_IW_T2X1L3_X (R2_SHI_N_SLLI_N)) |
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1001 | #define MASK_R2_SLLI_N (MASK_R2_OP | IW_T2X1L3_X_SHIFTED_MASK) |
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1002 | #define MATCH_R2_SPADDI_N MATCH_R2_OP (SPADDI_N) |
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1003 | #define MASK_R2_SPADDI_N MASK_R2_OP |
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1004 | #define MATCH_R2_SPDECI_N (MATCH_R2_OP (SPI_N) | SET_IW_X1I7_X (R2_SPI_N_SPDECI_N)) |
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1005 | #define MASK_R2_SPDECI_N (MASK_R2_OP | IW_X1I7_X_SHIFTED_MASK) |
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1006 | #define MATCH_R2_SPINCI_N (MATCH_R2_OP (SPI_N) | SET_IW_X1I7_X (R2_SPI_N_SPINCI_N)) |
||
1007 | #define MASK_R2_SPINCI_N (MASK_R2_OP | IW_X1I7_X_SHIFTED_MASK) |
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1008 | #define MATCH_R2_SRA MATCH_R2_OPX0 (SRA) |
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1009 | #define MASK_R2_SRA MASK_R2_OPX0 |
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1010 | #define MATCH_R2_SRAI MATCH_R2_OPX (SRAI, 0, 0, 0) |
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1011 | #define MASK_R2_SRAI MASK_R2_OPX (0, 1, 0, 0) |
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1012 | #define MATCH_R2_SRL MATCH_R2_OPX0 (SRL) |
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1013 | #define MASK_R2_SRL MASK_R2_OPX0 |
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1014 | #define MATCH_R2_SRLI MATCH_R2_OPX (SRLI, 0, 0, 0) |
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1015 | #define MASK_R2_SRLI MASK_R2_OPX (0, 1, 0, 0) |
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1016 | #define MATCH_R2_SRL_N MATCH_R2_R_N (SRL_N) |
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1017 | #define MASK_R2_SRL_N MASK_R2_R_N |
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1018 | #define MATCH_R2_SRLI_N (MATCH_R2_OP (SHI_N) | SET_IW_T2X1L3_X (R2_SHI_N_SRLI_N)) |
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1019 | #define MASK_R2_SRLI_N (MASK_R2_OP | IW_T2X1L3_X_SHIFTED_MASK) |
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1020 | #define MATCH_R2_STB MATCH_R2_OP (STB) |
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1021 | #define MASK_R2_STB MASK_R2_OP |
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1022 | #define MATCH_R2_STBIO MATCH_R2_I12 (STBIO) |
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1023 | #define MASK_R2_STBIO MASK_R2_I12 |
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1024 | #define MATCH_R2_STB_N MATCH_R2_OP (STB_N) |
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1025 | #define MASK_R2_STB_N MASK_R2_OP |
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1026 | #define MATCH_R2_STBZ_N (MATCH_R2_OP (STZ_N) | SET_IW_T1X1I6_X (R2_STZ_N_STBZ_N)) |
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1027 | #define MASK_R2_STBZ_N (MASK_R2_OP | IW_T1X1I6_X_SHIFTED_MASK) |
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1028 | #define MATCH_R2_STEX MATCH_R2_OPX0 (STEX) |
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1029 | #define MASK_R2_STEX MASK_R2_OPX0 |
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1030 | #define MATCH_R2_STH MATCH_R2_OP (STH) |
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1031 | #define MASK_R2_STH MASK_R2_OP |
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1032 | #define MATCH_R2_STHIO MATCH_R2_I12 (STHIO) |
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1033 | #define MASK_R2_STHIO MASK_R2_I12 |
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1034 | #define MATCH_R2_STH_N MATCH_R2_OP (STH_N) |
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1035 | #define MASK_R2_STH_N MASK_R2_OP |
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1036 | #define MATCH_R2_STSEX MATCH_R2_OPX0 (STSEX) |
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1037 | #define MASK_R2_STSEX MASK_R2_OPX0 |
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1038 | #define MATCH_R2_STW MATCH_R2_OP (STW) |
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1039 | #define MASK_R2_STW MASK_R2_OP |
||
1040 | #define MATCH_R2_STWIO MATCH_R2_I12 (STWIO) |
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1041 | #define MASK_R2_STWIO MASK_R2_I12 |
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1042 | #define MATCH_R2_STWM MATCH_R2_I12 (STWM) |
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1043 | #define MASK_R2_STWM MASK_R2_I12 |
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1044 | #define MATCH_R2_STWSP_N MATCH_R2_OP (STWSP_N) |
||
1045 | #define MASK_R2_STWSP_N MASK_R2_OP |
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1046 | #define MATCH_R2_STW_N MATCH_R2_OP (STW_N) |
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1047 | #define MASK_R2_STW_N MASK_R2_OP |
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1048 | #define MATCH_R2_STWZ_N MATCH_R2_OP (STZ_N) |
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1049 | #define MASK_R2_STWZ_N MASK_R2_OP |
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1050 | #define MATCH_R2_SUB MATCH_R2_OPX0 (SUB) |
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1051 | #define MASK_R2_SUB MASK_R2_OPX0 |
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1052 | #define MATCH_R2_SUBI MATCH_R2_OP (ADDI) |
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1053 | #define MASK_R2_SUBI MASK_R2_OP |
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1054 | #define MATCH_R2_SUB_N (MATCH_R2_OP (AS_N) | SET_IW_T3X1_X (R2_AS_N_SUB_N)) |
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1055 | #define MASK_R2_SUB_N (MASK_R2_OP | IW_T3X1_X_SHIFTED_MASK) |
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1056 | #define MATCH_R2_SUBI_N (MATCH_R2_OP (ASI_N) | SET_IW_T2X1I3_X (R2_ASI_N_SUBI_N)) |
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1057 | #define MASK_R2_SUBI_N (MASK_R2_OP | IW_T2X1I3_X_SHIFTED_MASK) |
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1058 | #define MATCH_R2_SYNC MATCH_R2_OPX (SYNC, 0, 0, 0) |
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1059 | #define MASK_R2_SYNC MASK_R2_OPX (1, 1, 1, 1) |
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1060 | #define MATCH_R2_TRAP MATCH_R2_OPX (TRAP, 0, 0, 0x1d) |
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1061 | #define MASK_R2_TRAP MASK_R2_OPX (1, 1, 1, 0) |
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1062 | #define MATCH_R2_TRAP_N MATCH_R2_R_N (TRAP_N) |
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1063 | #define MASK_R2_TRAP_N MASK_R2_R_N |
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1064 | #define MATCH_R2_WRCTL MATCH_R2_OPX (WRCTL, 0, 0, 0) |
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1065 | #define MASK_R2_WRCTL MASK_R2_OPX (0, 1, 1, 0) |
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1066 | #define MATCH_R2_WRPIE MATCH_R2_OPX (WRPIE, 0, 0, 0) |
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1067 | #define MASK_R2_WRPIE MASK_R2_OPX (0, 1, 0, 1) |
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1068 | #define MATCH_R2_WRPRS MATCH_R2_OPX (WRPRS, 0, 0, 0) |
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1069 | #define MASK_R2_WRPRS MASK_R2_OPX (0, 1, 0, 1) |
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1070 | #define MATCH_R2_XOR MATCH_R2_OPX0 (XOR) |
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1071 | #define MASK_R2_XOR MASK_R2_OPX0 |
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1072 | #define MATCH_R2_XORHI MATCH_R2_OP (XORHI) |
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1073 | #define MASK_R2_XORHI MASK_R2_OP |
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1074 | #define MATCH_R2_XORI MATCH_R2_OP (XORI) |
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1075 | #define MASK_R2_XORI MASK_R2_OP |
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1076 | #define MATCH_R2_XOR_N MATCH_R2_R_N (XOR_N) |
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1077 | #define MASK_R2_XOR_N MASK_R2_R_N |
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1078 | |||
1079 | #endif /* _NIOS2R2_H */><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |
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1080 |