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5191 | serge | 1 | /* ia64.h -- Header file for ia64 opcode table |
6324 | serge | 2 | Copyright (C) 1998-2015 Free Software Foundation, Inc. |
5191 | serge | 3 | Contributed by David Mosberger-Tang |
4 | |||
5 | This file is part of BFD, the Binary File Descriptor library. |
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6 | |||
7 | This program is free software; you can redistribute it and/or modify |
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8 | it under the terms of the GNU General Public License as published by |
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9 | the Free Software Foundation; either version 3 of the License, or |
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10 | (at your option) any later version. |
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11 | |||
12 | This program is distributed in the hope that it will be useful, |
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13 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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14 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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15 | GNU General Public License for more details. |
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16 | |||
17 | You should have received a copy of the GNU General Public License |
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18 | along with this program; if not, write to the Free Software Foundation, |
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19 | Inc., 51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA. */ |
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20 | |||
21 | #ifndef opcode_ia64_h |
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22 | #define opcode_ia64_h |
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23 | |||
24 | #include |
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25 | |||
26 | #include "bfd.h" |
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27 | |||
28 | |||
29 | typedef BFD_HOST_U_64_BIT ia64_insn; |
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30 | |||
31 | enum ia64_insn_type |
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32 | { |
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33 | IA64_TYPE_NIL = 0, /* illegal type */ |
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34 | IA64_TYPE_A, /* integer alu (I- or M-unit) */ |
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35 | IA64_TYPE_I, /* non-alu integer (I-unit) */ |
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36 | IA64_TYPE_M, /* memory (M-unit) */ |
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37 | IA64_TYPE_B, /* branch (B-unit) */ |
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38 | IA64_TYPE_F, /* floating-point (F-unit) */ |
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39 | IA64_TYPE_X, /* long encoding (X-unit) */ |
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40 | IA64_TYPE_DYN, /* Dynamic opcode */ |
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41 | IA64_NUM_TYPES |
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42 | }; |
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43 | |||
44 | enum ia64_unit |
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45 | { |
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46 | IA64_UNIT_NIL = 0, /* illegal unit */ |
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47 | IA64_UNIT_I, /* integer unit */ |
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48 | IA64_UNIT_M, /* memory unit */ |
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49 | IA64_UNIT_B, /* branching unit */ |
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50 | IA64_UNIT_F, /* floating-point unit */ |
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51 | IA64_UNIT_L, /* long "unit" */ |
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52 | IA64_UNIT_X, /* may be integer or branch unit */ |
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53 | IA64_NUM_UNITS |
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54 | }; |
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55 | |||
56 | /* Changes to this enumeration must be propagated to the operand table in |
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57 | bfd/cpu-ia64-opc.c |
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58 | */ |
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59 | enum ia64_opnd |
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60 | { |
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61 | IA64_OPND_NIL, /* no operand---MUST BE FIRST!*/ |
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62 | |||
63 | /* constants */ |
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64 | IA64_OPND_AR_CSD, /* application register csd (ar.csd) */ |
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65 | IA64_OPND_AR_CCV, /* application register ccv (ar.ccv) */ |
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66 | IA64_OPND_AR_PFS, /* application register pfs (ar.pfs) */ |
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67 | IA64_OPND_C1, /* the constant 1 */ |
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68 | IA64_OPND_C8, /* the constant 8 */ |
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69 | IA64_OPND_C16, /* the constant 16 */ |
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70 | IA64_OPND_GR0, /* gr0 */ |
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71 | IA64_OPND_IP, /* instruction pointer (ip) */ |
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72 | IA64_OPND_PR, /* predicate register (pr) */ |
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73 | IA64_OPND_PR_ROT, /* rotating predicate register (pr.rot) */ |
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74 | IA64_OPND_PSR, /* processor status register (psr) */ |
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75 | IA64_OPND_PSR_L, /* processor status register L (psr.l) */ |
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76 | IA64_OPND_PSR_UM, /* processor status register UM (psr.um) */ |
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77 | |||
78 | /* register operands: */ |
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79 | IA64_OPND_AR3, /* third application register # (bits 20-26) */ |
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80 | IA64_OPND_B1, /* branch register # (bits 6-8) */ |
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81 | IA64_OPND_B2, /* branch register # (bits 13-15) */ |
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82 | IA64_OPND_CR3, /* third control register # (bits 20-26) */ |
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83 | IA64_OPND_F1, /* first floating-point register # */ |
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84 | IA64_OPND_F2, /* second floating-point register # */ |
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85 | IA64_OPND_F3, /* third floating-point register # */ |
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86 | IA64_OPND_F4, /* fourth floating-point register # */ |
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87 | IA64_OPND_P1, /* first predicate # */ |
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88 | IA64_OPND_P2, /* second predicate # */ |
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89 | IA64_OPND_R1, /* first register # */ |
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90 | IA64_OPND_R2, /* second register # */ |
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91 | IA64_OPND_R3, /* third register # */ |
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92 | IA64_OPND_R3_2, /* third register # (limited to gr0-gr3) */ |
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93 | IA64_OPND_DAHR3, /* dahr reg # ( bits 23-25) */ |
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94 | |||
95 | /* memory operands: */ |
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96 | IA64_OPND_MR3, /* memory at addr of third register # */ |
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97 | |||
98 | /* indirect operands: */ |
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99 | IA64_OPND_CPUID_R3, /* cpuid[reg] */ |
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100 | IA64_OPND_DBR_R3, /* dbr[reg] */ |
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101 | IA64_OPND_DTR_R3, /* dtr[reg] */ |
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102 | IA64_OPND_ITR_R3, /* itr[reg] */ |
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103 | IA64_OPND_IBR_R3, /* ibr[reg] */ |
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104 | IA64_OPND_MSR_R3, /* msr[reg] */ |
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105 | IA64_OPND_PKR_R3, /* pkr[reg] */ |
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106 | IA64_OPND_PMC_R3, /* pmc[reg] */ |
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107 | IA64_OPND_PMD_R3, /* pmd[reg] */ |
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108 | IA64_OPND_DAHR_R3, /* dahr[reg] */ |
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109 | IA64_OPND_RR_R3, /* rr[reg] */ |
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110 | |||
111 | /* immediate operands: */ |
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112 | IA64_OPND_CCNT5, /* 5-bit count (31 - bits 20-24) */ |
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113 | IA64_OPND_CNT2a, /* 2-bit count (1 + bits 27-28) */ |
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114 | IA64_OPND_CNT2b, /* 2-bit count (bits 27-28): 1, 2, 3 */ |
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115 | IA64_OPND_CNT2c, /* 2-bit count (bits 30-31): 0, 7, 15, or 16 */ |
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116 | IA64_OPND_CNT5, /* 5-bit count (bits 14-18) */ |
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117 | IA64_OPND_CNT6, /* 6-bit count (bits 27-32) */ |
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118 | IA64_OPND_CPOS6a, /* 6-bit count (63 - bits 20-25) */ |
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119 | IA64_OPND_CPOS6b, /* 6-bit count (63 - bits 14-19) */ |
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120 | IA64_OPND_CPOS6c, /* 6-bit count (63 - bits 31-36) */ |
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121 | IA64_OPND_IMM1, /* signed 1-bit immediate (bit 36) */ |
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122 | IA64_OPND_IMMU2, /* unsigned 2-bit immediate (bits 13-14) */ |
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123 | IA64_OPND_IMMU5b, /* unsigned 5-bit immediate (32 + bits 14-18) */ |
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124 | IA64_OPND_IMMU7a, /* unsigned 7-bit immediate (bits 13-19) */ |
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125 | IA64_OPND_IMMU7b, /* unsigned 7-bit immediate (bits 20-26) */ |
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126 | IA64_OPND_SOF, /* 8-bit stack frame size */ |
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127 | IA64_OPND_SOL, /* 8-bit size of locals */ |
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128 | IA64_OPND_SOR, /* 6-bit number of rotating registers (scaled by 8) */ |
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129 | IA64_OPND_IMM8, /* signed 8-bit immediate (bits 13-19 & 36) */ |
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130 | IA64_OPND_IMM8U4, /* cmp4*u signed 8-bit immediate (bits 13-19 & 36) */ |
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131 | IA64_OPND_IMM8M1, /* signed 8-bit immediate -1 (bits 13-19 & 36) */ |
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132 | IA64_OPND_IMM8M1U4, /* cmp4*u signed 8-bit immediate -1 (bits 13-19 & 36)*/ |
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133 | IA64_OPND_IMM8M1U8, /* cmp*u signed 8-bit immediate -1 (bits 13-19 & 36) */ |
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134 | IA64_OPND_IMMU9, /* unsigned 9-bit immediate (bits 33-34, 20-26) */ |
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135 | IA64_OPND_IMM9a, /* signed 9-bit immediate (bits 6-12, 27, 36) */ |
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136 | IA64_OPND_IMM9b, /* signed 9-bit immediate (bits 13-19, 27, 36) */ |
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137 | IA64_OPND_IMM14, /* signed 14-bit immediate (bits 13-19, 27-32, 36) */ |
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138 | IA64_OPND_IMMU16, /* unsigned 16-bit immediate (bits 6-9, 12-22, 36) */ |
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139 | IA64_OPND_IMM17, /* signed 17-bit immediate (2*bits 6-12, 24-31, 36) */ |
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140 | IA64_OPND_IMMU19, /* unsigned 19-bit immediate (bits 6-9, 12-25, 36) */ |
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141 | IA64_OPND_IMMU21, /* unsigned 21-bit immediate (bits 6-25, 36) */ |
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142 | IA64_OPND_IMM22, /* signed 22-bit immediate (bits 13-19, 22-36) */ |
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143 | IA64_OPND_IMMU24, /* unsigned 24-bit immediate (bits 6-26, 31-32, 36) */ |
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144 | IA64_OPND_IMM44, /* signed 44-bit immediate (2^16*bits 6-32, 36) */ |
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145 | IA64_OPND_IMMU62, /* unsigned 62-bit immediate */ |
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146 | IA64_OPND_IMMU64, /* unsigned 64-bit immediate (lotsa bits...) */ |
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147 | IA64_OPND_INC3, /* signed 3-bit (bits 13-15): +/-1, 4, 8, 16 */ |
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148 | IA64_OPND_LEN4, /* 4-bit count (bits 27-30 + 1) */ |
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149 | IA64_OPND_LEN6, /* 6-bit count (bits 27-32 + 1) */ |
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150 | IA64_OPND_MBTYPE4, /* 4-bit mux type (bits 20-23) */ |
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151 | IA64_OPND_MHTYPE8, /* 8-bit mux type (bits 20-27) */ |
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152 | IA64_OPND_POS6, /* 6-bit count (bits 14-19) */ |
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153 | IA64_OPND_TAG13, /* signed 13-bit tag (ip + 16*bits 6-12, 33-34) */ |
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154 | IA64_OPND_TAG13b, /* signed 13-bit tag (ip + 16*bits 24-32) */ |
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155 | IA64_OPND_TGT25, /* signed 25-bit (ip + 16*bits 6-25, 36) */ |
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156 | IA64_OPND_TGT25b, /* signed 25-bit (ip + 16*bits 6-12, 20-32, 36) */ |
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157 | IA64_OPND_TGT25c, /* signed 25-bit (ip + 16*bits 13-32, 36) */ |
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158 | IA64_OPND_TGT64, /* 64-bit (ip + 16*bits 13-32, 36, 2-40(L)) */ |
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159 | IA64_OPND_LDXMOV, /* any symbol, generates R_IA64_LDXMOV. */ |
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160 | |||
161 | IA64_OPND_CNT6a, /* 6-bit count (bits 6-11) */ |
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162 | IA64_OPND_STRD5b, /* 5-bit stride (bits 13-17) */ |
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163 | |||
164 | IA64_OPND_COUNT /* # of operand types (MUST BE LAST!) */ |
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165 | }; |
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166 | |||
167 | enum ia64_dependency_mode |
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168 | { |
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169 | IA64_DV_RAW, |
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170 | IA64_DV_WAW, |
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171 | IA64_DV_WAR, |
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172 | }; |
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173 | |||
174 | enum ia64_dependency_semantics |
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175 | { |
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176 | IA64_DVS_NONE, |
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177 | IA64_DVS_IMPLIED, |
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178 | IA64_DVS_IMPLIEDF, |
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179 | IA64_DVS_DATA, |
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180 | IA64_DVS_INSTR, |
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181 | IA64_DVS_SPECIFIC, |
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182 | IA64_DVS_STOP, |
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183 | IA64_DVS_OTHER, |
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184 | }; |
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185 | |||
186 | enum ia64_resource_specifier |
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187 | { |
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188 | IA64_RS_ANY, |
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189 | IA64_RS_AR_K, |
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190 | IA64_RS_AR_UNAT, |
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191 | IA64_RS_AR, /* 8-15, 20, 22-23, 31, 33-35, 37-39, 41-43, 45-47, 67-111 */ |
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192 | IA64_RS_ARb, /* 48-63, 112-127 */ |
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193 | IA64_RS_BR, |
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194 | IA64_RS_CFM, |
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195 | IA64_RS_CPUID, |
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196 | IA64_RS_CR_IIB, |
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197 | IA64_RS_CR_IRR, |
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198 | IA64_RS_CR_LRR, |
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199 | IA64_RS_CR, /* 3-7,10-15,18,28-63,75-79,82-127 */ |
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200 | IA64_RS_DAHR, |
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201 | IA64_RS_DBR, |
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202 | IA64_RS_FR, |
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203 | IA64_RS_FRb, |
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204 | IA64_RS_GR0, |
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205 | IA64_RS_GR, |
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206 | IA64_RS_IBR, |
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207 | IA64_RS_INSERVICE, /* CR[EOI] or CR[IVR] */ |
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208 | IA64_RS_MSR, |
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209 | IA64_RS_PKR, |
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210 | IA64_RS_PMC, |
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211 | IA64_RS_PMD, |
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212 | IA64_RS_PR, /* non-rotating, 1-15 */ |
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213 | IA64_RS_PRr, /* rotating, 16-62 */ |
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214 | IA64_RS_PR63, |
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215 | IA64_RS_RR, |
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216 | |||
217 | IA64_RS_ARX, /* ARs not in RS_AR or RS_ARb */ |
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218 | IA64_RS_CRX, /* CRs not in RS_CR */ |
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219 | IA64_RS_PSR, /* PSR bits */ |
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220 | IA64_RS_RSE, /* implementation-specific RSE resources */ |
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221 | IA64_RS_AR_FPSR, |
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222 | |||
223 | }; |
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224 | |||
225 | enum ia64_rse_resource |
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226 | { |
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227 | IA64_RSE_N_STACKED_PHYS, |
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228 | IA64_RSE_BOF, |
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229 | IA64_RSE_STORE_REG, |
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230 | IA64_RSE_LOAD_REG, |
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231 | IA64_RSE_BSPLOAD, |
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232 | IA64_RSE_RNATBITINDEX, |
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233 | IA64_RSE_CFLE, |
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234 | IA64_RSE_NDIRTY, |
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235 | }; |
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236 | |||
237 | /* Information about a given resource dependency */ |
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238 | struct ia64_dependency |
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239 | { |
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240 | /* Name of the resource */ |
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241 | const char *name; |
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242 | /* Does this dependency need further specification? */ |
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243 | enum ia64_resource_specifier specifier; |
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244 | /* Mode of dependency */ |
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245 | enum ia64_dependency_mode mode; |
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246 | /* Dependency semantics */ |
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247 | enum ia64_dependency_semantics semantics; |
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248 | /* Register index, if applicable (distinguishes AR, CR, and PSR deps) */ |
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249 | #define REG_NONE (-1) |
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250 | int regindex; |
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251 | /* Special info on semantics */ |
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252 | const char *info; |
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253 | }; |
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254 | |||
255 | /* Two arrays of indexes into the ia64_dependency table. |
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256 | chks are dependencies to check for conflicts when an opcode is |
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257 | encountered; regs are dependencies to register (mark as used) when an |
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258 | opcode is used. chks correspond to readers (RAW) or writers (WAW or |
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259 | WAR) of a resource, while regs correspond to writers (RAW or WAW) and |
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260 | readers (WAR) of a resource. */ |
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261 | struct ia64_opcode_dependency |
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262 | { |
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263 | int nchks; |
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264 | const unsigned short *chks; |
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265 | int nregs; |
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266 | const unsigned short *regs; |
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267 | }; |
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268 | |||
269 | /* encode/extract the note/index for a dependency */ |
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270 | #define RDEP(N,X) (((N)<<11)|(X)) |
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271 | #define NOTE(X) (((X)>>11)&0x1F) |
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272 | #define DEP(X) ((X)&0x7FF) |
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273 | |||
274 | /* A template descriptor describes the execution units that are active |
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275 | for each of the three slots. It also specifies the location of |
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276 | instruction group boundaries that may be present between two slots. */ |
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277 | struct ia64_templ_desc |
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278 | { |
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279 | int group_boundary; /* 0=no boundary, 1=between slot 0 & 1, etc. */ |
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280 | enum ia64_unit exec_unit[3]; |
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281 | const char *name; |
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282 | }; |
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283 | |||
284 | /* The opcode table is an array of struct ia64_opcode. */ |
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285 | |||
286 | struct ia64_opcode |
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287 | { |
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288 | /* The opcode name. */ |
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289 | const char *name; |
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290 | |||
291 | /* The type of the instruction: */ |
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292 | enum ia64_insn_type type; |
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293 | |||
294 | /* Number of output operands: */ |
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295 | int num_outputs; |
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296 | |||
297 | /* The opcode itself. Those bits which will be filled in with |
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298 | operands are zeroes. */ |
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299 | ia64_insn opcode; |
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300 | |||
301 | /* The opcode mask. This is used by the disassembler. This is a |
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302 | mask containing ones indicating those bits which must match the |
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303 | opcode field, and zeroes indicating those bits which need not |
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304 | match (and are presumably filled in by operands). */ |
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305 | ia64_insn mask; |
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306 | |||
307 | /* An array of operand codes. Each code is an index into the |
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308 | operand table. They appear in the order which the operands must |
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309 | appear in assembly code, and are terminated by a zero. */ |
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310 | enum ia64_opnd operands[5]; |
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311 | |||
312 | /* One bit flags for the opcode. These are primarily used to |
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313 | indicate specific processors and environments support the |
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314 | instructions. The defined values are listed below. */ |
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315 | unsigned int flags; |
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316 | |||
317 | /* Used by ia64_find_next_opcode (). */ |
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318 | short ent_index; |
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319 | |||
320 | /* Opcode dependencies. */ |
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321 | const struct ia64_opcode_dependency *dependencies; |
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322 | }; |
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323 | |||
324 | /* Values defined for the flags field of a struct ia64_opcode. */ |
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325 | |||
326 | #define IA64_OPCODE_FIRST (1<<0) /* must be first in an insn group */ |
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327 | #define IA64_OPCODE_X_IN_MLX (1<<1) /* insn is allowed in X slot of MLX */ |
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328 | #define IA64_OPCODE_LAST (1<<2) /* must be last in an insn group */ |
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329 | #define IA64_OPCODE_PRIV (1<<3) /* privileged instruct */ |
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330 | #define IA64_OPCODE_SLOT2 (1<<4) /* insn allowed in slot 2 only */ |
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331 | #define IA64_OPCODE_NO_PRED (1<<5) /* insn cannot be predicated */ |
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332 | #define IA64_OPCODE_PSEUDO (1<<6) /* insn is a pseudo-op */ |
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333 | #define IA64_OPCODE_F2_EQ_F3 (1<<7) /* constraint: F2 == F3 */ |
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334 | #define IA64_OPCODE_LEN_EQ_64MCNT (1<<8) /* constraint: LEN == 64-CNT */ |
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335 | #define IA64_OPCODE_MOD_RRBS (1<<9) /* modifies all rrbs in CFM */ |
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336 | #define IA64_OPCODE_POSTINC (1<<10) /* postincrement MR3 operand */ |
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337 | |||
338 | /* A macro to extract the major opcode from an instruction. */ |
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339 | #define IA64_OP(i) (((i) >> 37) & 0xf) |
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340 | |||
341 | enum ia64_operand_class |
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342 | { |
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343 | IA64_OPND_CLASS_CST, /* constant */ |
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344 | IA64_OPND_CLASS_REG, /* register */ |
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345 | IA64_OPND_CLASS_IND, /* indirect register */ |
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346 | IA64_OPND_CLASS_ABS, /* absolute value */ |
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347 | IA64_OPND_CLASS_REL, /* IP-relative value */ |
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348 | }; |
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349 | |||
350 | /* The operands table is an array of struct ia64_operand. */ |
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351 | |||
352 | struct ia64_operand |
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353 | { |
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354 | enum ia64_operand_class op_class; |
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355 | |||
356 | /* Set VALUE as the operand bits for the operand of type SELF in the |
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357 | instruction pointed to by CODE. If an error occurs, *CODE is not |
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358 | modified and the returned string describes the cause of the |
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359 | error. If no error occurs, NULL is returned. */ |
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360 | const char *(*insert) (const struct ia64_operand *self, ia64_insn value, |
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361 | ia64_insn *code); |
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362 | |||
363 | /* Extract the operand bits for an operand of type SELF from |
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364 | instruction CODE store them in *VALUE. If an error occurs, the |
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365 | cause of the error is described by the string returned. If no |
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366 | error occurs, NULL is returned. */ |
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367 | const char *(*extract) (const struct ia64_operand *self, ia64_insn code, |
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368 | ia64_insn *value); |
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369 | |||
370 | /* A string whose meaning depends on the operand class. */ |
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371 | |||
372 | const char *str; |
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373 | |||
374 | struct bit_field |
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375 | { |
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376 | /* The number of bits in the operand. */ |
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377 | int bits; |
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378 | |||
379 | /* How far the operand is left shifted in the instruction. */ |
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380 | int shift; |
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381 | } |
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382 | field[4]; /* no operand has more than this many bit-fields */ |
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383 | |||
384 | unsigned int flags; |
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385 | |||
386 | const char *desc; /* brief description */ |
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387 | }; |
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388 | |||
389 | /* Values defined for the flags field of a struct ia64_operand. */ |
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390 | |||
391 | /* Disassemble as signed decimal (instead of hex): */ |
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392 | #define IA64_OPND_FLAG_DECIMAL_SIGNED (1<<0) |
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393 | /* Disassemble as unsigned decimal (instead of hex): */ |
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394 | #define IA64_OPND_FLAG_DECIMAL_UNSIGNED (1<<1) |
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395 | |||
396 | extern const struct ia64_templ_desc ia64_templ_desc[16]; |
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397 | |||
398 | /* The tables are sorted by major opcode number and are otherwise in |
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399 | the order in which the disassembler should consider instructions. */ |
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400 | extern struct ia64_opcode ia64_opcodes_a[]; |
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401 | extern struct ia64_opcode ia64_opcodes_i[]; |
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402 | extern struct ia64_opcode ia64_opcodes_m[]; |
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403 | extern struct ia64_opcode ia64_opcodes_b[]; |
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404 | extern struct ia64_opcode ia64_opcodes_f[]; |
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405 | extern struct ia64_opcode ia64_opcodes_d[]; |
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406 | |||
407 | |||
408 | extern struct ia64_opcode *ia64_find_opcode (const char *); |
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409 | extern struct ia64_opcode *ia64_find_next_opcode (struct ia64_opcode *); |
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410 | |||
411 | extern struct ia64_opcode *ia64_dis_opcode (ia64_insn, |
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412 | enum ia64_insn_type); |
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413 | |||
414 | extern void ia64_free_opcode (struct ia64_opcode *); |
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415 | extern const struct ia64_dependency *ia64_find_dependency (int); |
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416 | |||
417 | /* To avoid circular library dependencies, this array is implemented |
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418 | in bfd/cpu-ia64-opc.c: */ |
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419 | extern const struct ia64_operand elf64_ia64_operands[IA64_OPND_COUNT]; |
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420 | |||
421 | #endif /* opcode_ia64_h */1) |