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5191 | serge | 1 | /* d30v.h -- Header file for D30V opcode table |
6324 | serge | 2 | Copyright (C) 1997-2015 Free Software Foundation, Inc. |
5191 | serge | 3 | Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions |
4 | |||
5 | This file is part of GDB, GAS, and the GNU binutils. |
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6 | |||
7 | GDB, GAS, and the GNU binutils are free software; you can redistribute |
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8 | them and/or modify them under the terms of the GNU General Public |
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9 | License as published by the Free Software Foundation; either version 3, |
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10 | or (at your option) any later version. |
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11 | |||
12 | GDB, GAS, and the GNU binutils are distributed in the hope that they |
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13 | will be useful, but WITHOUT ANY WARRANTY; without even the implied |
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14 | warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See |
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15 | the GNU General Public License for more details. |
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16 | |||
17 | You should have received a copy of the GNU General Public License |
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18 | along with this file; see the file COPYING3. If not, write to the Free |
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19 | Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
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20 | MA 02110-1301, USA. */ |
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21 | |||
22 | #ifndef D30V_H |
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23 | #define D30V_H |
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24 | |||
25 | #define NOP 0x00F00000 |
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26 | |||
27 | /* Structure to hold information about predefined registers. */ |
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28 | struct pd_reg |
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29 | { |
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30 | char *name; /* name to recognize */ |
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31 | char *pname; /* name to print for this register */ |
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32 | int value; |
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33 | }; |
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34 | |||
35 | extern const struct pd_reg pre_defined_registers[]; |
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36 | int reg_name_cnt (void); |
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37 | |||
38 | /* the number of control registers */ |
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39 | #define MAX_CONTROL_REG 64 |
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40 | |||
41 | /* define the format specifiers */ |
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42 | #define FM00 0 |
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43 | #define FM01 0x80000000 |
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44 | #define FM10 0x8000000000000000LL |
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45 | #define FM11 0x8000000080000000LL |
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46 | |||
47 | /* define the opcode classes */ |
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48 | #define BRA 0 |
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49 | #define LOGIC 1 |
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50 | #define IMEM 2 |
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51 | #define IALU1 4 |
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52 | #define IALU2 5 |
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53 | |||
54 | /* define the execution condition codes */ |
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55 | #define ECC_AL 0 /* ALways (default) */ |
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56 | #define ECC_TX 1 /* F0=True, F1=Don't care */ |
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57 | #define ECC_FX 2 /* F0=False, F1=Don't care */ |
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58 | #define ECC_XT 3 /* F0=Don't care, F1=True */ |
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59 | #define ECC_XF 4 /* F0=Don't care, F1=False */ |
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60 | #define ECC_TT 5 /* F0=True, F1=True */ |
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61 | #define ECC_TF 6 /* F0=True, F1=False */ |
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62 | #define ECC_RESERVED 7 /* reserved */ |
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63 | #define ECC_MAX ECC_RESERVED |
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64 | |||
65 | extern const char *d30v_ecc_names[]; |
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66 | |||
67 | /* condition code table for CMP and CMPU */ |
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68 | extern const char *d30v_cc_names[]; |
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69 | |||
70 | /* The opcode table is an array of struct d30v_opcode. */ |
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71 | struct d30v_opcode |
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72 | { |
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73 | /* The opcode name. */ |
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74 | const char *name; |
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75 | |||
76 | /* the opcode */ |
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77 | int op1; /* first part, "IALU1" for example */ |
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78 | int op2; /* the rest of the opcode */ |
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79 | |||
80 | /* opcode format(s). These numbers correspond to entries */ |
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81 | /* in the d30v_format_table */ |
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82 | unsigned char format[4]; |
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83 | |||
84 | #define SHORT_M 1 |
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85 | #define SHORT_M2 5 /* for ld2w and st2w */ |
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86 | #define SHORT_A 9 |
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87 | #define SHORT_B1 11 |
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88 | #define SHORT_B2 12 |
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89 | #define SHORT_B2r 13 |
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90 | #define SHORT_B3 14 |
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91 | #define SHORT_B3r 16 |
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92 | #define SHORT_B3b 18 |
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93 | #define SHORT_B3br 20 |
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94 | #define SHORT_D1r 22 |
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95 | #define SHORT_D2 24 |
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96 | #define SHORT_D2r 26 |
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97 | #define SHORT_D2Br 28 |
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98 | #define SHORT_U 30 /* unary SHORT_A. ABS for example */ |
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99 | #define SHORT_F 31 /* SHORT_A with flag registers */ |
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100 | #define SHORT_AF 33 /* SHORT_A with only the first register a flag register */ |
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101 | #define SHORT_T 35 /* for trap instruction */ |
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102 | #define SHORT_A5 36 /* SHORT_A with a 5-bit immediate instead of 6 */ |
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103 | #define SHORT_CMP 38 /* special form for CMPcc */ |
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104 | #define SHORT_CMPU 40 /* special form for CMPUcc */ |
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105 | #define SHORT_A1 42 /* special form of SHORT_A for MACa opcodes where a=1 */ |
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106 | #define SHORT_AA 44 /* SHORT_A with the first register an accumulator */ |
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107 | #define SHORT_RA 46 /* SHORT_A with the second register an accumulator */ |
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108 | #define SHORT_MODINC 48 |
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109 | #define SHORT_MODDEC 49 |
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110 | #define SHORT_C1 50 |
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111 | #define SHORT_C2 51 |
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112 | #define SHORT_UF 52 |
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113 | #define SHORT_A2 53 |
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114 | #define SHORT_NONE 55 /* no operands */ |
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115 | #define SHORT_AR 56 /* like SHORT_AA but only accept register as third parameter */ |
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116 | #define LONG 57 |
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117 | #define LONG_U 58 /* unary LONG */ |
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118 | #define LONG_Ur 59 /* LONG pc-relative */ |
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119 | #define LONG_CMP 60 /* special form for CMPcc and CMPUcc */ |
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120 | #define LONG_M 61 /* Memory long for ldb, stb */ |
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121 | #define LONG_M2 62 /* Memory long for ld2w, st2w */ |
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122 | #define LONG_2 63 /* LONG with 2 operands; jmptnz */ |
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123 | #define LONG_2r 64 /* LONG with 2 operands; bratnz */ |
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124 | #define LONG_2b 65 /* LONG_2 with modifier of 3 */ |
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125 | #define LONG_2br 66 /* LONG_2r with modifier of 3 */ |
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126 | #define LONG_D 67 /* for DJMPI */ |
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127 | #define LONG_Dr 68 /* for DBRAI */ |
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128 | #define LONG_Dbr 69 /* for repeati */ |
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129 | |||
130 | /* the execution unit(s) used */ |
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131 | int unit; |
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132 | #define EITHER 0 |
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133 | #define IU 1 |
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134 | #define MU 2 |
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135 | #define EITHER_BUT_PREFER_MU 3 |
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136 | |||
137 | /* this field is used to decide if two instructions */ |
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138 | /* can be executed in parallel */ |
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139 | long flags_used; |
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140 | long flags_set; |
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141 | #define FLAG_0 (1L<<0) |
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142 | #define FLAG_1 (1L<<1) |
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143 | #define FLAG_2 (1L<<2) |
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144 | #define FLAG_3 (1L<<3) |
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145 | #define FLAG_4 (1L<<4) /* S (saturation) */ |
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146 | #define FLAG_5 (1L<<5) /* V (overflow) */ |
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147 | #define FLAG_6 (1L<<6) /* VA (accumulated overflow) */ |
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148 | #define FLAG_7 (1L<<7) /* C (carry/borrow) */ |
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149 | #define FLAG_SM (1L<<8) /* SM (stack mode) */ |
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150 | #define FLAG_RP (1L<<9) /* RP (repeat enable) */ |
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151 | #define FLAG_CONTROL (1L<<10) /* control registers */ |
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152 | #define FLAG_A0 (1L<<11) /* A0 */ |
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153 | #define FLAG_A1 (1L<<12) /* A1 */ |
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154 | #define FLAG_JMP (1L<<13) /* instruction is a branch */ |
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155 | #define FLAG_JSR (1L<<14) /* subroutine call. must be aligned */ |
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156 | #define FLAG_MEM (1L<<15) /* reads/writes memory */ |
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157 | #define FLAG_NOT_WITH_ADDSUBppp (1L<<16) /* Old meaning: a 2 word 4 byter operation |
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158 | New meaning: operation cannot be |
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159 | combined in parallel with ADD/SUBppp. */ |
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160 | #define FLAG_MUL16 (1L<<17) /* 16 bit multiply */ |
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161 | #define FLAG_MUL32 (1L<<18) /* 32 bit multiply */ |
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162 | #define FLAG_ADDSUBppp (1L<<19) /* ADDppp or SUBppp */ |
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163 | #define FLAG_DELAY (1L<<20) /* This is a delayed branch or jump */ |
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164 | #define FLAG_LKR (1L<<21) /* insn in left slot kills right slot */ |
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165 | #define FLAG_CVVA (FLAG_5|FLAG_6|FLAG_7) |
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166 | #define FLAG_C FLAG_7 |
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167 | #define FLAG_ALL (FLAG_0 | \ |
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168 | FLAG_1 | \ |
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169 | FLAG_2 | \ |
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170 | FLAG_3 | \ |
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171 | FLAG_4 | \ |
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172 | FLAG_5 | \ |
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173 | FLAG_6 | \ |
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174 | FLAG_7 | \ |
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175 | FLAG_SM | \ |
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176 | FLAG_RP | \ |
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177 | FLAG_CONTROL) |
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178 | |||
179 | int reloc_flag; |
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180 | #define RELOC_PCREL 1 |
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181 | #define RELOC_ABS 2 |
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182 | }; |
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183 | |||
184 | extern const struct d30v_opcode d30v_opcode_table[]; |
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185 | extern const int d30v_num_opcodes; |
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186 | |||
187 | /* The operands table is an array of struct d30v_operand. */ |
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188 | struct d30v_operand |
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189 | { |
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190 | /* the length of the field */ |
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191 | int length; |
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192 | |||
193 | /* The number of significant bits in the operand. */ |
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194 | int bits; |
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195 | |||
196 | /* position relative to Ra */ |
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197 | int position; |
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198 | |||
199 | /* syntax flags. */ |
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200 | long flags; |
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201 | }; |
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202 | extern const struct d30v_operand d30v_operand_table[]; |
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203 | |||
204 | /* Values defined for the flags field of a struct d30v_operand. */ |
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205 | |||
206 | /* this is the destination register; it will be modified */ |
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207 | /* this is used by the optimizer */ |
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208 | #define OPERAND_DEST (1) |
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209 | |||
210 | /* number or symbol */ |
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211 | #define OPERAND_NUM (2) |
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212 | |||
213 | /* address or label */ |
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214 | #define OPERAND_ADDR (4) |
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215 | |||
216 | /* register */ |
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217 | #define OPERAND_REG (8) |
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218 | |||
219 | /* postincrement + */ |
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220 | #define OPERAND_PLUS (0x10) |
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221 | |||
222 | /* postdecrement - */ |
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223 | #define OPERAND_MINUS (0x20) |
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224 | |||
225 | /* signed number */ |
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226 | #define OPERAND_SIGNED (0x40) |
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227 | |||
228 | /* this operand must be shifted left by 3 */ |
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229 | #define OPERAND_SHIFT (0x80) |
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230 | |||
231 | /* flag register */ |
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232 | #define OPERAND_FLAG (0x100) |
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233 | |||
234 | /* control register */ |
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235 | #define OPERAND_CONTROL (0x200) |
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236 | |||
237 | /* accumulator */ |
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238 | #define OPERAND_ACC (0x400) |
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239 | |||
240 | /* @ */ |
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241 | #define OPERAND_ATSIGN (0x800) |
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242 | |||
243 | /* @( */ |
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244 | #define OPERAND_ATPAR (0x1000) |
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245 | |||
246 | /* predecrement mode '@-sp' */ |
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247 | #define OPERAND_ATMINUS (0x2000) |
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248 | |||
249 | /* this operand changes the instruction name */ |
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250 | /* for example, CPMcc, CMPUcc */ |
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251 | #define OPERAND_NAME (0x4000) |
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252 | |||
253 | /* fake operand for mvtsys and mvfsys */ |
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254 | #define OPERAND_SPECIAL (0x8000) |
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255 | |||
256 | /* let the optimizer know that two registers are affected */ |
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257 | #define OPERAND_2REG (0x10000) |
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258 | |||
259 | /* This operand is pc-relative. Note that repeati can have two immediate |
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260 | operands, one of which is pcrel, the other (the IMM6U one) is not. */ |
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261 | #define OPERAND_PCREL (0x20000) |
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262 | |||
263 | /* The format table is an array of struct d30v_format. */ |
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264 | struct d30v_format |
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265 | { |
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266 | int form; /* SHORT_A, LONG, etc */ |
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267 | int modifier; /* two bit modifier following opcode */ |
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268 | unsigned char operands[5]; |
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269 | }; |
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270 | extern const struct d30v_format d30v_format_table[]; |
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271 | |||
272 | |||
273 | /* an instruction is defined by an opcode and a format */ |
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274 | /* for example, "add" has one opcode, but three different */ |
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275 | /* formats, 2 SHORT_A forms and a LONG form. */ |
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276 | struct d30v_insn |
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277 | { |
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278 | struct d30v_opcode *op; /* pointer to an entry in the opcode table */ |
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279 | struct d30v_format *form; /* pointer to an entry in the format table */ |
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280 | int ecc; /* execution condition code */ |
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281 | }; |
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282 | |||
283 | /* an expressionS only has one register type, so we fake it */ |
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284 | /* by setting high bits to indicate type */ |
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285 | #define REGISTER_MASK 0xFF |
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286 | |||
287 | #endif /* D30V_H */21)><21)>20)><20)>19)><19)>18)><18)>17)><17)>16)><16)>15)><15)>14)><14)>13)><13)>12)><12)>11)><11)>10)><10)>9)><9)>8)><8)>7)><7)>6)><6)>5)><5)>4)><4)>3) |