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5191 | serge | 1 | /* crx.h -- Header file for CRX opcode and register tables. |
6324 | serge | 2 | Copyright (C) 2004-2015 Free Software Foundation, Inc. |
5191 | serge | 3 | Contributed by Tomer Levi, NSC, Israel. |
4 | Originally written for GAS 2.12 by Tomer Levi, NSC, Israel. |
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5 | Updates, BFDizing, GNUifying and ELF support by Tomer Levi. |
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6 | |||
7 | This file is part of GAS, GDB and the GNU binutils. |
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8 | |||
9 | GAS, GDB, and GNU binutils is free software; you can redistribute it |
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10 | and/or modify it under the terms of the GNU General Public License as |
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11 | published by the Free Software Foundation; either version 3, or (at your |
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12 | option) any later version. |
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13 | |||
14 | GAS, GDB, and GNU binutils are distributed in the hope that they will be |
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15 | useful, but WITHOUT ANY WARRANTY; without even the implied warranty of |
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16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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17 | GNU General Public License for more details. |
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18 | |||
19 | You should have received a copy of the GNU General Public License |
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20 | along with this program; if not, write to the Free Software |
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21 | Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston, |
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22 | MA 02110-1301, USA. */ |
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23 | |||
24 | #ifndef _CRX_H_ |
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25 | #define _CRX_H_ |
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26 | |||
27 | /* CRX core/debug Registers : |
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28 | The enums are used as indices to CRX registers table (crx_regtab). |
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29 | Therefore, order MUST be preserved. */ |
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30 | |||
31 | typedef enum |
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32 | { |
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33 | /* 32-bit general purpose registers. */ |
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34 | r0, r1, r2, r3, r4, r5, r6, r7, r8, r9, |
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35 | r10, r11, r12, r13, r14, r15, ra, sp, |
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36 | /* 32-bit user registers. */ |
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37 | u0, u1, u2, u3, u4, u5, u6, u7, u8, u9, |
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38 | u10, u11, u12, u13, u14, u15, ura, usp, |
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39 | /* hi and lo registers. */ |
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40 | hi, lo, |
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41 | /* hi and lo user registers. */ |
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42 | uhi, ulo, |
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43 | /* Processor Status Register. */ |
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44 | psr, |
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45 | /* Interrupt Base Register. */ |
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46 | intbase, |
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47 | /* Interrupt Stack Pointer Register. */ |
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48 | isp, |
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49 | /* Configuration Register. */ |
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50 | cfg, |
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51 | /* Coprocessor Configuration Register. */ |
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52 | cpcfg, |
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53 | /* Coprocessor Enable Register. */ |
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54 | cen, |
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55 | /* Not a register. */ |
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56 | nullregister, |
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57 | MAX_REG |
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58 | } |
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59 | reg; |
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60 | |||
61 | /* CRX Coprocessor registers and special registers : |
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62 | The enums are used as indices to CRX coprocessor registers table |
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63 | (crx_copregtab). Therefore, order MUST be preserved. */ |
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64 | |||
65 | typedef enum |
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66 | { |
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67 | /* Coprocessor registers. */ |
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68 | c0 = MAX_REG, c1, c2, c3, c4, c5, c6, c7, c8, |
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69 | c9, c10, c11, c12, c13, c14, c15, |
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70 | /* Coprocessor special registers. */ |
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71 | cs0, cs1 ,cs2, cs3, cs4, cs5, cs6, cs7, cs8, |
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72 | cs9, cs10, cs11, cs12, cs13, cs14, cs15, |
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73 | /* Not a Coprocessor register. */ |
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74 | nullcopregister, |
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75 | MAX_COPREG |
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76 | } |
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77 | copreg; |
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78 | |||
79 | /* CRX Register types. */ |
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80 | |||
81 | typedef enum |
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82 | { |
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83 | CRX_R_REGTYPE, /* r |
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84 | CRX_U_REGTYPE, /* u |
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85 | CRX_C_REGTYPE, /* c |
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86 | CRX_CS_REGTYPE, /* cs |
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87 | CRX_CFG_REGTYPE /* configuration register */ |
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88 | } |
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89 | reg_type; |
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90 | |||
91 | /* CRX argument types : |
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92 | The argument types correspond to instructions operands |
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93 | |||
94 | Argument types : |
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95 | r - register |
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96 | c - constant |
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97 | i - immediate |
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98 | idxr - index register |
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99 | rbase - register base |
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100 | s - star ('*') |
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101 | copr - coprocessor register |
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102 | copsr - coprocessor special register. */ |
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103 | |||
104 | typedef enum |
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105 | { |
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106 | arg_r, arg_c, arg_cr, arg_ic, arg_icr, arg_sc, |
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107 | arg_idxr, arg_rbase, arg_copr, arg_copsr, |
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108 | /* Not an argument. */ |
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109 | nullargs |
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110 | } |
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111 | argtype; |
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112 | |||
113 | /* CRX operand types : |
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114 | The operand types correspond to instructions operands. */ |
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115 | |||
116 | typedef enum |
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117 | { |
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118 | dummy, |
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119 | /* 4-bit encoded constant. */ |
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120 | cst4, |
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121 | /* N-bit immediate. */ |
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122 | i16, i32, |
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123 | /* N-bit unsigned immediate. */ |
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124 | ui3, ui4, ui5, ui16, |
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125 | /* N-bit signed displacement. */ |
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126 | disps9, disps17, disps25, disps32, |
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127 | /* N-bit unsigned displacement. */ |
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128 | dispu5, |
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129 | /* N-bit escaped displacement. */ |
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130 | dispe9, |
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131 | /* N-bit absolute address. */ |
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132 | abs16, abs32, |
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133 | /* Register relative. */ |
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134 | rbase, rbase_dispu4, |
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135 | rbase_disps12, rbase_disps16, rbase_disps28, rbase_disps32, |
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136 | /* Register index. */ |
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137 | rindex_disps6, rindex_disps22, |
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138 | /* 4-bit genaral-purpose register specifier. */ |
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139 | regr, |
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140 | /* 8-bit register address space. */ |
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141 | regr8, |
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142 | /* coprocessor register. */ |
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143 | copregr, |
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144 | /* coprocessor special register. */ |
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145 | copsregr, |
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146 | /* Not an operand. */ |
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147 | nulloperand, |
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148 | /* Maximum supported operand. */ |
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149 | MAX_OPRD |
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150 | } |
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151 | operand_type; |
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152 | |||
153 | /* CRX instruction types. */ |
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154 | |||
155 | #define NO_TYPE_INS 0 |
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156 | #define ARITH_INS 1 |
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157 | #define LD_STOR_INS 2 |
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158 | #define BRANCH_INS 3 |
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159 | #define ARITH_BYTE_INS 4 |
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160 | #define CMPBR_INS 5 |
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161 | #define SHIFT_INS 6 |
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162 | #define BRANCH_NEQ_INS 7 |
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163 | #define LD_STOR_INS_INC 8 |
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164 | #define STOR_IMM_INS 9 |
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165 | #define CSTBIT_INS 10 |
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166 | #define COP_BRANCH_INS 11 |
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167 | #define COP_REG_INS 12 |
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168 | #define COPS_REG_INS 13 |
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169 | #define DCR_BRANCH_INS 14 |
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170 | |||
171 | /* Maximum value supported for instruction types. */ |
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172 | #define CRX_INS_MAX (1 << 4) |
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173 | /* Mask to record an instruction type. */ |
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174 | #define CRX_INS_MASK (CRX_INS_MAX - 1) |
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175 | /* Return instruction type, given instruction's attributes. */ |
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176 | #define CRX_INS_TYPE(attr) ((attr) & CRX_INS_MASK) |
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177 | |||
178 | /* Indicates whether this instruction has a register list as parameter. */ |
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179 | #define REG_LIST CRX_INS_MAX |
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180 | /* The operands in binary and assembly are placed in reverse order. |
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181 | load - (REVERSE_MATCH)/store - (! REVERSE_MATCH). */ |
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182 | #define REVERSE_MATCH (1 << 5) |
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183 | |||
184 | /* Kind of displacement map used DISPU[BWD]4. */ |
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185 | #define DISPUB4 (1 << 6) |
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186 | #define DISPUW4 (1 << 7) |
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187 | #define DISPUD4 (1 << 8) |
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188 | #define DISPU4MAP (DISPUB4 | DISPUW4 | DISPUD4) |
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189 | |||
190 | /* Printing formats, where the instruction prefix isn't consecutive. */ |
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191 | #define FMT_1 (1 << 9) /* 0xF0F00000 */ |
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192 | #define FMT_2 (1 << 10) /* 0xFFF0FF00 */ |
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193 | #define FMT_3 (1 << 11) /* 0xFFF00F00 */ |
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194 | #define FMT_4 (1 << 12) /* 0xFFF0F000 */ |
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195 | #define FMT_5 (1 << 13) /* 0xFFF0FFF0 */ |
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196 | #define FMT_CRX (FMT_1 | FMT_2 | FMT_3 | FMT_4 | FMT_5) |
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197 | |||
198 | /* Indicates whether this instruction can be relaxed. */ |
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199 | #define RELAXABLE (1 << 14) |
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200 | |||
201 | /* Indicates that instruction uses user registers (and not |
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202 | general-purpose registers) as operands. */ |
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203 | #define USER_REG (1 << 15) |
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204 | |||
205 | /* Indicates that instruction can perfom a cst4 mapping. */ |
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206 | #define CST4MAP (1 << 16) |
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207 | |||
208 | /* Instruction shouldn't allow 'sp' usage. */ |
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209 | #define NO_SP (1 << 17) |
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210 | |||
211 | /* Instruction shouldn't allow to push a register which is used as a rptr. */ |
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212 | #define NO_RPTR (1 << 18) |
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213 | |||
214 | /* Maximum operands per instruction. */ |
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215 | #define MAX_OPERANDS 5 |
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216 | /* Maximum register name length. */ |
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217 | #define MAX_REGNAME_LEN 10 |
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218 | /* Maximum instruction length. */ |
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219 | #define MAX_INST_LEN 256 |
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220 | |||
221 | |||
222 | /* Values defined for the flags field of a struct operand_entry. */ |
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223 | |||
224 | /* Operand must be an unsigned number. */ |
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225 | #define OP_UNSIGNED (1 << 0) |
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226 | /* Operand must be a signed number. */ |
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227 | #define OP_SIGNED (1 << 1) |
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228 | /* A special arithmetic 4-bit constant operand. */ |
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229 | #define OP_CST4 (1 << 2) |
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230 | /* A special load/stor 4-bit unsigned displacement operand. */ |
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231 | #define OP_DISPU4 (1 << 3) |
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232 | /* Operand must be an even number. */ |
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233 | #define OP_EVEN (1 << 4) |
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234 | /* Operand is shifted right. */ |
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235 | #define OP_SHIFT (1 << 5) |
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236 | /* Operand is shifted right and decremented. */ |
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237 | #define OP_SHIFT_DEC (1 << 6) |
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238 | /* Operand has reserved escape sequences. */ |
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239 | #define OP_ESC (1 << 7) |
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240 | /* Operand is used only for the upper 64 KB (FFFF0000 to FFFFFFFF). */ |
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241 | #define OP_UPPER_64KB (1 << 8) |
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242 | |||
243 | /* Single operand description. */ |
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244 | |||
245 | typedef struct |
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246 | { |
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247 | /* Operand type. */ |
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248 | operand_type op_type; |
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249 | /* Operand location within the opcode. */ |
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250 | unsigned int shift; |
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251 | } |
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252 | operand_desc; |
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253 | |||
254 | /* Instruction data structure used in instruction table. */ |
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255 | |||
256 | typedef struct |
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257 | { |
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258 | /* Name. */ |
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259 | const char *mnemonic; |
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260 | /* Size (in words). */ |
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261 | unsigned int size; |
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262 | /* Constant prefix (matched by the disassembler). */ |
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263 | unsigned long match; |
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264 | /* Match size (in bits). */ |
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265 | int match_bits; |
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266 | /* Attributes. */ |
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267 | unsigned int flags; |
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268 | /* Operands (always last, so unreferenced operands are initialized). */ |
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269 | operand_desc operands[MAX_OPERANDS]; |
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270 | } |
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271 | inst; |
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272 | |||
273 | /* Data structure for a single instruction's arguments (Operands). */ |
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274 | |||
275 | typedef struct |
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276 | { |
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277 | /* Register or base register. */ |
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278 | reg r; |
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279 | /* Index register. */ |
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280 | reg i_r; |
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281 | /* Coprocessor register. */ |
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282 | copreg cr; |
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283 | /* Constant/immediate/absolute value. */ |
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284 | long constant; |
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285 | /* Scaled index mode. */ |
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286 | unsigned int scale; |
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287 | /* Argument type. */ |
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288 | argtype type; |
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289 | /* Size of the argument (in bits) required to represent. */ |
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290 | int size; |
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291 | /* The type of the expression. */ |
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292 | unsigned char X_op; |
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293 | } |
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294 | argument; |
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295 | |||
296 | /* Internal structure to hold the various entities |
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297 | corresponding to the current assembling instruction. */ |
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298 | |||
299 | typedef struct |
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300 | { |
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301 | /* Number of arguments. */ |
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302 | int nargs; |
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303 | /* The argument data structure for storing args (operands). */ |
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304 | argument arg[MAX_OPERANDS]; |
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305 | /* The following fields are required only by CRX-assembler. */ |
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306 | #ifdef TC_CRX |
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307 | /* Expression used for setting the fixups (if any). */ |
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308 | expressionS exp; |
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309 | bfd_reloc_code_real_type rtype; |
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310 | #endif /* TC_CRX */ |
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311 | /* Instruction size (in bytes). */ |
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312 | int size; |
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313 | } |
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314 | ins; |
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315 | |||
316 | /* Structure to hold information about predefined operands. */ |
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317 | |||
318 | typedef struct |
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319 | { |
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320 | /* Size (in bits). */ |
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321 | unsigned int bit_size; |
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322 | /* Argument type. */ |
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323 | argtype arg_type; |
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324 | /* One bit syntax flags. */ |
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325 | int flags; |
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326 | } |
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327 | operand_entry; |
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328 | |||
329 | /* Structure to hold trap handler information. */ |
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330 | |||
331 | typedef struct |
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332 | { |
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333 | /* Trap name. */ |
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334 | char *name; |
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335 | /* Index in dispatch table. */ |
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336 | unsigned int entry; |
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337 | } |
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338 | trap_entry; |
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339 | |||
340 | /* Structure to hold information about predefined registers. */ |
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341 | |||
342 | typedef struct |
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343 | { |
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344 | /* Name (string representation). */ |
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345 | char *name; |
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346 | /* Value (enum representation). */ |
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347 | union |
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348 | { |
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349 | /* Register. */ |
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350 | reg reg_val; |
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351 | /* Coprocessor register. */ |
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352 | copreg copreg_val; |
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353 | } value; |
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354 | /* Register image. */ |
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355 | int image; |
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356 | /* Register type. */ |
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357 | reg_type type; |
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358 | } |
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359 | reg_entry; |
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360 | |||
361 | /* Structure to hold a cst4 operand mapping. */ |
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362 | |||
363 | /* CRX opcode table. */ |
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364 | extern const inst crx_instruction[]; |
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365 | extern const int crx_num_opcodes; |
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366 | #define NUMOPCODES crx_num_opcodes |
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367 | |||
368 | /* CRX operands table. */ |
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369 | extern const operand_entry crx_optab[]; |
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370 | |||
371 | /* CRX registers table. */ |
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372 | extern const reg_entry crx_regtab[]; |
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373 | extern const int crx_num_regs; |
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374 | #define NUMREGS crx_num_regs |
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375 | |||
376 | /* CRX coprocessor registers table. */ |
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377 | extern const reg_entry crx_copregtab[]; |
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378 | extern const int crx_num_copregs; |
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379 | #define NUMCOPREGS crx_num_copregs |
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380 | |||
381 | /* CRX trap/interrupt table. */ |
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382 | extern const trap_entry crx_traps[]; |
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383 | extern const int crx_num_traps; |
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384 | #define NUMTRAPS crx_num_traps |
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385 | |||
386 | /* cst4 operand mapping. */ |
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387 | extern const int cst4_map[]; |
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388 | extern const int cst4_maps; |
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389 | |||
390 | /* Table of instructions with no operands. */ |
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391 | extern const char* no_op_insn[]; |
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392 | |||
393 | /* Current instruction we're assembling. */ |
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394 | extern const inst *instruction; |
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395 | |||
396 | /* A macro for representing the instruction "constant" opcode, that is, |
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397 | the FIXED part of the instruction. The "constant" opcode is represented |
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398 | as a 32-bit unsigned long, where OPC is expanded (by a left SHIFT) |
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399 | over that range. */ |
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400 | #define BIN(OPC,SHIFT) (OPC << SHIFT) |
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401 | |||
402 | /* Is the current instruction type is TYPE ? */ |
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403 | #define IS_INSN_TYPE(TYPE) \ |
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404 | (CRX_INS_TYPE(instruction->flags) == TYPE) |
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405 | |||
406 | /* Is the current instruction mnemonic is MNEMONIC ? */ |
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407 | #define IS_INSN_MNEMONIC(MNEMONIC) \ |
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408 | (strcmp(instruction->mnemonic,MNEMONIC) == 0) |
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409 | |||
410 | /* Does the current instruction has register list ? */ |
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411 | #define INST_HAS_REG_LIST \ |
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412 | (instruction->flags & REG_LIST) |
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413 | |||
414 | /* Long long type handling. */ |
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415 | /* Replace all appearances of 'long long int' with LONGLONG. */ |
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416 | typedef long long int LONGLONG; |
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417 | typedef unsigned long long ULONGLONG; |
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418 | |||
419 | #endif /* _CRX_H_ */><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><> |