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5191 | serge | 1 | /* Opcode table for the ARC. |
6324 | serge | 2 | Copyright 1994-2015 Free Software Foundation, Inc. |
5191 | serge | 3 | |
6324 | serge | 4 | Contributed by Claudiu Zissulescu (claziss@synopsys.com) |
5 | |||
5191 | serge | 6 | This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and |
7 | the GNU Binutils. |
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8 | |||
9 | GAS/GDB is free software; you can redistribute it and/or modify |
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10 | it under the terms of the GNU General Public License as published by |
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11 | the Free Software Foundation; either version 3, or (at your option) |
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12 | any later version. |
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13 | |||
14 | GAS/GDB is distributed in the hope that it will be useful, |
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15 | but WITHOUT ANY WARRANTY; without even the implied warranty of |
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6324 | serge | 16 | MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
5191 | serge | 17 | GNU General Public License for more details. |
18 | |||
19 | You should have received a copy of the GNU General Public License |
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20 | along with GAS or GDB; see the file COPYING3. If not, write to |
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21 | the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston, |
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22 | MA 02110-1301, USA. */ |
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23 | |||
6324 | serge | 24 | #ifndef OPCODE_ARC_H |
25 | #define OPCODE_ARC_H |
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5191 | serge | 26 | |
6324 | serge | 27 | #define MAX_INSN_ARGS 6 |
28 | #define MAX_INSN_FLGS 3 |
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5191 | serge | 29 | |
6324 | serge | 30 | /* Instruction Class. */ |
31 | typedef enum |
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32 | { |
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33 | ARITH, |
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34 | AUXREG, |
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35 | BRANCH, |
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36 | CONTROL, |
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37 | DSP, |
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38 | FLOAT, |
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39 | INVALID, |
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40 | JUMP, |
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41 | KERNEL, |
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42 | LOGICAL, |
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43 | MEMORY, |
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44 | } insn_class_t; |
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5191 | serge | 45 | |
6324 | serge | 46 | /* Instruction Subclass. */ |
47 | typedef enum |
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48 | { |
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49 | NONE, |
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50 | CVT, |
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51 | BTSCN, |
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52 | CD1, |
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53 | CD2, |
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54 | DIV, |
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55 | DP, |
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56 | MPY1E, |
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57 | MPY6E, |
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58 | MPY7E, |
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59 | MPY8E, |
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60 | MPY9E, |
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61 | SHFT1, |
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62 | SHFT2, |
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63 | SWAP, |
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64 | SP |
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65 | } insn_subclass_t; |
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5191 | serge | 66 | |
6324 | serge | 67 | /* Flags class. */ |
68 | typedef enum |
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69 | { |
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70 | FNONE, |
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71 | CND, /* Conditional flags. */ |
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72 | WBM, /* Write-back modes. */ |
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73 | FLG, /* F Flag. */ |
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74 | SBP, /* Static branch prediction. */ |
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75 | DLY, /* Delay slot. */ |
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76 | DIF, /* Bypass caches. */ |
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77 | SGX, /* Sign extend modes. */ |
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78 | SZM /* Data size modes. */ |
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79 | } flag_class_t; |
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5191 | serge | 80 | |
6324 | serge | 81 | /* The opcode table is an array of struct arc_opcode. */ |
82 | struct arc_opcode |
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83 | { |
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84 | /* The opcode name. */ |
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85 | const char *name; |
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5191 | serge | 86 | |
6324 | serge | 87 | /* The opcode itself. Those bits which will be filled in with |
88 | operands are zeroes. */ |
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89 | unsigned opcode; |
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5191 | serge | 90 | |
6324 | serge | 91 | /* The opcode mask. This is used by the disassembler. This is a |
92 | mask containing ones indicating those bits which must match the |
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93 | opcode field, and zeroes indicating those bits which need not |
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94 | match (and are presumably filled in by operands). */ |
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95 | unsigned mask; |
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5191 | serge | 96 | |
6324 | serge | 97 | /* One bit flags for the opcode. These are primarily used to |
98 | indicate specific processors and environments support the |
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99 | instructions. The defined values are listed below. */ |
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100 | unsigned cpu; |
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5191 | serge | 101 | |
6324 | serge | 102 | /* The instruction class. This is used by gdb. */ |
103 | insn_class_t class; |
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5191 | serge | 104 | |
6324 | serge | 105 | /* The instruction subclass. */ |
106 | insn_subclass_t subclass; |
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5191 | serge | 107 | |
6324 | serge | 108 | /* An array of operand codes. Each code is an index into the |
109 | operand table. They appear in the order which the operands must |
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110 | appear in assembly code, and are terminated by a zero. */ |
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111 | unsigned char operands[MAX_INSN_ARGS + 1]; |
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5191 | serge | 112 | |
6324 | serge | 113 | /* An array of flag codes. Each code is an index into the flag |
114 | table. They appear in the order which the flags must appear in |
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115 | assembly code, and are terminated by a zero. */ |
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116 | unsigned char flags[MAX_INSN_FLGS + 1]; |
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117 | }; |
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5191 | serge | 118 | |
6324 | serge | 119 | /* The table itself is sorted by major opcode number, and is otherwise |
120 | in the order in which the disassembler should consider |
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121 | instructions. */ |
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122 | extern const struct arc_opcode arc_opcodes[]; |
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123 | extern const unsigned arc_num_opcodes; |
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5191 | serge | 124 | |
6324 | serge | 125 | /* CPU Availability. */ |
126 | #define ARC_OPCODE_ARC600 0x0001 /* ARC 600 specific insns. */ |
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127 | #define ARC_OPCODE_ARC700 0x0002 /* ARC 700 specific insns. */ |
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128 | #define ARC_OPCODE_ARCv2EM 0x0004 /* ARCv2 EM specific insns. */ |
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129 | #define ARC_OPCODE_ARCv2HS 0x0008 /* ARCv2 HS specific insns. */ |
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5191 | serge | 130 | |
6324 | serge | 131 | /* CPU extensions. */ |
132 | #define ARC_EA 0x0001 |
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133 | #define ARC_CD 0x0001 /* Mutual exclusive with EA. */ |
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134 | #define ARC_LLOCK 0x0002 |
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135 | #define ARC_ATOMIC 0x0002 /* Mutual exclusive with LLOCK. */ |
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136 | #define ARC_MPY 0x0004 |
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137 | #define ARC_MULT 0x0004 |
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5191 | serge | 138 | |
6324 | serge | 139 | /* Floating point support. */ |
140 | #define ARC_DPFP 0x0010 |
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141 | #define ARC_SPFP 0x0020 |
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142 | #define ARC_FPU 0x0030 |
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5191 | serge | 143 | |
6324 | serge | 144 | /* NORM & SWAP. */ |
145 | #define ARC_SWAP 0x0100 |
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146 | #define ARC_NORM 0x0200 |
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147 | #define ARC_BSCAN 0x0200 |
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5191 | serge | 148 | |
6324 | serge | 149 | /* A7 specific. */ |
150 | #define ARC_UIX 0x1000 |
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151 | #define ARC_TSTAMP 0x1000 |
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5191 | serge | 152 | |
6324 | serge | 153 | /* A6 specific. */ |
154 | #define ARC_VBFDW 0x1000 |
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155 | #define ARC_BARREL 0x1000 |
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156 | #define ARC_DSPA 0x1000 |
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5191 | serge | 157 | |
6324 | serge | 158 | /* EM specific. */ |
159 | #define ARC_SHIFT 0x1000 |
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5191 | serge | 160 | |
6324 | serge | 161 | /* V2 specific. */ |
162 | #define ARC_INTR 0x1000 |
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163 | #define ARC_DIV 0x1000 |
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5191 | serge | 164 | |
6324 | serge | 165 | /* V1 specific. */ |
166 | #define ARC_XMAC 0x1000 |
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167 | #define ARC_CRC 0x1000 |
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5191 | serge | 168 | |
6324 | serge | 169 | /* Base architecture -- all cpus. */ |
170 | #define ARC_OPCODE_BASE \ |
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171 | (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700 \ |
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172 | | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS) |
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5191 | serge | 173 | |
6324 | serge | 174 | /* A macro to check for short instructions. */ |
175 | #define ARC_SHORT(mask) \ |
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176 | (((mask) & 0xFFFF0000) ? 0 : 1) |
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5191 | serge | 177 | |
6324 | serge | 178 | /* The operands table is an array of struct arc_operand. */ |
179 | struct arc_operand |
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180 | { |
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181 | /* The number of bits in the operand. */ |
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182 | unsigned int bits; |
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5191 | serge | 183 | |
6324 | serge | 184 | /* How far the operand is left shifted in the instruction. */ |
185 | unsigned int shift; |
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5191 | serge | 186 | |
6324 | serge | 187 | /* The default relocation type for this operand. */ |
188 | signed int default_reloc; |
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5191 | serge | 189 | |
6324 | serge | 190 | /* One bit syntax flags. */ |
191 | unsigned int flags; |
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5191 | serge | 192 | |
6324 | serge | 193 | /* Insertion function. This is used by the assembler. To insert an |
194 | operand value into an instruction, check this field. |
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5191 | serge | 195 | |
6324 | serge | 196 | If it is NULL, execute |
197 | i |= (op & ((1 << o->bits) - 1)) << o->shift; |
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198 | (i is the instruction which we are filling in, o is a pointer to |
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199 | this structure, and op is the opcode value; this assumes twos |
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200 | complement arithmetic). |
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5191 | serge | 201 | |
6324 | serge | 202 | If this field is not NULL, then simply call it with the |
203 | instruction and the operand value. It will return the new value |
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204 | of the instruction. If the ERRMSG argument is not NULL, then if |
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205 | the operand value is illegal, *ERRMSG will be set to a warning |
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206 | string (the operand will be inserted in any case). If the |
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207 | operand value is legal, *ERRMSG will be unchanged (most operands |
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208 | can accept any value). */ |
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209 | unsigned (*insert) (unsigned instruction, int op, const char **errmsg); |
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5191 | serge | 210 | |
6324 | serge | 211 | /* Extraction function. This is used by the disassembler. To |
212 | extract this operand type from an instruction, check this field. |
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5191 | serge | 213 | |
6324 | serge | 214 | If it is NULL, compute |
215 | op = ((i) >> o->shift) & ((1 << o->bits) - 1); |
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216 | if ((o->flags & ARC_OPERAND_SIGNED) != 0 |
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217 | && (op & (1 << (o->bits - 1))) != 0) |
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218 | op -= 1 << o->bits; |
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219 | (i is the instruction, o is a pointer to this structure, and op |
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220 | is the result; this assumes twos complement arithmetic). |
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5191 | serge | 221 | |
6324 | serge | 222 | If this field is not NULL, then simply call it with the |
223 | instruction value. It will return the value of the operand. If |
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224 | the INVALID argument is not NULL, *INVALID will be set to |
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225 | TRUE if this operand type can not actually be extracted from |
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226 | this operand (i.e., the instruction does not match). If the |
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227 | operand is valid, *INVALID will not be changed. */ |
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228 | int (*extract) (unsigned instruction, bfd_boolean *invalid); |
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229 | }; |
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230 | |||
231 | /* Elements in the table are retrieved by indexing with values from |
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232 | the operands field of the arc_opcodes table. */ |
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233 | extern const struct arc_operand arc_operands[]; |
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234 | extern const unsigned arc_num_operands; |
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235 | extern const unsigned arc_Toperand; |
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236 | extern const unsigned arc_NToperand; |
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237 | |||
238 | /* Values defined for the flags field of a struct arc_operand. */ |
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239 | |||
240 | /* This operand does not actually exist in the assembler input. This |
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241 | is used to support extended mnemonics, for which two operands fields |
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242 | are identical. The assembler should call the insert function with |
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243 | any op value. The disassembler should call the extract function, |
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244 | ignore the return value, and check the value placed in the invalid |
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245 | argument. */ |
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246 | #define ARC_OPERAND_FAKE 0x0001 |
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247 | |||
248 | /* This operand names an integer register. */ |
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249 | #define ARC_OPERAND_IR 0x0002 |
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250 | |||
5191 | serge | 251 | /* This operand takes signed values. */ |
6324 | serge | 252 | #define ARC_OPERAND_SIGNED 0x0004 |
5191 | serge | 253 | |
6324 | serge | 254 | /* This operand takes unsigned values. This exists primarily so that |
255 | a flags value of 0 can be treated as end-of-arguments. */ |
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256 | #define ARC_OPERAND_UNSIGNED 0x0008 |
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5191 | serge | 257 | |
6324 | serge | 258 | /* This operand takes long immediate values. */ |
259 | #define ARC_OPERAND_LIMM 0x0010 |
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5191 | serge | 260 | |
6324 | serge | 261 | /* This operand is identical like the previous one. */ |
262 | #define ARC_OPERAND_DUPLICATE 0x0020 |
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5191 | serge | 263 | |
6324 | serge | 264 | /* This operand is PC relative. Used for internal relocs. */ |
265 | #define ARC_OPERAND_PCREL 0x0040 |
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5191 | serge | 266 | |
6324 | serge | 267 | /* This operand is truncated. The truncation is done accordingly to |
268 | operand alignment attribute. */ |
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269 | #define ARC_OPERAND_TRUNCATE 0x0080 |
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5191 | serge | 270 | |
6324 | serge | 271 | /* This operand is 16bit aligned. */ |
272 | #define ARC_OPERAND_ALIGNED16 0x0100 |
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5191 | serge | 273 | |
6324 | serge | 274 | /* This operand is 32bit aligned. */ |
275 | #define ARC_OPERAND_ALIGNED32 0x0200 |
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5191 | serge | 276 | |
6324 | serge | 277 | /* This operand can be ignored by matching process if it is not |
278 | present. */ |
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279 | #define ARC_OPERAND_IGNORE 0x0400 |
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5191 | serge | 280 | |
6324 | serge | 281 | /* Don't check the range when matching. */ |
282 | #define ARC_OPERAND_NCHK 0x0800 |
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5191 | serge | 283 | |
6324 | serge | 284 | /* Mark the braket possition. */ |
285 | #define ARC_OPERAND_BRAKET 0x1000 |
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5191 | serge | 286 | |
6324 | serge | 287 | /* Mask for selecting the type for typecheck purposes. */ |
288 | #define ARC_OPERAND_TYPECHECK_MASK \ |
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289 | (ARC_OPERAND_IR | \ |
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290 | ARC_OPERAND_LIMM | ARC_OPERAND_SIGNED | \ |
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291 | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET) |
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5191 | serge | 292 | |
6324 | serge | 293 | /* The flags structure. */ |
294 | struct arc_flag_operand |
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295 | { |
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296 | /* The flag name. */ |
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297 | const char *name; |
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5191 | serge | 298 | |
6324 | serge | 299 | /* The flag code. */ |
300 | unsigned code; |
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5191 | serge | 301 | |
6324 | serge | 302 | /* The number of bits in the operand. */ |
303 | unsigned int bits; |
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5191 | serge | 304 | |
6324 | serge | 305 | /* How far the operand is left shifted in the instruction. */ |
306 | unsigned int shift; |
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5191 | serge | 307 | |
6324 | serge | 308 | /* Available for disassembler. */ |
309 | unsigned char favail; |
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310 | }; |
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5191 | serge | 311 | |
6324 | serge | 312 | /* The flag operands table. */ |
313 | extern const struct arc_flag_operand arc_flag_operands[]; |
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314 | extern const unsigned arc_num_flag_operands; |
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5191 | serge | 315 | |
6324 | serge | 316 | /* The flag's class structure. */ |
317 | struct arc_flag_class |
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318 | { |
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319 | /* Flag class. */ |
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320 | flag_class_t class; |
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5191 | serge | 321 | |
6324 | serge | 322 | /* List of valid flags (codes). */ |
323 | unsigned flags[256]; |
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324 | }; |
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5191 | serge | 325 | |
6324 | serge | 326 | extern const struct arc_flag_class arc_flag_classes[]; |
5191 | serge | 327 | |
6324 | serge | 328 | /* Structure for special cases. */ |
329 | struct arc_flag_special |
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330 | { |
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331 | /* Name of special case instruction. */ |
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332 | const char *name; |
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333 | |||
334 | /* List of flags applicable for special case instruction. */ |
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335 | unsigned flags[32]; |
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5191 | serge | 336 | }; |
337 | |||
6324 | serge | 338 | extern const struct arc_flag_special arc_flag_special_cases[]; |
339 | extern const unsigned arc_num_flag_special; |
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5191 | serge | 340 | |
6324 | serge | 341 | /* Relocation equivalence structure. */ |
342 | struct arc_reloc_equiv_tab |
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343 | { |
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344 | const char * name; /* String to lookup. */ |
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345 | const char * mnemonic; /* Extra matching condition. */ |
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346 | unsigned flagcode; /* Extra matching condition. */ |
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347 | signed int oldreloc; /* Old relocation. */ |
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348 | signed int newreloc; /* New relocation. */ |
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349 | }; |
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5191 | serge | 350 | |
6324 | serge | 351 | extern const struct arc_reloc_equiv_tab arc_reloc_equiv[]; |
352 | extern const unsigned arc_num_equiv_tab; |
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5191 | serge | 353 | |
6324 | serge | 354 | /* Structure for operand operations for pseudo/alias instructions. */ |
355 | struct arc_operand_operation |
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356 | { |
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357 | /* The index for operand from operand array. */ |
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358 | unsigned operand_idx; |
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5191 | serge | 359 | |
6324 | serge | 360 | /* Defines if it needs the operand inserted by the assembler or |
361 | whether this operand comes from the pseudo instruction's |
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362 | operands. */ |
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363 | unsigned char needs_insert; |
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5191 | serge | 364 | |
6324 | serge | 365 | /* Count we have to add to the operand. Use negative number to |
366 | subtract from the operand. Also use this number to add to 0 if |
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367 | the operand needs to be inserted (i.e. needs_insert == 1). */ |
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368 | int count; |
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5191 | serge | 369 | |
6324 | serge | 370 | /* Index of the operand to swap with. To be done AFTER applying |
371 | inc_count. */ |
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372 | unsigned swap_operand_idx; |
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373 | }; |
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5191 | serge | 374 | |
6324 | serge | 375 | /* Structure for pseudo/alias instructions. */ |
376 | struct arc_pseudo_insn |
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377 | { |
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378 | /* Mnemonic for pseudo/alias insn. */ |
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379 | const char *mnemonic_p; |
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5191 | serge | 380 | |
6324 | serge | 381 | /* Mnemonic for real instruction. */ |
382 | const char *mnemonic_r; |
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5191 | serge | 383 | |
6324 | serge | 384 | /* Flag that will have to be added (if any). */ |
385 | const char *flag_r; |
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386 | |||
387 | /* Amount of operands. */ |
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388 | unsigned operand_cnt; |
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389 | |||
390 | /* Array of operand operations. */ |
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391 | struct arc_operand_operation operand[6]; |
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392 | }; |
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393 | |||
394 | extern const struct arc_pseudo_insn arc_pseudo_insns[]; |
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395 | extern const unsigned arc_num_pseudo_insn; |
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396 | |||
397 | /* Structure for AUXILIARY registers. */ |
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398 | struct arc_aux_reg |
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399 | { |
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400 | /* Register address. */ |
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401 | int address; |
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402 | |||
403 | /* Register name. */ |
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404 | const char *name; |
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405 | |||
406 | /* Size of the string. */ |
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407 | size_t length; |
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408 | }; |
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409 | |||
410 | extern const struct arc_aux_reg arc_aux_regs[]; |
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411 | extern const unsigned arc_num_aux_regs; |
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412 | |||
413 | #endif /* OPCODE_ARC_H */><>><>><>><>><> |