WebSVN – Kolibri OS – Blame – /contrib/toolchain/avra/includes/m64def.inc

Rev	Author	Line No.	Line
6400	punk_joker	1	;*** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************
		2	;*** Created: 2005-01-11 10:31 *** Source: ATmega64.xml **********
		3	;*************************************************************************
		4	;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
		5	;*
		6	;* Number : AVR000
		7	;* File Name : "m64def.inc"
		8	;* Title : Register/Bit Definitions for the ATmega64
		9	;* Date : 2005-01-11
		10	;* Version : 2.14
		11	;* Support E-mail : avr@atmel.com
		12	;* Target MCU : ATmega64
		13	;*
		14	;* DESCRIPTION
		15	;* When including this file in the assembly program file, all I/O register
		16	;* names and I/O register bit names appearing in the data book can be used.
		17	;* In addition, the six registers forming the three data pointers X, Y and
		18	;* Z have been assigned names XL - ZH. Highest RAM address for Internal
		19	;* SRAM is also defined
		20	;*
		21	;* The Register names are represented by their hexadecimal address.
		22	;*
		23	;* The Register Bit names are represented by their bit number (0-7).
		24	;*
		25	;* Please observe the difference in using the bit names with instructions
		26	;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
		27	;* (skip if bit in register set/cleared). The following example illustrates
		28	;* this:
		29	;*
		30	;* in r16,PORTB ;read PORTB latch
		31	;* sbr r16,(1<
		32	;* out PORTB,r16 ;output to PORTB
		33	;*
		34	;* in r16,TIFR ;read the Timer Interrupt Flag Register
		35	;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
		36	;* rjmp TOV0_is_set ;jump if set
		37	;* ... ;otherwise do something else
		38	;*************************************************************************
		39
		40	#ifndef _M64DEF_INC_
		41	#define _M64DEF_INC_
		42
		43
		44	#pragma partinc 0
		45
		46	; *** SPECIFY DEVICE *************************************************
		47	.device ATmega64
		48	#pragma AVRPART ADMIN PART_NAME ATmega64
		49	.equ SIGNATURE_000 = 0x1e
		50	.equ SIGNATURE_001 = 0x96
		51	.equ SIGNATURE_002 = 0x02
		52
		53	#pragma AVRPART CORE CORE_VERSION V2E
		54
		55
		56	; *** I/O REGISTER DEFINITIONS ***************************************
		57	; NOTE:
		58	; Definitions marked "MEMORY MAPPED"are extended I/O ports
		59	; and cannot be used with IN/OUT instructions
		60	.equ UCSR1C = 0x9d ; MEMORY MAPPED
		61	.equ UDR1 = 0x9c ; MEMORY MAPPED
		62	.equ UCSR1A = 0x9b ; MEMORY MAPPED
		63	.equ UCSR1B = 0x9a ; MEMORY MAPPED
		64	.equ UBRR1L = 0x99 ; MEMORY MAPPED
		65	.equ UBRR1H = 0x98 ; MEMORY MAPPED
		66	.equ UCSR0C = 0x95 ; MEMORY MAPPED
		67	.equ UBRR0H = 0x90 ; MEMORY MAPPED
		68	.equ ADCSRB = 0x8e ; MEMORY MAPPED
		69	.equ TCCR3C = 0x8c ; MEMORY MAPPED
		70	.equ TCCR3A = 0x8b ; MEMORY MAPPED
		71	.equ TCCR3B = 0x8a ; MEMORY MAPPED
		72	.equ TCNT3H = 0x89 ; MEMORY MAPPED
		73	.equ TCNT3L = 0x88 ; MEMORY MAPPED
		74	.equ OCR3AH = 0x87 ; MEMORY MAPPED
		75	.equ OCR3AL = 0x86 ; MEMORY MAPPED
		76	.equ OCR3BH = 0x85 ; MEMORY MAPPED
		77	.equ OCR3BL = 0x84 ; MEMORY MAPPED
		78	.equ OCR3CH = 0x83 ; MEMORY MAPPED
		79	.equ OCR3CL = 0x82 ; MEMORY MAPPED
		80	.equ ICR3H = 0x81 ; MEMORY MAPPED
		81	.equ ICR3L = 0x80 ; MEMORY MAPPED
		82	.equ ETIMSK = 0x7d ; MEMORY MAPPED
		83	.equ ETIFR = 0x7c ; MEMORY MAPPED
		84	.equ TCCR1C = 0x7a ; MEMORY MAPPED
		85	.equ OCR1CH = 0x79 ; MEMORY MAPPED
		86	.equ OCR1CL = 0x78 ; MEMORY MAPPED
		87	.equ TWCR = 0x74 ; MEMORY MAPPED
		88	.equ TWDR = 0x73 ; MEMORY MAPPED
		89	.equ TWAR = 0x72 ; MEMORY MAPPED
		90	.equ TWSR = 0x71 ; MEMORY MAPPED
		91	.equ TWBR = 0x70 ; MEMORY MAPPED
		92	.equ OSCCAL = 0x6f ; MEMORY MAPPED
		93	.equ XMCRA = 0x6d ; MEMORY MAPPED
		94	.equ XMCRB = 0x6c ; MEMORY MAPPED
		95	.equ EICRA = 0x6a ; MEMORY MAPPED
		96	.equ SPMCSR = 0x68 ; MEMORY MAPPED
		97	.equ PORTG = 0x65 ; MEMORY MAPPED
		98	.equ DDRG = 0x64 ; MEMORY MAPPED
		99	.equ PING = 0x63 ; MEMORY MAPPED
		100	.equ PORTF = 0x62 ; MEMORY MAPPED
		101	.equ DDRF = 0x61 ; MEMORY MAPPED
		102	.equ SREG = 0x3f
		103	.equ SPH = 0x3e
		104	.equ SPL = 0x3d
		105	.equ XDIV = 0x3c
		106	.equ EICRB = 0x3a
		107	.equ EIMSK = 0x39
		108	.equ EIFR = 0x38
		109	.equ TIMSK = 0x37
		110	.equ TIFR = 0x36
		111	.equ MCUCR = 0x35
		112	.equ MCUCSR = 0x34
		113	.equ TCCR0 = 0x33
		114	.equ TCNT0 = 0x32
		115	.equ OCR0 = 0x31
		116	.equ ASSR = 0x30
		117	.equ TCCR1A = 0x2f
		118	.equ TCCR1B = 0x2e
		119	.equ TCNT1H = 0x2d
		120	.equ TCNT1L = 0x2c
		121	.equ OCR1AH = 0x2b
		122	.equ OCR1AL = 0x2a
		123	.equ OCR1BH = 0x29
		124	.equ OCR1BL = 0x28
		125	.equ ICR1H = 0x27
		126	.equ ICR1L = 0x26
		127	.equ TCCR2 = 0x25
		128	.equ TCNT2 = 0x24
		129	.equ OCR2 = 0x23
		130	.equ OCDR = 0x22
		131	.equ WDTCR = 0x21
		132	.equ SFIOR = 0x20
		133	.equ EEARH = 0x1f
		134	.equ EEARL = 0x1e
		135	.equ EEDR = 0x1d
		136	.equ EECR = 0x1c
		137	.equ PORTA = 0x1b
		138	.equ DDRA = 0x1a
		139	.equ PINA = 0x19
		140	.equ PORTB = 0x18
		141	.equ DDRB = 0x17
		142	.equ PINB = 0x16
		143	.equ PORTC = 0x15
		144	.equ DDRC = 0x14
		145	.equ PINC = 0x13
		146	.equ PORTD = 0x12
		147	.equ DDRD = 0x11
		148	.equ PIND = 0x10
		149	.equ SPDR = 0x0f
		150	.equ SPSR = 0x0e
		151	.equ SPCR = 0x0d
		152	.equ UDR0 = 0x0c
		153	.equ UCSR0A = 0x0b
		154	.equ UCSR0B = 0x0a
		155	.equ UBRR0L = 0x09
		156	.equ ACSR = 0x08
		157	.equ ADMUX = 0x07
		158	.equ ADCSRA = 0x06
		159	.equ ADCH = 0x05
		160	.equ ADCL = 0x04
		161	.equ PORTE = 0x03
		162	.equ DDRE = 0x02
		163	.equ PINE = 0x01
		164	.equ PINF = 0x00
		165
		166
		167	; *** BIT DEFINITIONS ************************************************
		168
		169	; *** ANALOG_COMPARATOR **********
		170	; SFIOR - Special Function IO Register
		171	.equ ACME = 3 ; Analog Comparator Multiplexer Enable
		172
		173	; ACSR - Analog Comparator Control And Status Register
		174	.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
		175	.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
		176	.equ ACIC = 2 ; Analog Comparator Input Capture Enable
		177	.equ ACIE = 3 ; Analog Comparator Interrupt Enable
		178	.equ ACI = 4 ; Analog Comparator Interrupt Flag
		179	.equ ACO = 5 ; Analog Compare Output
		180	.equ ACBG = 6 ; Analog Comparator Bandgap Select
		181	.equ ACD = 7 ; Analog Comparator Disable
		182
		183
		184	; *** AD_CONVERTER ***************
		185	; ADMUX - The ADC multiplexer Selection Register
		186	.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
		187	.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
		188	.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
		189	.equ MUX3 = 3 ; Analog Channel and Gain Selection Bits
		190	.equ MUX4 = 4 ; Analog Channel and Gain Selection Bits
		191	.equ ADLAR = 5 ; Left Adjust Result
		192	.equ REFS0 = 6 ; Reference Selection Bit 0
		193	.equ REFS1 = 7 ; Reference Selection Bit 1
		194
		195	; ADCSRA - The ADC Control and Status register A
		196	.equ ADCSR = ADCSRA ; For compatibility
		197	.equ ADPS0 = 0 ; ADC Prescaler Select Bits
		198	.equ ADPS1 = 1 ; ADC Prescaler Select Bits
		199	.equ ADPS2 = 2 ; ADC Prescaler Select Bits
		200	.equ ADIE = 3 ; ADC Interrupt Enable
		201	.equ ADIF = 4 ; ADC Interrupt Flag
		202	.equ ADATE = 5 ; ADC Auto Trigger Enable
		203	.equ ADFR = ADATE ; For compatibility
		204	.equ ADSC = 6 ; ADC Start Conversion
		205	.equ ADEN = 7 ; ADC Enable
		206
		207	; ADCH - ADC Data Register High Byte
		208	.equ ADCH0 = 0 ; ADC Data Register High Byte Bit 0
		209	.equ ADCH1 = 1 ; ADC Data Register High Byte Bit 1
		210	.equ ADCH2 = 2 ; ADC Data Register High Byte Bit 2
		211	.equ ADCH3 = 3 ; ADC Data Register High Byte Bit 3
		212	.equ ADCH4 = 4 ; ADC Data Register High Byte Bit 4
		213	.equ ADCH5 = 5 ; ADC Data Register High Byte Bit 5
		214	.equ ADCH6 = 6 ; ADC Data Register High Byte Bit 6
		215	.equ ADCH7 = 7 ; ADC Data Register High Byte Bit 7
		216
		217	; ADCL - ADC Data Register Low Byte
		218	.equ ADCL0 = 0 ; ADC Data Register Low Byte Bit 0
		219	.equ ADCL1 = 1 ; ADC Data Register Low Byte Bit 1
		220	.equ ADCL2 = 2 ; ADC Data Register Low Byte Bit 2
		221	.equ ADCL3 = 3 ; ADC Data Register Low Byte Bit 3
		222	.equ ADCL4 = 4 ; ADC Data Register Low Byte Bit 4
		223	.equ ADCL5 = 5 ; ADC Data Register Low Byte Bit 5
		224	.equ ADCL6 = 6 ; ADC Data Register Low Byte Bit 6
		225	.equ ADCL7 = 7 ; ADC Data Register Low Byte Bit 7
		226
		227	; ADCSRB - The ADC Control and Status register B
		228	.equ ADTS0 = 0 ; ADC Auto Trigger Source bit 0
		229	.equ ADTS1 = 1 ; ADC Auto Trigger Source bit 1
		230	.equ ADTS2 = 2 ; ADC Auto Trigger Source bit 2
		231
		232
		233	; *** SPI ************************
		234	; SPDR - SPI Data Register
		235	.equ SPDR0 = 0 ; SPI Data Register bit 0
		236	.equ SPDR1 = 1 ; SPI Data Register bit 1
		237	.equ SPDR2 = 2 ; SPI Data Register bit 2
		238	.equ SPDR3 = 3 ; SPI Data Register bit 3
		239	.equ SPDR4 = 4 ; SPI Data Register bit 4
		240	.equ SPDR5 = 5 ; SPI Data Register bit 5
		241	.equ SPDR6 = 6 ; SPI Data Register bit 6
		242	.equ SPDR7 = 7 ; SPI Data Register bit 7
		243
		244	; SPSR - SPI Status Register
		245	.equ SPI2X = 0 ; Double SPI Speed Bit
		246	.equ WCOL = 6 ; Write Collision Flag
		247	.equ SPIF = 7 ; SPI Interrupt Flag
		248
		249	; SPCR - SPI Control Register
		250	.equ SPR0 = 0 ; SPI Clock Rate Select 0
		251	.equ SPR1 = 1 ; SPI Clock Rate Select 1
		252	.equ CPHA = 2 ; Clock Phase
		253	.equ CPOL = 3 ; Clock polarity
		254	.equ MSTR = 4 ; Master/Slave Select
		255	.equ DORD = 5 ; Data Order
		256	.equ SPE = 6 ; SPI Enable
		257	.equ SPIE = 7 ; SPI Interrupt Enable
		258
		259
		260	; *** TWI ************************
		261	; TWBR - TWI Bit Rate register
		262	.equ I2BR = TWBR ; For compatibility
		263	.equ TWBR0 = 0 ;
		264	.equ TWBR1 = 1 ;
		265	.equ TWBR2 = 2 ;
		266	.equ TWBR3 = 3 ;
		267	.equ TWBR4 = 4 ;
		268	.equ TWBR5 = 5 ;
		269	.equ TWBR6 = 6 ;
		270	.equ TWBR7 = 7 ;
		271
		272	; TWCR - TWI Control Register
		273	.equ I2CR = TWCR ; For compatibility
		274	.equ TWIE = 0 ; TWI Interrupt Enable
		275	.equ I2IE = TWIE ; For compatibility
		276	.equ TWEN = 2 ; TWI Enable Bit
		277	.equ I2EN = TWEN ; For compatibility
		278	.equ ENI2C = TWEN ; For compatibility
		279	.equ TWWC = 3 ; TWI Write Collition Flag
		280	.equ I2WC = TWWC ; For compatibility
		281	.equ TWSTO = 4 ; TWI Stop Condition Bit
		282	.equ I2STO = TWSTO ; For compatibility
		283	.equ TWSTA = 5 ; TWI Start Condition Bit
		284	.equ I2STA = TWSTA ; For compatibility
		285	.equ TWEA = 6 ; TWI Enable Acknowledge Bit
		286	.equ I2EA = TWEA ; For compatibility
		287	.equ TWINT = 7 ; TWI Interrupt Flag
		288	.equ I2INT = TWINT ; For compatibility
		289
		290	; TWSR - TWI Status Register
		291	.equ I2SR = TWSR ; For compatibility
		292	.equ TWPS0 = 0 ; TWI Prescaler
		293	.equ TWS0 = TWPS0 ; For compatibility
		294	.equ I2GCE = TWPS0 ; For compatibility
		295	.equ TWPS1 = 1 ; TWI Prescaler
		296	.equ TWS1 = TWPS1 ; For compatibility
		297	.equ TWS3 = 3 ; TWI Status
		298	.equ I2S3 = TWS3 ; For compatibility
		299	.equ TWS4 = 4 ; TWI Status
		300	.equ I2S4 = TWS4 ; For compatibility
		301	.equ TWS5 = 5 ; TWI Status
		302	.equ I2S5 = TWS5 ; For compatibility
		303	.equ TWS6 = 6 ; TWI Status
		304	.equ I2S6 = TWS6 ; For compatibility
		305	.equ TWS7 = 7 ; TWI Status
		306	.equ I2S7 = TWS7 ; For compatibility
		307
		308	; TWDR - TWI Data register
		309	.equ I2DR = TWDR ; For compatibility
		310	.equ TWD0 = 0 ; TWI Data Register Bit 0
		311	.equ TWD1 = 1 ; TWI Data Register Bit 1
		312	.equ TWD2 = 2 ; TWI Data Register Bit 2
		313	.equ TWD3 = 3 ; TWI Data Register Bit 3
		314	.equ TWD4 = 4 ; TWI Data Register Bit 4
		315	.equ TWD5 = 5 ; TWI Data Register Bit 5
		316	.equ TWD6 = 6 ; TWI Data Register Bit 6
		317	.equ TWD7 = 7 ; TWI Data Register Bit 7
		318
		319	; TWAR - TWI (Slave) Address register
		320	.equ I2AR = TWAR ; For compatibility
		321	.equ TWGCE = 0 ; TWI General Call Recognition Enable Bit
		322	.equ TWA0 = 1 ; TWI (Slave) Address register Bit 0
		323	.equ TWA1 = 2 ; TWI (Slave) Address register Bit 1
		324	.equ TWA2 = 3 ; TWI (Slave) Address register Bit 2
		325	.equ TWA3 = 4 ; TWI (Slave) Address register Bit 3
		326	.equ TWA4 = 5 ; TWI (Slave) Address register Bit 4
		327	.equ TWA5 = 6 ; TWI (Slave) Address register Bit 5
		328	.equ TWA6 = 7 ; TWI (Slave) Address register Bit 6
		329
		330
		331	; *** USART0 *********************
		332	; UDR0 - USART I/O Data Register
		333	.equ UDR00 = 0 ; USART I/O Data Register bit 0
		334	.equ UDR01 = 1 ; USART I/O Data Register bit 1
		335	.equ UDR02 = 2 ; USART I/O Data Register bit 2
		336	.equ UDR03 = 3 ; USART I/O Data Register bit 3
		337	.equ UDR04 = 4 ; USART I/O Data Register bit 4
		338	.equ UDR05 = 5 ; USART I/O Data Register bit 5
		339	.equ UDR06 = 6 ; USART I/O Data Register bit 6
		340	.equ UDR07 = 7 ; USART I/O Data Register bit 7
		341
		342	; UCSR0A - USART Control and Status Register A
		343	.equ MPCM0 = 0 ; Multi-processor Communication Mode
		344	.equ U2X0 = 1 ; Double the USART transmission speed
		345	.equ UPE0 = 2 ; Parity Error
		346	.equ DOR0 = 3 ; Data overRun
		347	.equ FE0 = 4 ; Framing Error
		348	.equ UDRE0 = 5 ; USART Data Register Empty
		349	.equ TXC0 = 6 ; USART Transmitt Complete
		350	.equ RXC0 = 7 ; USART Receive Complete
		351
		352	; UCSR0B - USART Control and Status Register B
		353	.equ TXB80 = 0 ; Transmit Data Bit 8
		354	.equ RXB80 = 1 ; Receive Data Bit 8
		355	.equ UCSZ02 = 2 ; Character Size
		356	.equ UCSZ2 = UCSZ02 ; For compatibility
		357	.equ TXEN0 = 3 ; Transmitter Enable
		358	.equ RXEN0 = 4 ; Receiver Enable
		359	.equ UDRIE0 = 5 ; USART Data register Empty Interrupt Enable
		360	.equ TXCIE0 = 6 ; TX Complete Interrupt Enable
		361	.equ RXCIE0 = 7 ; RX Complete Interrupt Enable
		362
		363	; UCSR0C - USART Control and Status Register C
		364	.equ UCPOL0 = 0 ; Clock Polarity
		365	.equ UCSZ00 = 1 ; Character Size
		366	.equ UCSZ01 = 2 ; Character Size
		367	.equ USBS0 = 3 ; Stop Bit Select
		368	.equ UPM00 = 4 ; Parity Mode Bit 0
		369	.equ UPM01 = 5 ; Parity Mode Bit 1
		370	.equ UMSEL0 = 6 ; USART Mode Select
		371
		372
		373	; *** USART1 *********************
		374	; UDR1 - USART I/O Data Register
		375	.equ UDR10 = 0 ; USART I/O Data Register bit 0
		376	.equ UDR11 = 1 ; USART I/O Data Register bit 1
		377	.equ UDR12 = 2 ; USART I/O Data Register bit 2
		378	.equ UDR13 = 3 ; USART I/O Data Register bit 3
		379	.equ UDR14 = 4 ; USART I/O Data Register bit 4
		380	.equ UDR15 = 5 ; USART I/O Data Register bit 5
		381	.equ UDR16 = 6 ; USART I/O Data Register bit 6
		382	.equ UDR17 = 7 ; USART I/O Data Register bit 7
		383
		384	; UCSR1A - USART Control and Status Register A
		385	.equ MPCM1 = 0 ; Multi-processor Communication Mode
		386	.equ U2X1 = 1 ; Double the USART transmission speed
		387	.equ UPE1 = 2 ; Parity Error
		388	.equ DOR1 = 3 ; Data overRun
		389	.equ FE1 = 4 ; Framing Error
		390	.equ UDRE1 = 5 ; USART Data Register Empty
		391	.equ TXC1 = 6 ; USART Transmitt Complete
		392	.equ RXC1 = 7 ; USART Receive Complete
		393
		394	; UCSR1B - USART Control and Status Register B
		395	.equ TXB81 = 0 ; Transmit Data Bit 8
		396	.equ RXB81 = 1 ; Receive Data Bit 8
		397	.equ UCSZ12 = 2 ; Character Size
		398	.equ TXEN1 = 3 ; Transmitter Enable
		399	.equ RXEN1 = 4 ; Receiver Enable
		400	.equ UDRIE1 = 5 ; USART Data register Empty Interrupt Enable
		401	.equ TXCIE1 = 6 ; TX Complete Interrupt Enable
		402	.equ RXCIE1 = 7 ; RX Complete Interrupt Enable
		403
		404	; UCSR1C - USART Control and Status Register C
		405	.equ UCPOL1 = 0 ; Clock Polarity
		406	.equ UCSZ10 = 1 ; Character Size
		407	.equ UCSZ11 = 2 ; Character Size
		408	.equ USBS1 = 3 ; Stop Bit Select
		409	.equ UPM10 = 4 ; Parity Mode Bit 0
		410	.equ UPM11 = 5 ; Parity Mode Bit 1
		411	.equ UMSEL1 = 6 ; USART Mode Select
		412
		413
		414	; *** CPU ************************
		415	; SREG - Status Register
		416	.equ SREG_C = 0 ; Carry Flag
		417	.equ SREG_Z = 1 ; Zero Flag
		418	.equ SREG_N = 2 ; Negative Flag
		419	.equ SREG_V = 3 ; Two's Complement Overflow Flag
		420	.equ SREG_S = 4 ; Sign Bit
		421	.equ SREG_H = 5 ; Half Carry Flag
		422	.equ SREG_T = 6 ; Bit Copy Storage
		423	.equ SREG_I = 7 ; Global Interrupt Enable
		424
		425	; MCUCR - MCU Control Register
		426	.equ IVCE = 0 ; Interrupt Vector Change Enable
		427	.equ IVSEL = 1 ; Interrupt Vector Select
		428	.equ SM2 = 2 ; Sleep Mode Select
		429	.equ SM0 = 3 ; Sleep Mode Select
		430	.equ SM1 = 4 ; Sleep Mode Select
		431	.equ SE = 5 ; Sleep Enable
		432	.equ SRW10 = 6 ; External SRAM Wait State Select
		433	.equ SRE = 7 ; External SRAM Enable
		434
		435	; XMCRA - External Memory Control Register A
		436	.equ SRW11 = 1 ; Wait state select bit upper page
		437	.equ SRW00 = 2 ; Wait state select bit lower page
		438	.equ SRW01 = 3 ; Wait state select bit lower page
		439	.equ SRL0 = 4 ; Wait state page limit
		440	.equ SRL1 = 5 ; Wait state page limit
		441	.equ SRL2 = 6 ; Wait state page limit
		442
		443	; XMCRB - External Memory Control Register B
		444	.equ XMM0 = 0 ; External Memory High Mask
		445	.equ XMM1 = 1 ; External Memory High Mask
		446	.equ XMM2 = 2 ; External Memory High Mask
		447	.equ XMBK = 7 ; External Memory Bus Keeper Enable
		448
		449	; OSCCAL - Oscillator Calibration Value
		450	.equ CAL0 = 0 ; Oscillator Calibration Value
		451	.equ CAL1 = 1 ; Oscillator Calibration Value
		452	.equ CAL2 = 2 ; Oscillator Calibration Value
		453	.equ CAL3 = 3 ; Oscillator Calibration Value
		454	.equ CAL4 = 4 ; Oscillator Calibration Value
		455	.equ CAL5 = 5 ; Oscillator Calibration Value
		456	.equ CAL6 = 6 ; Oscillator Calibration Value
		457	.equ CAL7 = 7 ; Oscillator Calibration Value
		458
		459	; XDIV - XTAL Divide Control Register
		460	.equ XDIV0 = 0 ; XTAl Divide Select Bit 0
		461	.equ XDIV1 = 1 ; XTAl Divide Select Bit 1
		462	.equ XDIV2 = 2 ; XTAl Divide Select Bit 2
		463	.equ XDIV3 = 3 ; XTAl Divide Select Bit 3
		464	.equ XDIV4 = 4 ; XTAl Divide Select Bit 4
		465	.equ XDIV5 = 5 ; XTAl Divide Select Bit 5
		466	.equ XDIV6 = 6 ; XTAl Divide Select Bit 6
		467	.equ XDIVEN = 7 ; XTAL Divide Enable
		468
		469	; MCUCSR - MCU Control And Status Register
		470	.equ PORF = 0 ; Power-on reset flag
		471	.equ EXTRF = 1 ; External Reset Flag
		472	.equ BORF = 2 ; Brown-out Reset Flag
		473	.equ WDRF = 3 ; Watchdog Reset Flag
		474	.equ JTRF = 4 ; JTAG Reset Flag
		475	.equ JTD = 7 ; JTAG Interface Disable
		476
		477
		478	; *** BOOT_LOAD ******************
		479	; SPMCSR - Store Program Memory Control Register
		480	.equ SPMCR = SPMCSR ; For compatibility
		481	.equ SPMEN = 0 ; Store Program Memory Enable
		482	.equ PGERS = 1 ; Page Erase
		483	.equ PGWRT = 2 ; Page Write
		484	.equ BLBSET = 3 ; Boot Lock Bit Set
		485	.equ RWWSRE = 4 ; Read While Write section read enable
		486	.equ ASRE = RWWSRE ; For compatibility
		487	.equ RWWSB = 6 ; Read While Write Section Busy
		488	.equ ASB = RWWSB ; For compatibility
		489	.equ SPMIE = 7 ; SPM Interrupt Enable
		490
		491
		492	; *** JTAG ***********************
		493	; OCDR - On-Chip Debug Related Register in I/O Memory
		494	.equ OCDR0 = 0 ; On-Chip Debug Register Bit 0
		495	.equ OCDR1 = 1 ; On-Chip Debug Register Bit 1
		496	.equ OCDR2 = 2 ; On-Chip Debug Register Bit 2
		497	.equ OCDR3 = 3 ; On-Chip Debug Register Bit 3
		498	.equ OCDR4 = 4 ; On-Chip Debug Register Bit 4
		499	.equ OCDR5 = 5 ; On-Chip Debug Register Bit 5
		500	.equ OCDR6 = 6 ; On-Chip Debug Register Bit 6
		501	.equ OCDR7 = 7 ; On-Chip Debug Register Bit 7
		502	.equ IDRD = OCDR7 ; For compatibility
		503
		504	; MCUCSR - MCU Control And Status Register
		505	;.equ JTRF = 4 ; JTAG Reset Flag
		506	;.equ JTD = 7 ; JTAG Interface Disable
		507
		508
		509	; *** MISC ***********************
		510	; SFIOR - Special Function IO Register
		511	.equ PSR321 = 0 ; Prescaler Reset Timer/Counter3, Timer/Counter2, and Timer/Counter1
		512	.equ PSR1 = PSR321 ; For compatibility
		513	.equ PSR2 = PSR321 ; For compatibility
		514	.equ PSR3 = PSR321 ; For compatibility
		515	.equ PSR0 = 1 ; Prescaler Reset Timer/Counter0
		516	.equ PUD = 2 ; Pull Up Disable
		517	;.equ ACME = 3 ; Analog Comparator Multiplexer Enable
		518	.equ TSM = 7 ; Timer/Counter Synchronization Mode
		519
		520
		521	; *** EXTERNAL_INTERRUPT *********
		522	; EICRA - External Interrupt Control Register A
		523	.equ ISC00 = 0 ; External Interrupt Sense Control Bit
		524	.equ ISC01 = 1 ; External Interrupt Sense Control Bit
		525	.equ ISC10 = 2 ; External Interrupt Sense Control Bit
		526	.equ ISC11 = 3 ; External Interrupt Sense Control Bit
		527	.equ ISC20 = 4 ; External Interrupt Sense Control Bit
		528	.equ ISC21 = 5 ; External Interrupt Sense Control Bit
		529	.equ ISC30 = 6 ; External Interrupt Sense Control Bit
		530	.equ ISC31 = 7 ; External Interrupt Sense Control Bit
		531
		532	; EICRB - External Interrupt Control Register B
		533	.equ ISC40 = 0 ; External Interrupt 7-4 Sense Control Bit
		534	.equ ISC41 = 1 ; External Interrupt 7-4 Sense Control Bit
		535	.equ ISC50 = 2 ; External Interrupt 7-4 Sense Control Bit
		536	.equ ISC51 = 3 ; External Interrupt 7-4 Sense Control Bit
		537	.equ ISC60 = 4 ; External Interrupt 7-4 Sense Control Bit
		538	.equ ISC61 = 5 ; External Interrupt 7-4 Sense Control Bit
		539	.equ ISC70 = 6 ; External Interrupt 7-4 Sense Control Bit
		540	.equ ISC71 = 7 ; External Interrupt 7-4 Sense Control Bit
		541
		542	; EIMSK - External Interrupt Mask Register
		543	.equ GICR = EIMSK ; For compatibility
		544	.equ GIMSK = EIMSK ; For compatibility
		545	.equ INT0 = 0 ; External Interrupt Request 0 Enable
		546	.equ INT1 = 1 ; External Interrupt Request 1 Enable
		547	.equ INT2 = 2 ; External Interrupt Request 2 Enable
		548	.equ INT3 = 3 ; External Interrupt Request 3 Enable
		549	.equ INT4 = 4 ; External Interrupt Request 4 Enable
		550	.equ INT5 = 5 ; External Interrupt Request 5 Enable
		551	.equ INT6 = 6 ; External Interrupt Request 6 Enable
		552	.equ INT7 = 7 ; External Interrupt Request 7 Enable
		553
		554	; EIFR - External Interrupt Flag Register
		555	.equ GIFR = EIFR ; For compatibility
		556	.equ INTF0 = 0 ; External Interrupt Flag 0
		557	.equ INTF1 = 1 ; External Interrupt Flag 1
		558	.equ INTF2 = 2 ; External Interrupt Flag 2
		559	.equ INTF3 = 3 ; External Interrupt Flag 3
		560	.equ INTF4 = 4 ; External Interrupt Flag 4
		561	.equ INTF5 = 5 ; External Interrupt Flag 5
		562	.equ INTF6 = 6 ; External Interrupt Flag 6
		563	.equ INTF7 = 7 ; External Interrupt Flag 7
		564
		565
		566	; *** EEPROM *********************
		567	; EEDR - EEPROM Data Register
		568	.equ EEDR0 = 0 ; EEPROM Data Register bit 0
		569	.equ EEDR1 = 1 ; EEPROM Data Register bit 1
		570	.equ EEDR2 = 2 ; EEPROM Data Register bit 2
		571	.equ EEDR3 = 3 ; EEPROM Data Register bit 3
		572	.equ EEDR4 = 4 ; EEPROM Data Register bit 4
		573	.equ EEDR5 = 5 ; EEPROM Data Register bit 5
		574	.equ EEDR6 = 6 ; EEPROM Data Register bit 6
		575	.equ EEDR7 = 7 ; EEPROM Data Register bit 7
		576
		577	; EECR - EEPROM Control Register
		578	.equ EERE = 0 ; EEPROM Read Enable
		579	.equ EEWE = 1 ; EEPROM Write Enable
		580	.equ EEMWE = 2 ; EEPROM Master Write Enable
		581	.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
		582
		583
		584	; *** PORTA **********************
		585	; PORTA - Port A Data Register
		586	.equ PORTA0 = 0 ; Port A Data Register bit 0
		587	.equ PA0 = 0 ; For compatibility
		588	.equ PORTA1 = 1 ; Port A Data Register bit 1
		589	.equ PA1 = 1 ; For compatibility
		590	.equ PORTA2 = 2 ; Port A Data Register bit 2
		591	.equ PA2 = 2 ; For compatibility
		592	.equ PORTA3 = 3 ; Port A Data Register bit 3
		593	.equ PA3 = 3 ; For compatibility
		594	.equ PORTA4 = 4 ; Port A Data Register bit 4
		595	.equ PA4 = 4 ; For compatibility
		596	.equ PORTA5 = 5 ; Port A Data Register bit 5
		597	.equ PA5 = 5 ; For compatibility
		598	.equ PORTA6 = 6 ; Port A Data Register bit 6
		599	.equ PA6 = 6 ; For compatibility
		600	.equ PORTA7 = 7 ; Port A Data Register bit 7
		601	.equ PA7 = 7 ; For compatibility
		602
		603	; DDRA - Port A Data Direction Register
		604	.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
		605	.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
		606	.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
		607	.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
		608	.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
		609	.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
		610	.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
		611	.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
		612
		613	; PINA - Port A Input Pins
		614	.equ PINA0 = 0 ; Input Pins, Port A bit 0
		615	.equ PINA1 = 1 ; Input Pins, Port A bit 1
		616	.equ PINA2 = 2 ; Input Pins, Port A bit 2
		617	.equ PINA3 = 3 ; Input Pins, Port A bit 3
		618	.equ PINA4 = 4 ; Input Pins, Port A bit 4
		619	.equ PINA5 = 5 ; Input Pins, Port A bit 5
		620	.equ PINA6 = 6 ; Input Pins, Port A bit 6
		621	.equ PINA7 = 7 ; Input Pins, Port A bit 7
		622
		623
		624	; *** PORTB **********************
		625	; PORTB - Port B Data Register
		626	.equ PORTB0 = 0 ; Port B Data Register bit 0
		627	.equ PB0 = 0 ; For compatibility
		628	.equ PORTB1 = 1 ; Port B Data Register bit 1
		629	.equ PB1 = 1 ; For compatibility
		630	.equ PORTB2 = 2 ; Port B Data Register bit 2
		631	.equ PB2 = 2 ; For compatibility
		632	.equ PORTB3 = 3 ; Port B Data Register bit 3
		633	.equ PB3 = 3 ; For compatibility
		634	.equ PORTB4 = 4 ; Port B Data Register bit 4
		635	.equ PB4 = 4 ; For compatibility
		636	.equ PORTB5 = 5 ; Port B Data Register bit 5
		637	.equ PB5 = 5 ; For compatibility
		638	.equ PORTB6 = 6 ; Port B Data Register bit 6
		639	.equ PB6 = 6 ; For compatibility
		640	.equ PORTB7 = 7 ; Port B Data Register bit 7
		641	.equ PB7 = 7 ; For compatibility
		642
		643	; DDRB - Port B Data Direction Register
		644	.equ DDB0 = 0 ; Port B Data Direction Register bit 0
		645	.equ DDB1 = 1 ; Port B Data Direction Register bit 1
		646	.equ DDB2 = 2 ; Port B Data Direction Register bit 2
		647	.equ DDB3 = 3 ; Port B Data Direction Register bit 3
		648	.equ DDB4 = 4 ; Port B Data Direction Register bit 4
		649	.equ DDB5 = 5 ; Port B Data Direction Register bit 5
		650	.equ DDB6 = 6 ; Port B Data Direction Register bit 6
		651	.equ DDB7 = 7 ; Port B Data Direction Register bit 7
		652
		653	; PINB - Port B Input Pins
		654	.equ PINB0 = 0 ; Port B Input Pins bit 0
		655	.equ PINB1 = 1 ; Port B Input Pins bit 1
		656	.equ PINB2 = 2 ; Port B Input Pins bit 2
		657	.equ PINB3 = 3 ; Port B Input Pins bit 3
		658	.equ PINB4 = 4 ; Port B Input Pins bit 4
		659	.equ PINB5 = 5 ; Port B Input Pins bit 5
		660	.equ PINB6 = 6 ; Port B Input Pins bit 6
		661	.equ PINB7 = 7 ; Port B Input Pins bit 7
		662
		663
		664	; *** PORTC **********************
		665	; PORTC - Port C Data Register
		666	.equ PORTC0 = 0 ; Port C Data Register bit 0
		667	.equ PC0 = 0 ; For compatibility
		668	.equ PORTC1 = 1 ; Port C Data Register bit 1
		669	.equ PC1 = 1 ; For compatibility
		670	.equ PORTC2 = 2 ; Port C Data Register bit 2
		671	.equ PC2 = 2 ; For compatibility
		672	.equ PORTC3 = 3 ; Port C Data Register bit 3
		673	.equ PC3 = 3 ; For compatibility
		674	.equ PORTC4 = 4 ; Port C Data Register bit 4
		675	.equ PC4 = 4 ; For compatibility
		676	.equ PORTC5 = 5 ; Port C Data Register bit 5
		677	.equ PC5 = 5 ; For compatibility
		678	.equ PORTC6 = 6 ; Port C Data Register bit 6
		679	.equ PC6 = 6 ; For compatibility
		680	.equ PORTC7 = 7 ; Port C Data Register bit 7
		681	.equ PC7 = 7 ; For compatibility
		682
		683	; DDRC - Port C Data Direction Register
		684	.equ DDC0 = 0 ; Port C Data Direction Register bit 0
		685	.equ DDC1 = 1 ; Port C Data Direction Register bit 1
		686	.equ DDC2 = 2 ; Port C Data Direction Register bit 2
		687	.equ DDC3 = 3 ; Port C Data Direction Register bit 3
		688	.equ DDC4 = 4 ; Port C Data Direction Register bit 4
		689	.equ DDC5 = 5 ; Port C Data Direction Register bit 5
		690	.equ DDC6 = 6 ; Port C Data Direction Register bit 6
		691	.equ DDC7 = 7 ; Port C Data Direction Register bit 7
		692
		693	; PINC - Port C Input Pins
		694	.equ PINC0 = 0 ; Port C Input Pins bit 0
		695	.equ PINC1 = 1 ; Port C Input Pins bit 1
		696	.equ PINC2 = 2 ; Port C Input Pins bit 2
		697	.equ PINC3 = 3 ; Port C Input Pins bit 3
		698	.equ PINC4 = 4 ; Port C Input Pins bit 4
		699	.equ PINC5 = 5 ; Port C Input Pins bit 5
		700	.equ PINC6 = 6 ; Port C Input Pins bit 6
		701	.equ PINC7 = 7 ; Port C Input Pins bit 7
		702
		703
		704	; *** PORTD **********************
		705	; PORTD - Port D Data Register
		706	.equ PORTD0 = 0 ; Port D Data Register bit 0
		707	.equ PD0 = 0 ; For compatibility
		708	.equ PORTD1 = 1 ; Port D Data Register bit 1
		709	.equ PD1 = 1 ; For compatibility
		710	.equ PORTD2 = 2 ; Port D Data Register bit 2
		711	.equ PD2 = 2 ; For compatibility
		712	.equ PORTD3 = 3 ; Port D Data Register bit 3
		713	.equ PD3 = 3 ; For compatibility
		714	.equ PORTD4 = 4 ; Port D Data Register bit 4
		715	.equ PD4 = 4 ; For compatibility
		716	.equ PORTD5 = 5 ; Port D Data Register bit 5
		717	.equ PD5 = 5 ; For compatibility
		718	.equ PORTD6 = 6 ; Port D Data Register bit 6
		719	.equ PD6 = 6 ; For compatibility
		720	.equ PORTD7 = 7 ; Port D Data Register bit 7
		721	.equ PD7 = 7 ; For compatibility
		722
		723	; DDRD - Port D Data Direction Register
		724	.equ DDD0 = 0 ; Port D Data Direction Register bit 0
		725	.equ DDD1 = 1 ; Port D Data Direction Register bit 1
		726	.equ DDD2 = 2 ; Port D Data Direction Register bit 2
		727	.equ DDD3 = 3 ; Port D Data Direction Register bit 3
		728	.equ DDD4 = 4 ; Port D Data Direction Register bit 4
		729	.equ DDD5 = 5 ; Port D Data Direction Register bit 5
		730	.equ DDD6 = 6 ; Port D Data Direction Register bit 6
		731	.equ DDD7 = 7 ; Port D Data Direction Register bit 7
		732
		733	; PIND - Port D Input Pins
		734	.equ PIND0 = 0 ; Port D Input Pins bit 0
		735	.equ PIND1 = 1 ; Port D Input Pins bit 1
		736	.equ PIND2 = 2 ; Port D Input Pins bit 2
		737	.equ PIND3 = 3 ; Port D Input Pins bit 3
		738	.equ PIND4 = 4 ; Port D Input Pins bit 4
		739	.equ PIND5 = 5 ; Port D Input Pins bit 5
		740	.equ PIND6 = 6 ; Port D Input Pins bit 6
		741	.equ PIND7 = 7 ; Port D Input Pins bit 7
		742
		743
		744	; *** PORTE **********************
		745	; PORTE - Data Register, Port E
		746	.equ PORTE0 = 0 ;
		747	.equ PE0 = 0 ; For compatibility
		748	.equ PORTE1 = 1 ;
		749	.equ PE1 = 1 ; For compatibility
		750	.equ PORTE2 = 2 ;
		751	.equ PE2 = 2 ; For compatibility
		752	.equ PORTE3 = 3 ;
		753	.equ PE3 = 3 ; For compatibility
		754	.equ PORTE4 = 4 ;
		755	.equ PE4 = 4 ; For compatibility
		756	.equ PORTE5 = 5 ;
		757	.equ PE5 = 5 ; For compatibility
		758	.equ PORTE6 = 6 ;
		759	.equ PE6 = 6 ; For compatibility
		760	.equ PORTE7 = 7 ;
		761	.equ PE7 = 7 ; For compatibility
		762
		763	; DDRE - Data Direction Register, Port E
		764	.equ DDE0 = 0 ;
		765	.equ DDE1 = 1 ;
		766	.equ DDE2 = 2 ;
		767	.equ DDE3 = 3 ;
		768	.equ DDE4 = 4 ;
		769	.equ DDE5 = 5 ;
		770	.equ DDE6 = 6 ;
		771	.equ DDE7 = 7 ;
		772
		773	; PINE - Input Pins, Port E
		774	.equ PINE0 = 0 ;
		775	.equ PINE1 = 1 ;
		776	.equ PINE2 = 2 ;
		777	.equ PINE3 = 3 ;
		778	.equ PINE4 = 4 ;
		779	.equ PINE5 = 5 ;
		780	.equ PINE6 = 6 ;
		781	.equ PINE7 = 7 ;
		782
		783
		784	; *** PORTF **********************
		785	; PORTF - Data Register, Port F
		786	.equ PORTF0 = 0 ;
		787	.equ PF0 = 0 ; For compatibility
		788	.equ PORTF1 = 1 ;
		789	.equ PF1 = 1 ; For compatibility
		790	.equ PORTF2 = 2 ;
		791	.equ PF2 = 2 ; For compatibility
		792	.equ PORTF3 = 3 ;
		793	.equ PF3 = 3 ; For compatibility
		794	.equ PORTF4 = 4 ;
		795	.equ PF4 = 4 ; For compatibility
		796	.equ PORTF5 = 5 ;
		797	.equ PF5 = 5 ; For compatibility
		798	.equ PORTF6 = 6 ;
		799	.equ PF6 = 6 ; For compatibility
		800	.equ PORTF7 = 7 ;
		801	.equ PF7 = 7 ; For compatibility
		802
		803	; DDRF - Data Direction Register, Port F
		804	.equ DDF0 = 0 ;
		805	.equ DDF1 = 1 ;
		806	.equ DDF2 = 2 ;
		807	.equ DDF3 = 3 ;
		808	.equ DDF4 = 4 ;
		809	.equ DDF5 = 5 ;
		810	.equ DDF6 = 6 ;
		811	.equ DDF7 = 7 ;
		812
		813	; PINF - Input Pins, Port F
		814	.equ PINF0 = 0 ;
		815	.equ PINF1 = 1 ;
		816	.equ PINF2 = 2 ;
		817	.equ PINF3 = 3 ;
		818	.equ PINF4 = 4 ;
		819	.equ PINF5 = 5 ;
		820	.equ PINF6 = 6 ;
		821	.equ PINF7 = 7 ;
		822
		823
		824	; *** PORTG **********************
		825	; PORTG - Data Register, Port G
		826	.equ PORTG0 = 0 ;
		827	.equ PG0 = 0 ; For compatibility
		828	.equ PORTG1 = 1 ;
		829	.equ PG1 = 1 ; For compatibility
		830	.equ PORTG2 = 2 ;
		831	.equ PG2 = 2 ; For compatibility
		832	.equ PORTG3 = 3 ;
		833	.equ PG3 = 3 ; For compatibility
		834	.equ PORTG4 = 4 ;
		835	.equ PG4 = 4 ; For compatibility
		836
		837	; DDRG - Data Direction Register, Port G
		838	.equ DDG0 = 0 ;
		839	.equ DDG1 = 1 ;
		840	.equ DDG2 = 2 ;
		841	.equ DDG3 = 3 ;
		842	.equ DDG4 = 4 ;
		843
		844	; PING - Input Pins, Port G
		845	.equ PING0 = 0 ;
		846	.equ PING1 = 1 ;
		847	.equ PING2 = 2 ;
		848	.equ PING3 = 3 ;
		849	.equ PING4 = 4 ;
		850
		851
		852	; *** TIMER_COUNTER_0 ************
		853	; TCCR0 - Timer/Counter Control Register
		854	.equ CS00 = 0 ; Clock Select 0
		855	.equ CS01 = 1 ; Clock Select 1
		856	.equ CS02 = 2 ; Clock Select 2
		857	.equ WGM01 = 3 ; Waveform Generation Mode 1
		858	.equ CTC0 = WGM01 ; For compatibility
		859	.equ COM00 = 4 ; Compare match Output Mode 0
		860	.equ COM01 = 5 ; Compare Match Output Mode 1
		861	.equ WGM00 = 6 ; Waveform Generation Mode 0
		862	.equ PWM0 = WGM00 ; For compatibility
		863	.equ FOC0 = 7 ; Force Output Compare
		864
		865	; TCNT0 - Timer/Counter Register
		866	.equ TCNT0_0 = 0 ;
		867	.equ TCNT0_1 = 1 ;
		868	.equ TCNT0_2 = 2 ;
		869	.equ TCNT0_3 = 3 ;
		870	.equ TCNT0_4 = 4 ;
		871	.equ TCNT0_5 = 5 ;
		872	.equ TCNT0_6 = 6 ;
		873	.equ TCNT0_7 = 7 ;
		874
		875	; OCR0 - Output Compare Register
		876	.equ OCR0_0 = 0 ;
		877	.equ OCR0_1 = 1 ;
		878	.equ OCR0_2 = 2 ;
		879	.equ OCR0_3 = 3 ;
		880	.equ OCR0_4 = 4 ;
		881	.equ OCR0_5 = 5 ;
		882	.equ OCR0_6 = 6 ;
		883	.equ OCR0_7 = 7 ;
		884
		885	; ASSR - Asynchronus Status Register
		886	.equ TCR0UB = 0 ; Timer/Counter Control Register 0 Update Busy
		887	.equ OCR0UB = 1 ; Output Compare register 0 Busy
		888	.equ TCN0UB = 2 ; Timer/Counter0 Update Busy
		889	.equ AS0 = 3 ; Asynchronus Timer/Counter 0
		890
		891	; TIMSK - Timer/Counter Interrupt Mask Register
		892	.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
		893	.equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register
		894
		895	; TIFR - Timer/Counter Interrupt Flag register
		896	.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
		897	.equ OCF0 = 1 ; Output Compare Flag 0
		898
		899	; SFIOR - Special Function IO Register
		900	;.equ PSR0 = 1 ; Prescaler Reset Timer/Counter0
		901	;.equ TSM = 7 ; Timer/Counter Synchronization Mode
		902
		903
		904	; *** TIMER_COUNTER_1 ************
		905	; TIMSK - Timer/Counter Interrupt Mask Register
		906	.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable
		907	.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable
		908	.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable
		909	.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
		910
		911	; ETIMSK - Extended Timer/Counter Interrupt Mask Register
		912	.equ OCIE1C = 0 ; Timer/Counter 1, Output Compare Match C Interrupt Enable
		913
		914	; TIFR - Timer/Counter Interrupt Flag register
		915	.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag
		916	.equ OCF1B = 3 ; Output Compare Flag 1B
		917	.equ OCF1A = 4 ; Output Compare Flag 1A
		918	.equ ICF1 = 5 ; Input Capture Flag 1
		919
		920	; ETIFR - Extended Timer/Counter Interrupt Flag register
		921	.equ OCF1C = 0 ; Timer/Counter 1, Output Compare C Match Flag
		922
		923	; SFIOR - Special Function IO Register
		924	;.equ PSR321 = 0 ; Prescaler Reset, T/C3, T/C2, T/C1
		925	;.equ TSM = 7 ; Timer/Counter Synchronization Mode
		926
		927	; TCCR1A - Timer/Counter1 Control Register A
		928	.equ WGM10 = 0 ; Waveform Generation Mode Bit 0
		929	.equ PWM10 = WGM10 ; For compatibility
		930	.equ WGM11 = 1 ; Waveform Generation Mode Bit 1
		931	.equ PWM11 = WGM11 ; For compatibility
		932	.equ COM1C0 = 2 ; Compare Output Mode 1C, bit 0
		933	.equ COM1C1 = 3 ; Compare Output Mode 1C, bit 1
		934	.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
		935	.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
		936	.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0
		937	.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
		938
		939	; TCCR1B - Timer/Counter1 Control Register B
		940	.equ CS10 = 0 ; Clock Select bit 0
		941	.equ CS11 = 1 ; Clock Select 1 bit 1
		942	.equ CS12 = 2 ; Clock Select1 bit 2
		943	.equ WGM12 = 3 ; Waveform Generation Mode
		944	.equ CTC10 = WGM12 ; For compatibility
		945	.equ WGM13 = 4 ; Waveform Generation Mode
		946	.equ CTC11 = WGM13 ; For compatibility
		947	.equ ICES1 = 6 ; Input Capture 1 Edge Select
		948	.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
		949
		950	; TCCR1C - Timer/Counter1 Control Register C
		951	.equ FOC1C = 5 ; Force Output Compare for channel C
		952	.equ FOC1B = 6 ; Force Output Compare for channel B
		953	.equ FOC1A = 7 ; Force Output Compare for channel A
		954
		955
		956	; *** TIMER_COUNTER_2 ************
		957	; TCCR2 - Timer/Counter Control Register
		958	.equ CS20 = 0 ; Clock Select
		959	.equ CS21 = 1 ; Clock Select
		960	.equ CS22 = 2 ; Clock Select
		961	.equ WGM21 = 3 ; Waveform Generation Mode
		962	.equ CTC2 = WGM21 ; For compatibility
		963	.equ COM20 = 4 ; Compare Match Output Mode
		964	.equ COM21 = 5 ; Compare Match Output Mode
		965	.equ WGM20 = 6 ; Wafeform Generation Mode
		966	.equ PWM2 = WGM20 ; For compatibility
		967	.equ FOC2 = 7 ; Force Output Compare
		968
		969	; TCNT2 - Timer/Counter Register
		970	.equ TCNT2_0 = 0 ; Timer/Counter Register Bit 0
		971	.equ TCNT2_1 = 1 ; Timer/Counter Register Bit 1
		972	.equ TCNT2_2 = 2 ; Timer/Counter Register Bit 2
		973	.equ TCNT2_3 = 3 ; Timer/Counter Register Bit 3
		974	.equ TCNT2_4 = 4 ; Timer/Counter Register Bit 4
		975	.equ TCNT2_5 = 5 ; Timer/Counter Register Bit 5
		976	.equ TCNT2_6 = 6 ; Timer/Counter Register Bit 6
		977	.equ TCNT2_7 = 7 ; Timer/Counter Register Bit 7
		978
		979	; OCR2 - Output Compare Register
		980	.equ OCR2_0 = 0 ; Output Compare Register Bit 0
		981	.equ OCR2_1 = 1 ; Output Compare Register Bit 1
		982	.equ OCR2_2 = 2 ; Output Compare Register Bit 2
		983	.equ OCR2_3 = 3 ; Output Compare Register Bit 3
		984	.equ OCR2_4 = 4 ; Output Compare Register Bit 4
		985	.equ OCR2_5 = 5 ; Output Compare Register Bit 5
		986	.equ OCR2_6 = 6 ; Output Compare Register Bit 6
		987	.equ OCR2_7 = 7 ; Output Compare Register Bit 7
		988
		989	; TIMSK -
		990	.equ TOIE2 = 6 ;
		991	.equ OCIE2 = 7 ;
		992
		993	; TIFR - Timer/Counter Interrupt Flag Register
		994	.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag
		995	.equ OCF2 = 7 ; Output Compare Flag 2
		996
		997
		998	; *** TIMER_COUNTER_3 ************
		999	; ETIMSK - Extended Timer/Counter Interrupt Mask Register
		1000	.equ OCIE3C = 1 ; Timer/Counter3, Output Compare Match Interrupt Enable
		1001	.equ TOIE3 = 2 ; Timer/Counter3 Overflow Interrupt Enable
		1002	.equ OCIE3B = 3 ; Timer/Counter3 Output CompareB Match Interrupt Enable
		1003	.equ OCIE3A = 4 ; Timer/Counter3 Output CompareA Match Interrupt Enable
		1004	.equ TICIE3 = 5 ; Timer/Counter3 Input Capture Interrupt Enable
		1005
		1006	; ETIFR - Extended Timer/Counter Interrupt Flag register
		1007	.equ OCF3C = 1 ; Timer/Counter3 Output Compare C Match Flag
		1008	.equ TOV3 = 2 ; Timer/Counter3 Overflow Flag
		1009	.equ OCF3B = 3 ; Output Compare Flag 1B
		1010	.equ OCF3A = 4 ; Output Compare Flag 1A
		1011	.equ ICF3 = 5 ; Input Capture Flag 1
		1012
		1013	; SFIOR - Special Function IO Register
		1014	;.equ PSR321 = 0 ; Prescaler Reset, T/C3, T/C2, T/C1
		1015	;.equ PSR1 = PSR321 ; For compatibility
		1016	;.equ PSR2 = PSR321 ; For compatibility
		1017	;.equ TSM = 7 ; Timer/Counter Synchronization Mode
		1018
		1019	; TCCR3A - Timer/Counter3 Control Register A
		1020	.equ WGM30 = 0 ; Waveform Generation Mode Bit 0
		1021	.equ PWM30 = WGM30 ; For compatibility
		1022	.equ WGM31 = 1 ; Waveform Generation Mode Bit 1
		1023	.equ PWM31 = WGM31 ; For compatibility
		1024	.equ COM3C0 = 2 ; Compare Output Mode 3C, bit 0
		1025	.equ COM3C1 = 3 ; Compare Output Mode 3C, bit 1
		1026	.equ COM3B0 = 4 ; Compare Output Mode 3B, bit 0
		1027	.equ COM3B1 = 5 ; Compare Output Mode 3B, bit 1
		1028	.equ COM3A0 = 6 ; Comparet Ouput Mode 3A, bit 0
		1029	.equ COM3A1 = 7 ; Compare Output Mode 3A, bit 1
		1030
		1031	; TCCR3B - Timer/Counter3 Control Register B
		1032	.equ CS30 = 0 ; Clock Select 3 bit 0
		1033	.equ CS31 = 1 ; Clock Select 3 bit 1
		1034	.equ CS32 = 2 ; Clock Select3 bit 2
		1035	.equ WGM32 = 3 ; Waveform Generation Mode
		1036	.equ CTC30 = WGM32 ; For compatibility
		1037	.equ WGM33 = 4 ; Waveform Generation Mode
		1038	.equ CTC31 = WGM33 ; For compatibility
		1039	.equ ICES3 = 6 ; Input Capture 3 Edge Select
		1040	.equ ICNC3 = 7 ; Input Capture 3 Noise Canceler
		1041
		1042	; TCCR3C - Timer/Counter3 Control Register C
		1043	.equ FOC3C = 5 ; Force Output Compare for channel C
		1044	.equ FOC3B = 6 ; Force Output Compare for channel B
		1045	.equ FOC3A = 7 ; Force Output Compare for channel A
		1046
		1047
		1048	; *** WATCHDOG *******************
		1049	; WDTCR - Watchdog Timer Control Register
		1050	.equ WDTCSR = WDTCR ; For compatibility
		1051	.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
		1052	.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
		1053	.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
		1054	.equ WDE = 3 ; Watch Dog Enable
		1055	.equ WDCE = 4 ; Watchdog Change Enable
		1056	.equ WDTOE = WDCE ; For compatibility
		1057
		1058
		1059
		1060	; *** LOCKSBITS ******************************************************
		1061	.equ LB1 = 0 ; Lock bit
		1062	.equ LB2 = 1 ; Lock bit
		1063	.equ BLB01 = 2 ; Boot Lock bit
		1064	.equ BLB02 = 3 ; Boot Lock bit
		1065	.equ BLB11 = 4 ; Boot lock bit
		1066	.equ BLB12 = 5 ; Boot lock bit
		1067
		1068
		1069	; *** FUSES **********************************************************
		1070	; LOW fuse bits
		1071	.equ CKSEL0 = 0 ; Select Clock Source
		1072	.equ CKSEL1 = 1 ; Select Clock Source
		1073	.equ CKSEL2 = 2 ; Select Clock Source
		1074	.equ CKSEL3 = 3 ; Select Clock Source
		1075	.equ SUT0 = 4 ; Select start-up time
		1076	.equ SUT1 = 5 ; Select start-up time
		1077	.equ BODEN = 6 ; Brown out detector enable
		1078	.equ BODLEVEL = 7 ; Brown out detector trigger level
		1079
		1080	; HIGH fuse bits
		1081	.equ BOOTRST = 0 ; Select Reset Vector
		1082	.equ BOOTSZ0 = 1 ; Select Boot Size
		1083	.equ BOOTSZ1 = 2 ; Select Boot Size
		1084	.equ EESAVE = 3 ; EEPROM memory is preserved through chip erase
		1085	.equ CKOPT = 4 ; Oscillator Options
		1086	.equ SPIEN = 5 ; Enable Serial programming and Data Downloading
		1087	.equ JTAGEN = 6 ; Enable JTAG
		1088	.equ OCDEN = 7 ; Enable OCD
		1089
		1090	; EXTENDED fuse bits
		1091	.equ WDTON = 0 ; Watchdog timer always on
		1092	.equ CompMode = 1 ; Compabillity mode
		1093
		1094
		1095
		1096	; *** CPU REGISTER DEFINITIONS ***************************************
		1097	.def XH = r27
		1098	.def XL = r26
		1099	.def YH = r29
		1100	.def YL = r28
		1101	.def ZH = r31
		1102	.def ZL = r30
		1103
		1104
		1105
		1106	; *** DATA MEMORY DECLARATIONS ***************************************
		1107	.equ FLASHEND = 0x7fff ; Note: Word address
		1108	.equ IOEND = 0x00ff
		1109	.equ SRAM_START = 0x0100
		1110	.equ SRAM_SIZE = 4096
		1111	.equ RAMEND = 0x10ff
		1112	.equ XRAMEND = 0xffff
		1113	.equ E2END = 0x07ff
		1114	.equ EEPROMEND = 0x07ff
		1115	.equ EEADRBITS = 11
		1116	#pragma AVRPART MEMORY PROG_FLASH 65536
		1117	#pragma AVRPART MEMORY EEPROM 2048
		1118	#pragma AVRPART MEMORY INT_SRAM SIZE 4096
		1119	#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x100
		1120
		1121
		1122
		1123	; *** BOOTLOADER DECLARATIONS ****************************************
		1124	.equ NRWW_START_ADDR = 0x7000
		1125	.equ NRWW_STOP_ADDR = 0x7fff
		1126	.equ RWW_START_ADDR = 0x0
		1127	.equ RWW_STOP_ADDR = 0x6fff
		1128	.equ PAGESIZE = 128
		1129	.equ FIRSTBOOTSTART = 0x7e00
		1130	.equ SECONDBOOTSTART = 0x7c00
		1131	.equ THIRDBOOTSTART = 0x7800
		1132	.equ FOURTHBOOTSTART = 0x7000
		1133	.equ SMALLBOOTSTART = FIRSTBOOTSTART
		1134	.equ LARGEBOOTSTART = FOURTHBOOTSTART
		1135
		1136
		1137
		1138	; *** INTERRUPT VECTORS **********************************************
		1139	.equ INT0addr = 0x0002 ; External Interrupt Request 0
		1140	.equ INT1addr = 0x0004 ; External Interrupt Request 1
		1141	.equ INT2addr = 0x0006 ; External Interrupt Request 2
		1142	.equ INT3addr = 0x0008 ; External Interrupt Request 3
		1143	.equ INT4addr = 0x000a ; External Interrupt Request 4
		1144	.equ INT5addr = 0x000c ; External Interrupt Request 5
		1145	.equ INT6addr = 0x000e ; External Interrupt Request 6
		1146	.equ INT7addr = 0x0010 ; External Interrupt Request 7
		1147	.equ OC2addr = 0x0012 ; Timer/Counter2 Compare Match
		1148	.equ OVF2addr = 0x0014 ; Timer/Counter2 Overflow
		1149	.equ ICP1addr = 0x0016 ; Timer/Counter1 Capture Event
		1150	.equ OC1Aaddr = 0x0018 ; Timer/Counter1 Compare Match A
		1151	.equ OC1Baddr = 0x001a ; Timer/Counter Compare Match B
		1152	.equ OVF1addr = 0x001c ; Timer/Counter1 Overflow
		1153	.equ OC0addr = 0x001e ; Timer/Counter0 Compare Match
		1154	.equ OVF0addr = 0x0020 ; Timer/Counter0 Overflow
		1155	.equ SPIaddr = 0x0022 ; SPI Serial Transfer Complete
		1156	.equ URXC0addr = 0x0024 ; USART0, Rx Complete
		1157	.equ UDRE0addr = 0x0026 ; USART0 Data Register Empty
		1158	.equ UTXC0addr = 0x0028 ; USART0, Tx Complete
		1159	.equ ADCCaddr = 0x002a ; ADC Conversion Complete
		1160	.equ ERDYaddr = 0x002c ; EEPROM Ready
		1161	.equ ACIaddr = 0x002e ; Analog Comparator
		1162	.equ OC1Caddr = 0x0030 ; Timer/Counter1 Compare Match C
		1163	.equ ICP3addr = 0x0032 ; Timer/Counter3 Capture Event
		1164	.equ OC3Aaddr = 0x0034 ; Timer/Counter3 Compare Match A
		1165	.equ OC3Baddr = 0x0036 ; Timer/Counter3 Compare Match B
		1166	.equ OC3Caddr = 0x0038 ; Timer/Counter3 Compare Match C
		1167	.equ OVF3addr = 0x003a ; Timer/Counter3 Overflow
		1168	.equ URXC1addr = 0x003c ; USART1, Rx Complete
		1169	.equ UDRE1addr = 0x003e ; USART1, Data Register Empty
		1170	.equ UTXC1addr = 0x0040 ; USART1, Tx Complete
		1171	.equ TWIaddr = 0x0042 ; 2-wire Serial Interface
		1172	.equ SPMRaddr = 0x0044 ; Store Program Memory Read
		1173
		1174	.equ INT_VECTORS_SIZE = 70 ; size in words
		1175
		1176	#endif /* _M64DEF_INC_ */
		1177
		1178	; *** END OF FILE ****************************************************

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(root)/contrib/toolchain/avra/includes/m64def.inc – Rev 6400