WebSVN – Kolibri OS – Blame – /contrib/toolchain/avra/includes/m103def.inc

Rev	Author	Line No.	Line
6400	punk_joker	1	;*** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************
		2	;*** Created: 2005-01-11 10:30 *** Source: ATmega103.xml *********
		3	;*************************************************************************
		4	;* A P P L I C A T I O N N O T E F O R T H E A V R F A M I L Y
		5	;*
		6	;* Number : AVR000
		7	;* File Name : "m103def.inc"
		8	;* Title : Register/Bit Definitions for the ATmega103
		9	;* Date : 2005-01-11
		10	;* Version : 2.14
		11	;* Support E-mail : avr@atmel.com
		12	;* Target MCU : ATmega103
		13	;*
		14	;* DESCRIPTION
		15	;* When including this file in the assembly program file, all I/O register
		16	;* names and I/O register bit names appearing in the data book can be used.
		17	;* In addition, the six registers forming the three data pointers X, Y and
		18	;* Z have been assigned names XL - ZH. Highest RAM address for Internal
		19	;* SRAM is also defined
		20	;*
		21	;* The Register names are represented by their hexadecimal address.
		22	;*
		23	;* The Register Bit names are represented by their bit number (0-7).
		24	;*
		25	;* Please observe the difference in using the bit names with instructions
		26	;* such as "sbr"/"cbr" (set/clear bit in register) and "sbrs"/"sbrc"
		27	;* (skip if bit in register set/cleared). The following example illustrates
		28	;* this:
		29	;*
		30	;* in r16,PORTB ;read PORTB latch
		31	;* sbr r16,(1<
		32	;* out PORTB,r16 ;output to PORTB
		33	;*
		34	;* in r16,TIFR ;read the Timer Interrupt Flag Register
		35	;* sbrc r16,TOV0 ;test the overflow flag (use bit#)
		36	;* rjmp TOV0_is_set ;jump if set
		37	;* ... ;otherwise do something else
		38	;*************************************************************************
		39
		40	#ifndef _M103DEF_INC_
		41	#define _M103DEF_INC_
		42
		43
		44	#pragma partinc 0
		45
		46	; *** SPECIFY DEVICE *************************************************
		47	.device ATmega103
		48	#pragma AVRPART ADMIN PART_NAME ATmega103
		49	.equ SIGNATURE_000 = 0x1e
		50	.equ SIGNATURE_001 = 0x97
		51	.equ SIGNATURE_002 = 0x01
		52
		53	#pragma AVRPART CORE CORE_VERSION V2
		54	#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED movw:break:lpm rd,z:spm
		55
		56
		57	; *** I/O REGISTER DEFINITIONS ***************************************
		58	; NOTE:
		59	; Definitions marked "MEMORY MAPPED"are extended I/O ports
		60	; and cannot be used with IN/OUT instructions
		61	.equ SREG = 0x3f
		62	.equ SPH = 0x3e
		63	.equ SPL = 0x3d
		64	.equ XDIV = 0x3c
		65	.equ RAMPZ = 0x3b
		66	.equ EICR = 0x3a
		67	.equ EIMSK = 0x39
		68	.equ EIFR = 0x38
		69	.equ TIMSK = 0x37
		70	.equ TIFR = 0x36
		71	.equ MCUCR = 0x35
		72	.equ MCUSR = 0x34
		73	.equ TCCR0 = 0x33
		74	.equ TCNT0 = 0x32
		75	.equ OCR0 = 0x31
		76	.equ ASSR = 0x30
		77	.equ TCCR1A = 0x2f
		78	.equ TCCR1B = 0x2e
		79	.equ TCNT1H = 0x2d
		80	.equ TCNT1L = 0x2c
		81	.equ OCR1AH = 0x2b
		82	.equ OCR1AL = 0x2a
		83	.equ OCR1BH = 0x29
		84	.equ OCR1BL = 0x28
		85	.equ ICR1H = 0x27
		86	.equ ICR1L = 0x26
		87	.equ TCCR2 = 0x25
		88	.equ TCNT2 = 0x24
		89	.equ OCR2 = 0x23
		90	.equ WDTCR = 0x21
		91	.equ EEARH = 0x1f
		92	.equ EEARL = 0x1e
		93	.equ EEDR = 0x1d
		94	.equ EECR = 0x1c
		95	.equ PORTA = 0x1b
		96	.equ DDRA = 0x1a
		97	.equ PINA = 0x19
		98	.equ PORTB = 0x18
		99	.equ DDRB = 0x17
		100	.equ PINB = 0x16
		101	.equ PORTC = 0x15
		102	.equ PORTD = 0x12
		103	.equ DDRD = 0x11
		104	.equ PIND = 0x10
		105	.equ SPDR = 0x0f
		106	.equ SPSR = 0x0e
		107	.equ SPCR = 0x0d
		108	.equ UDR = 0x0c
		109	.equ USR = 0x0b
		110	.equ UCR = 0x0a
		111	.equ UBRR = 0x09
		112	.equ ACSR = 0x08
		113	.equ ADMUX = 0x07
		114	.equ ADCSR = 0x06
		115	.equ ADCH = 0x05
		116	.equ ADCL = 0x04
		117	.equ PORTE = 0x03
		118	.equ DDRE = 0x02
		119	.equ PINE = 0x01
		120	.equ PINF = 0x00
		121
		122
		123	; *** BIT DEFINITIONS ************************************************
		124
		125	; *** AD_CONVERTER ***************
		126	; ADMUX - The ADC multiplexer Selection Register
		127	.equ MUX0 = 0 ; Analog Channel and Gain Selection Bits
		128	.equ MUX1 = 1 ; Analog Channel and Gain Selection Bits
		129	.equ MUX2 = 2 ; Analog Channel and Gain Selection Bits
		130
		131	; ADCSR - The ADC Control and Status register
		132	.equ ADPS0 = 0 ; ADC Prescaler Select Bits
		133	.equ ADPS1 = 1 ; ADC Prescaler Select Bits
		134	.equ ADPS2 = 2 ; ADC Prescaler Select Bits
		135	.equ ADIE = 3 ; ADC Interrupt Enable
		136	.equ ADIF = 4 ; ADC Interrupt Flag
		137	.equ ADSC = 6 ; ADC Start Conversion
		138	.equ ADEN = 7 ; ADC Enable
		139
		140	; ADCH - ADC Data Register High Byte
		141	.equ ADC8 = 0 ; ADC Data Register High Byte Bit 0
		142	.equ ADC9 = 1 ; ADC Data Register High Byte Bit 1
		143
		144	; ADCL - ADC Data Register Low Byte
		145	.equ ADC0 = 0 ; ADC Data Register Low Byte Bit 0
		146	.equ ADC1 = 1 ; ADC Data Register Low Byte Bit 1
		147	.equ ADC2 = 2 ; ADC Data Register Low Byte Bit 2
		148	.equ ADC3 = 3 ; ADC Data Register Low Byte Bit 3
		149	.equ ADC4 = 4 ; ADC Data Register Low Byte Bit 4
		150	.equ ADC5 = 5 ; ADC Data Register Low Byte Bit 5
		151	.equ ADC6 = 6 ; ADC Data Register Low Byte Bit 6
		152	.equ ADC7 = 7 ; ADC Data Register Low Byte Bit 7
		153
		154
		155	; *** ANALOG_COMPARATOR **********
		156	; ACSR - Analog Comparator Control And Status Register
		157	.equ ACIS0 = 0 ; Analog Comparator Interrupt Mode Select bit 0
		158	.equ ACIS1 = 1 ; Analog Comparator Interrupt Mode Select bit 1
		159	.equ ACIC = 2 ; Analog Comparator Input Capture Enable
		160	.equ ACIE = 3 ; Analog Comparator Interrupt Enable
		161	.equ ACI = 4 ; Analog Comparator Interrupt Flag
		162	.equ ACO = 5 ; Analog Comparator Output
		163	.equ ACD = 7 ; Analog Comparator Disable
		164
		165
		166	; *** SPI ************************
		167	; SPDR - SPI Data Register
		168	.equ SPDR0 = 0 ; SPI Data Register bit 0
		169	.equ SPDR1 = 1 ; SPI Data Register bit 1
		170	.equ SPDR2 = 2 ; SPI Data Register bit 2
		171	.equ SPDR3 = 3 ; SPI Data Register bit 3
		172	.equ SPDR4 = 4 ; SPI Data Register bit 4
		173	.equ SPDR5 = 5 ; SPI Data Register bit 5
		174	.equ SPDR6 = 6 ; SPI Data Register bit 6
		175	.equ SPDR7 = 7 ; SPI Data Register bit 7
		176
		177	; SPSR - SPI Status Register
		178	.equ WCOL = 6 ; Write Collision Flag
		179	.equ SPIF = 7 ; SPI Interrupt Flag
		180
		181	; SPCR - SPI Control Register
		182	.equ SPR0 = 0 ; SPI Clock Rate Select 0
		183	.equ SPR1 = 1 ; SPI Clock Rate Select 1
		184	.equ CPHA = 2 ; Clock Phase
		185	.equ CPOL = 3 ; Clock polarity
		186	.equ MSTR = 4 ; Master/Slave Select
		187	.equ DORD = 5 ; Data Order
		188	.equ SPE = 6 ; SPI Enable
		189	.equ SPIE = 7 ; SPI Interrupt Enable
		190
		191
		192	; *** UART ***********************
		193	; UDR - UART I/O Data Register
		194	.equ UDR0 = 0 ; UART I/O Data Register bit 0
		195	.equ UDR1 = 1 ; UART I/O Data Register bit 1
		196	.equ UDR2 = 2 ; UART I/O Data Register bit 2
		197	.equ UDR3 = 3 ; UART I/O Data Register bit 3
		198	.equ UDR4 = 4 ; UART I/O Data Register bit 4
		199	.equ UDR5 = 5 ; UART I/O Data Register bit 5
		200	.equ UDR6 = 6 ; UART I/O Data Register bit 6
		201	.equ UDR7 = 7 ; UART I/O Data Register bit 7
		202
		203	; USR - UART Status Register
		204	.equ DOR = 3 ; Data overRun
		205	.equ FE = 4 ; Framing Error
		206	.equ UDRE = 5 ; UART Data Register Empty
		207	.equ TXC = 6 ; UART Transmit Complete
		208	.equ RXC = 7 ; UART Receive Complete
		209
		210	; UCR - UART Control Register
		211	.equ TXB8 = 0 ; Transmit Data Bit 8
		212	.equ RXB8 = 1 ; Receive Data Bit 8
		213	.equ CHR9 = 2 ; 9-bit Characters
		214	.equ TXEN = 3 ; Transmitter Enable
		215	.equ RXEN = 4 ; Receiver Enable
		216	.equ UDRIE = 5 ; UART Data Register Empty Interrupt Enable
		217	.equ TXCIE = 6 ; TX Complete Interrupt Enable
		218	.equ RXCIE = 7 ; RX Complete Interrupt Enable
		219
		220	; UBRR - UART BAUD Rate Register
		221	.equ UBRR0 = 0 ; UART Baud Rate Register bit 0
		222	.equ UBRR1 = 1 ; UART Baud Rate Register bit 1
		223	.equ UBRR2 = 2 ; UART Baud Rate Register bit 2
		224	.equ UBRR3 = 3 ; UART Baud Rate Register bit 3
		225	.equ UBRR4 = 4 ; UART Baud Rate Register bit 4
		226	.equ UBRR5 = 5 ; UART Baud Rate Register bit 5
		227	.equ UBRR6 = 6 ; UART Baud Rate Register bit 6
		228	.equ UBRR7 = 7 ; UART Baud Rate Register bit 7
		229
		230
		231	; *** CPU ************************
		232	; SREG - Status Register
		233	.equ SREG_C = 0 ; Carry Flag
		234	.equ SREG_Z = 1 ; Zero Flag
		235	.equ SREG_N = 2 ; Negative Flag
		236	.equ SREG_V = 3 ; Two's Complement Overflow Flag
		237	.equ SREG_S = 4 ; Sign Bit
		238	.equ SREG_H = 5 ; Half Carry Flag
		239	.equ SREG_T = 6 ; Bit Copy Storage
		240	.equ SREG_I = 7 ; Global Interrupt Enable
		241
		242	; MCUCR - MCU Control Register
		243	.equ SM0 = 3 ; Sleep Mode Select
		244	.equ SM1 = 4 ; Sleep Mode Select
		245	.equ SE = 5 ; Sleep Enable
		246	.equ SRW = 6 ; External SRAM Wait State Select
		247	.equ SRE = 7 ; External SRAM Enable
		248
		249	; MCUSR - MCU Status Register
		250	.equ PORF = 0 ; Power-on reset flag
		251	.equ EXTRF = 1 ; External Reset Flag
		252	.equ EXTREF = EXTRF ; For compatibility
		253
		254	; XDIV - XTAL Divide Control Register
		255	.equ XDIV0 = 0 ; XTAl Divide Select Bit 0
		256	.equ XDIV1 = 1 ; XTAl Divide Select Bit 1
		257	.equ XDIV2 = 2 ; XTAl Divide Select Bit 2
		258	.equ XDIV3 = 3 ; XTAl Divide Select Bit 3
		259	.equ XDIV4 = 4 ; XTAl Divide Select Bit 4
		260	.equ XDIV5 = 5 ; XTAl Divide Select Bit 5
		261	.equ XDIV6 = 6 ; XTAl Divide Select Bit 6
		262	.equ XDIVEN = 7 ; XTAL Divide Enable
		263
		264	; RAMPZ - RAM Page Z Select Register
		265	.equ RAMPZ0 = 0 ; RAMPZ0 = 0: Program memory address $0000 - $7FFF. RAMPZ0 = 1, program memory address $8000 - $FFFF.
		266
		267
		268	; *** EXTERNAL_INTERRUPT *********
		269	; EICR - External Interrupt Control Register B
		270	.equ ISC40 = 0 ; External Interrupt 7-4 Sense Control Bit
		271	.equ ISC41 = 1 ; External Interrupt 7-4 Sense Control Bit
		272	.equ ISC50 = 2 ; External Interrupt 7-4 Sense Control Bit
		273	.equ ISC51 = 3 ; External Interrupt 7-4 Sense Control Bit
		274	.equ ISC60 = 4 ; External Interrupt 7-4 Sense Control Bit
		275	.equ ISC61 = 5 ; External Interrupt 7-4 Sense Control Bit
		276	.equ ISC70 = 6 ; External Interrupt 7-4 Sense Control Bit
		277	.equ ISC71 = 7 ; External Interrupt 7-4 Sense Control Bit
		278
		279	; EIMSK - External Interrupt Mask Register
		280	.equ INT0 = 0 ; External Interrupt Request 0 Enable
		281	.equ INT1 = 1 ; External Interrupt Request 1 Enable
		282	.equ INT2 = 2 ; External Interrupt Request 2 Enable
		283	.equ INT3 = 3 ; External Interrupt Request 3 Enable
		284	.equ INT4 = 4 ; External Interrupt Request 4 Enable
		285	.equ INT5 = 5 ; External Interrupt Request 5 Enable
		286	.equ INT6 = 6 ; External Interrupt Request 6 Enable
		287	.equ INT7 = 7 ; External Interrupt Request 7 Enable
		288
		289	; EIFR - External Interrupt Flag Register
		290	.equ INTF4 = 4 ; External Interrupt Flag 4
		291	.equ INTF5 = 5 ; External Interrupt Flag 5
		292	.equ INTF6 = 6 ; External Interrupt Flag 6
		293	.equ INTF7 = 7 ; External Interrupt Flag 7
		294
		295
		296	; *** EEPROM *********************
		297	; EEDR - EEPROM Data Register
		298	.equ EEDR0 = 0 ; EEPROM Data Register bit 0
		299	.equ EEDR1 = 1 ; EEPROM Data Register bit 1
		300	.equ EEDR2 = 2 ; EEPROM Data Register bit 2
		301	.equ EEDR3 = 3 ; EEPROM Data Register bit 3
		302	.equ EEDR4 = 4 ; EEPROM Data Register bit 4
		303	.equ EEDR5 = 5 ; EEPROM Data Register bit 5
		304	.equ EEDR6 = 6 ; EEPROM Data Register bit 6
		305	.equ EEDR7 = 7 ; EEPROM Data Register bit 7
		306
		307	; EECR - EEPROM Control Register
		308	.equ EERE = 0 ; EEPROM Read Enable
		309	.equ EEWE = 1 ; EEPROM Write Enable
		310	.equ EEMWE = 2 ; EEPROM Master Write Enable
		311	.equ EERIE = 3 ; EEPROM Ready Interrupt Enable
		312
		313
		314	; *** PORTA **********************
		315	; PORTA - Port A Data Register
		316	.equ PORTA0 = 0 ; Port A Data Register bit 0
		317	.equ PA0 = 0 ; For compatibility
		318	.equ PORTA1 = 1 ; Port A Data Register bit 1
		319	.equ PA1 = 1 ; For compatibility
		320	.equ PORTA2 = 2 ; Port A Data Register bit 2
		321	.equ PA2 = 2 ; For compatibility
		322	.equ PORTA3 = 3 ; Port A Data Register bit 3
		323	.equ PA3 = 3 ; For compatibility
		324	.equ PORTA4 = 4 ; Port A Data Register bit 4
		325	.equ PA4 = 4 ; For compatibility
		326	.equ PORTA5 = 5 ; Port A Data Register bit 5
		327	.equ PA5 = 5 ; For compatibility
		328	.equ PORTA6 = 6 ; Port A Data Register bit 6
		329	.equ PA6 = 6 ; For compatibility
		330	.equ PORTA7 = 7 ; Port A Data Register bit 7
		331	.equ PA7 = 7 ; For compatibility
		332
		333	; DDRA - Port A Data Direction Register
		334	.equ DDA0 = 0 ; Data Direction Register, Port A, bit 0
		335	.equ DDA1 = 1 ; Data Direction Register, Port A, bit 1
		336	.equ DDA2 = 2 ; Data Direction Register, Port A, bit 2
		337	.equ DDA3 = 3 ; Data Direction Register, Port A, bit 3
		338	.equ DDA4 = 4 ; Data Direction Register, Port A, bit 4
		339	.equ DDA5 = 5 ; Data Direction Register, Port A, bit 5
		340	.equ DDA6 = 6 ; Data Direction Register, Port A, bit 6
		341	.equ DDA7 = 7 ; Data Direction Register, Port A, bit 7
		342
		343	; PINA - Port A Input Pins
		344	.equ PINA0 = 0 ; Input Pins, Port A bit 0
		345	.equ PINA1 = 1 ; Input Pins, Port A bit 1
		346	.equ PINA2 = 2 ; Input Pins, Port A bit 2
		347	.equ PINA3 = 3 ; Input Pins, Port A bit 3
		348	.equ PINA4 = 4 ; Input Pins, Port A bit 4
		349	.equ PINA5 = 5 ; Input Pins, Port A bit 5
		350	.equ PINA6 = 6 ; Input Pins, Port A bit 6
		351	.equ PINA7 = 7 ; Input Pins, Port A bit 7
		352
		353
		354	; *** PORTB **********************
		355	; PORTB - Port B Data Register
		356	.equ PORTB0 = 0 ; Port B Data Register bit 0
		357	.equ PB0 = 0 ; For compatibility
		358	.equ PORTB1 = 1 ; Port B Data Register bit 1
		359	.equ PB1 = 1 ; For compatibility
		360	.equ PORTB2 = 2 ; Port B Data Register bit 2
		361	.equ PB2 = 2 ; For compatibility
		362	.equ PORTB3 = 3 ; Port B Data Register bit 3
		363	.equ PB3 = 3 ; For compatibility
		364	.equ PORTB4 = 4 ; Port B Data Register bit 4
		365	.equ PB4 = 4 ; For compatibility
		366	.equ PORTB5 = 5 ; Port B Data Register bit 5
		367	.equ PB5 = 5 ; For compatibility
		368	.equ PORTB6 = 6 ; Port B Data Register bit 6
		369	.equ PB6 = 6 ; For compatibility
		370	.equ PORTB7 = 7 ; Port B Data Register bit 7
		371	.equ PB7 = 7 ; For compatibility
		372
		373	; DDRB - Port B Data Direction Register
		374	.equ DDB0 = 0 ; Port B Data Direction Register bit 0
		375	.equ DDB1 = 1 ; Port B Data Direction Register bit 1
		376	.equ DDB2 = 2 ; Port B Data Direction Register bit 2
		377	.equ DDB3 = 3 ; Port B Data Direction Register bit 3
		378	.equ DDB4 = 4 ; Port B Data Direction Register bit 4
		379	.equ DDB5 = 5 ; Port B Data Direction Register bit 5
		380	.equ DDB6 = 6 ; Port B Data Direction Register bit 6
		381	.equ DDB7 = 7 ; Port B Data Direction Register bit 7
		382
		383	; PINB - Port B Input Pins
		384	.equ PINB0 = 0 ; Port B Input Pins bit 0
		385	.equ PINB1 = 1 ; Port B Input Pins bit 1
		386	.equ PINB2 = 2 ; Port B Input Pins bit 2
		387	.equ PINB3 = 3 ; Port B Input Pins bit 3
		388	.equ PINB4 = 4 ; Port B Input Pins bit 4
		389	.equ PINB5 = 5 ; Port B Input Pins bit 5
		390	.equ PINB6 = 6 ; Port B Input Pins bit 6
		391	.equ PINB7 = 7 ; Port B Input Pins bit 7
		392
		393
		394	; *** PORTD **********************
		395	; PORTD - Port D Data Register
		396	.equ PORTD0 = 0 ; Port D Data Register bit 0
		397	.equ PD0 = 0 ; For compatibility
		398	.equ PORTD1 = 1 ; Port D Data Register bit 1
		399	.equ PD1 = 1 ; For compatibility
		400	.equ PORTD2 = 2 ; Port D Data Register bit 2
		401	.equ PD2 = 2 ; For compatibility
		402	.equ PORTD3 = 3 ; Port D Data Register bit 3
		403	.equ PD3 = 3 ; For compatibility
		404	.equ PORTD4 = 4 ; Port D Data Register bit 4
		405	.equ PD4 = 4 ; For compatibility
		406	.equ PORTD5 = 5 ; Port D Data Register bit 5
		407	.equ PD5 = 5 ; For compatibility
		408	.equ PORTD6 = 6 ; Port D Data Register bit 6
		409	.equ PD6 = 6 ; For compatibility
		410	.equ PORTD7 = 7 ; Port D Data Register bit 7
		411	.equ PD7 = 7 ; For compatibility
		412
		413	; DDRD - Port D Data Direction Register
		414	.equ DDD0 = 0 ; Port D Data Direction Register bit 0
		415	.equ DDD1 = 1 ; Port D Data Direction Register bit 1
		416	.equ DDD2 = 2 ; Port D Data Direction Register bit 2
		417	.equ DDD3 = 3 ; Port D Data Direction Register bit 3
		418	.equ DDD4 = 4 ; Port D Data Direction Register bit 4
		419	.equ DDD5 = 5 ; Port D Data Direction Register bit 5
		420	.equ DDD6 = 6 ; Port D Data Direction Register bit 6
		421	.equ DDD7 = 7 ; Port D Data Direction Register bit 7
		422
		423	; PIND - Port D Input Pins
		424	.equ PIND0 = 0 ; Port D Input Pins bit 0
		425	.equ PIND1 = 1 ; Port D Input Pins bit 1
		426	.equ PIND2 = 2 ; Port D Input Pins bit 2
		427	.equ PIND3 = 3 ; Port D Input Pins bit 3
		428	.equ PIND4 = 4 ; Port D Input Pins bit 4
		429	.equ PIND5 = 5 ; Port D Input Pins bit 5
		430	.equ PIND6 = 6 ; Port D Input Pins bit 6
		431	.equ PIND7 = 7 ; Port D Input Pins bit 7
		432
		433
		434	; *** PORTC **********************
		435	; PORTC - Port C Data Register
		436	.equ PORTC0 = 0 ; Port C Data Register bit 0
		437	.equ PC0 = 0 ; For compatibility
		438	.equ PORTC1 = 1 ; Port C Data Register bit 1
		439	.equ PC1 = 1 ; For compatibility
		440	.equ PORTC2 = 2 ; Port C Data Register bit 2
		441	.equ PC2 = 2 ; For compatibility
		442	.equ PORTC3 = 3 ; Port C Data Register bit 3
		443	.equ PC3 = 3 ; For compatibility
		444	.equ PORTC4 = 4 ; Port C Data Register bit 4
		445	.equ PC4 = 4 ; For compatibility
		446	.equ PORTC5 = 5 ; Port C Data Register bit 5
		447	.equ PC5 = 5 ; For compatibility
		448	.equ PORTC6 = 6 ; Port C Data Register bit 6
		449	.equ PC6 = 6 ; For compatibility
		450	.equ PORTC7 = 7 ; Port C Data Register bit 7
		451	.equ PC7 = 7 ; For compatibility
		452
		453
		454	; *** PORTE **********************
		455	; PORTE - Data Register, Port E
		456	.equ PORTE0 = 0 ;
		457	.equ PE0 = 0 ; For compatibility
		458	.equ PORTE1 = 1 ;
		459	.equ PE1 = 1 ; For compatibility
		460	.equ PORTE2 = 2 ;
		461	.equ PE2 = 2 ; For compatibility
		462	.equ PORTE3 = 3 ;
		463	.equ PE3 = 3 ; For compatibility
		464	.equ PORTE4 = 4 ;
		465	.equ PE4 = 4 ; For compatibility
		466	.equ PORTE5 = 5 ;
		467	.equ PE5 = 5 ; For compatibility
		468	.equ PORTE6 = 6 ;
		469	.equ PE6 = 6 ; For compatibility
		470	.equ PORTE7 = 7 ;
		471	.equ PE7 = 7 ; For compatibility
		472
		473	; DDRE - Data Direction Register, Port E
		474	.equ DDE0 = 0 ;
		475	.equ DDE1 = 1 ;
		476	.equ DDE2 = 2 ;
		477	.equ DDE3 = 3 ;
		478	.equ DDE4 = 4 ;
		479	.equ DDE5 = 5 ;
		480	.equ DDE6 = 6 ;
		481	.equ DDE7 = 7 ;
		482
		483	; PINE - Input Pins, Port E
		484	.equ PINE0 = 0 ;
		485	.equ PINE1 = 1 ;
		486	.equ PINE2 = 2 ;
		487	.equ PINE3 = 3 ;
		488	.equ PINE4 = 4 ;
		489	.equ PINE5 = 5 ;
		490	.equ PINE6 = 6 ;
		491	.equ PINE7 = 7 ;
		492
		493
		494	; *** PORTF **********************
		495	; PINF - Input Pins, Port F
		496	.equ PINF0 = 0 ;
		497	.equ PINF1 = 1 ;
		498	.equ PINF2 = 2 ;
		499	.equ PINF3 = 3 ;
		500	.equ PINF4 = 4 ;
		501	.equ PINF5 = 5 ;
		502	.equ PINF6 = 6 ;
		503	.equ PINF7 = 7 ;
		504
		505
		506	; *** TIMER_COUNTER_2 ************
		507	; TIMSK - Timer/Counter Interrupt Mask register
		508	.equ TOIE2 = 6 ; Timer/Counter2 Overflow Interrupt Enable
		509	.equ OCIE2 = 7 ; Timer/Counter2 Output Compare Match Interrupt Enable
		510
		511	; TIFR - Timer/Counter Interrupt Flag Register
		512	.equ TOV2 = 6 ; Timer/Counter2 Overflow Flag
		513	.equ OCF2 = 7 ; Output Compare Flag 2
		514
		515	; TCCR2 - Timer/Counter2 Control Register
		516	.equ CS20 = 0 ; Clock Select bit 0
		517	.equ CS21 = 1 ; Clock Select bit 1
		518	.equ CS22 = 2 ; Clock Select bit 2
		519	.equ CTC2 = 3 ; Clear Timer/Counter2 on Compare Match
		520	.equ COM20 = 4 ; Compare Output Mode bit 0
		521	.equ COM21 = 5 ; Compare Output Mode bit 1
		522	.equ PWM2 = 6 ; Pulse Width Modulator Enable
		523
		524	; TCNT2 - Timer/Counter2
		525	.equ TCNT2_0 = 0 ; Timer/Counter 2 bit 0
		526	.equ TCNT2_1 = 1 ; Timer/Counter 2 bit 1
		527	.equ TCNT2_2 = 2 ; Timer/Counter 2 bit 2
		528	.equ TCNT2_3 = 3 ; Timer/Counter 2 bit 3
		529	.equ TCNT2_4 = 4 ; Timer/Counter 2 bit 4
		530	.equ TCNT2_5 = 5 ; Timer/Counter 2 bit 5
		531	.equ TCNT2_6 = 6 ; Timer/Counter 2 bit 6
		532	.equ TCNT2_7 = 7 ; Timer/Counter 2 bit 7
		533
		534	; OCR2 - Timer/Counter2 Output Compare Register
		535	.equ OCR2_0 = 0 ; Timer/Counter2 Output Compare Register Bit 0
		536	.equ OCR2_1 = 1 ; Timer/Counter2 Output Compare Register Bit 1
		537	.equ OCR2_2 = 2 ; Timer/Counter2 Output Compare Register Bit 2
		538	.equ OCR2_3 = 3 ; Timer/Counter2 Output Compare Register Bit 3
		539	.equ OCR2_4 = 4 ; Timer/Counter2 Output Compare Register Bit 4
		540	.equ OCR2_5 = 5 ; Timer/Counter2 Output Compare Register Bit 5
		541	.equ OCR2_6 = 6 ; Timer/Counter2 Output Compare Register Bit 6
		542	.equ OCR2_7 = 7 ; Timer/Counter2 Output Compare Register Bit 7
		543
		544
		545	; *** TIMER_COUNTER_0 ************
		546	; TCCR0 - Timer/Counter Control Register
		547	.equ CS00 = 0 ; Clock Select 1
		548	.equ CS01 = 1 ; Clock Select 1
		549	.equ CS02 = 2 ; Clock Select 2
		550	.equ CTC0 = 3 ; CLear Timer/Counter on Compare Match
		551	.equ COM00 = 4 ; Compare match Output Mode 0
		552	.equ COM01 = 5 ; Compare Match Output Mode 1
		553	.equ PWM0 = 6 ; Pulse Width Modulator Enable
		554
		555	; TCNT0 - Timer/Counter Register
		556	.equ TCNT0_0 = 0 ;
		557	.equ TCNT0_1 = 1 ;
		558	.equ TCNT0_2 = 2 ;
		559	.equ TCNT0_3 = 3 ;
		560	.equ TCNT0_4 = 4 ;
		561	.equ TCNT0_5 = 5 ;
		562	.equ TCNT0_6 = 6 ;
		563	.equ TCNT0_7 = 7 ;
		564
		565	; OCR0 - Output Compare Register
		566	.equ OCR0_0 = 0 ;
		567	.equ OCR0_1 = 1 ;
		568	.equ OCR0_2 = 2 ;
		569	.equ OCR0_3 = 3 ;
		570	.equ OCR0_4 = 4 ;
		571	.equ OCR0_5 = 5 ;
		572	.equ OCR0_6 = 6 ;
		573	.equ OCR0_7 = 7 ;
		574
		575	; ASSR - Asynchronus Status Register
		576	.equ TCR0UB = 0 ; Timer/Counter Control Register 0 Update Busy
		577	.equ OCR0UB = 1 ; Output Compare register 0 Busy
		578	.equ TCN0UB = 2 ; Timer/Couner0 Update Busy
		579	.equ AS0 = 3 ; Asynchronus Timer/Counter 0
		580
		581	; TIMSK - Timer/Counter Interrupt Mask Register
		582	.equ TOIE0 = 0 ; Timer/Counter0 Overflow Interrupt Enable
		583	.equ OCIE0 = 1 ; Timer/Counter0 Output Compare Match Interrupt register
		584
		585	; TIFR - Timer/Counter Interrupt Flag register
		586	.equ TOV0 = 0 ; Timer/Counter0 Overflow Flag
		587	.equ OCF0 = 1 ; Output Compare Flag 0
		588
		589
		590	; *** TIMER_COUNTER_1 ************
		591	; TIMSK - Timer/Counter Interrupt Mask Register
		592	.equ TOIE1 = 2 ; Timer/Counter1 Overflow Interrupt Enable
		593	.equ OCIE1B = 3 ; Timer/Counter1 Output CompareB Match Interrupt Enable
		594	.equ OCIE1A = 4 ; Timer/Counter1 Output CompareA Match Interrupt Enable
		595	.equ TICIE1 = 5 ; Timer/Counter1 Input Capture Interrupt Enable
		596
		597	; TIFR - Timer/Counter Interrupt Flag register
		598	.equ TOV1 = 2 ; Timer/Counter1 Overflow Flag
		599	.equ OCF1B = 3 ; Output Compare Flag 1B
		600	.equ OCF1A = 4 ; Output Compare Flag 1A
		601	.equ ICF1 = 5 ; Input Capture Flag 1
		602
		603	; TCCR1A - Timer/Counter1 Control Register A
		604	.equ PWM10 = 0 ; Pulse Width Modulator Select Bit 0
		605	.equ PWM11 = 1 ; Pulse Width Modulator Select Bit 1
		606	.equ COM1B0 = 4 ; Compare Output Mode 1B, bit 0
		607	.equ COM1B1 = 5 ; Compare Output Mode 1B, bit 1
		608	.equ COM1A0 = 6 ; Compare Ouput Mode 1A, bit 0
		609	.equ COM1A1 = 7 ; Compare Output Mode 1A, bit 1
		610
		611	; TCCR1B - Timer/Counter1 Control Register B
		612	.equ CS10 = 0 ; Clock Select1 bit 0
		613	.equ CS11 = 1 ; Clock Select1 bit 1
		614	.equ CS12 = 2 ; Clock Select1 bit 2
		615	.equ CTC1 = 3 ; Clear Timer/Counter1 on Compare Match
		616	.equ ICES1 = 6 ; Input Capture 1 Edge Select
		617	.equ ICNC1 = 7 ; Input Capture 1 Noise Canceler
		618
		619
		620	; *** WATCHDOG *******************
		621	; WDTCR - Watchdog Timer Control Register
		622	.equ WDP0 = 0 ; Watch Dog Timer Prescaler bit 0
		623	.equ WDP1 = 1 ; Watch Dog Timer Prescaler bit 1
		624	.equ WDP2 = 2 ; Watch Dog Timer Prescaler bit 2
		625	.equ WDE = 3 ; Watch Dog Enable
		626	.equ WDTOE = 4 ; RW
		627	.equ WDDE = WDTOE ; For compatibility
		628
		629
		630
		631	; *** LOCKSBITS ******************************************************
		632	.equ LB1 = 0 ; Lockbit
		633	.equ LB2 = 1 ; Lockbit
		634
		635
		636	; *** FUSES **********************************************************
		637	; LOW fuse bits
		638	.equ CKSEL0 = 0 ; Select Clock Source
		639	.equ CKSEL1 = 1 ; Select Clock Source
		640	.equ CKSEL2 = 2 ; Select Clock Source
		641	.equ CKSEL3 = 3 ; Select Clock Source
		642	.equ SUT0 = 4 ; Select start-up time
		643	.equ SUT1 = 5 ; Select start-up time
		644	.equ BODEN = 6 ; Brown out detector enable
		645	.equ BODLEVEL = 7 ; Brown out detector trigger level
		646
		647	; HIGH fuse bits
		648
		649	; EXTENDED fuse bits
		650
		651
		652
		653	; *** CPU REGISTER DEFINITIONS ***************************************
		654	.def XH = r27
		655	.def XL = r26
		656	.def YH = r29
		657	.def YL = r28
		658	.def ZH = r31
		659	.def ZL = r30
		660
		661
		662
		663	; *** DATA MEMORY DECLARATIONS ***************************************
		664	.equ FLASHEND = 0xffff ; Note: Word address
		665	.equ IOEND = 0x003f
		666	.equ SRAM_START = 0x0060
		667	.equ SRAM_SIZE = 4000
		668	.equ RAMEND = 0x0fff
		669	.equ XRAMEND = 0xffff
		670	.equ E2END = 0x0fff
		671	.equ EEPROMEND = 0x0fff
		672	.equ EEADRBITS = 12
		673	#pragma AVRPART MEMORY PROG_FLASH 131072
		674	#pragma AVRPART MEMORY EEPROM 4096
		675	#pragma AVRPART MEMORY INT_SRAM SIZE 4000
		676	#pragma AVRPART MEMORY INT_SRAM START_ADDR 0x60
		677
		678
		679
		680
		681
		682	; *** INTERRUPT VECTORS **********************************************
		683	.equ INT0addr = 0x0002 ; External Interrupt 0
		684	.equ INT1addr = 0x0004 ; External Interrupt 1
		685	.equ INT2addr = 0x0006 ; External Interrupt 2
		686	.equ INT3addr = 0x0008 ; External Interrupt 3
		687	.equ INT4addr = 0x000a ; External Interrupt 4
		688	.equ INT5addr = 0x000c ; External Interrupt 5
		689	.equ INT6addr = 0x000e ; External Interrupt 6
		690	.equ INT7addr = 0x0010 ; External Interrupt 7
		691	.equ OC2addr = 0x0012 ; Timer/Counter2 Compare Match
		692	.equ OVF2addr = 0x0014 ; Timer/Counter2 Overflow
		693	.equ ICP1addr = 0x0016 ; Timer/Counter1 Capture Event
		694	.equ OC1Aaddr = 0x0018 ; Timer/Counter1 Compare Match A
		695	.equ OC1Baddr = 0x001a ; Timer/Counter1 Compare Match B
		696	.equ OVF1addr = 0x001c ; Timer/Counter1 Overflow
		697	.equ OC0addr = 0x001e ; Timer/Counter0 Compare Match
		698	.equ OVF0addr = 0x0020 ; Timer/Counter0 Overflow
		699	.equ SPIaddr = 0x0022 ; SPI Serial Transfer Complete
		700	.equ URXCaddr = 0x0024 ; UART, Rx Complete
		701	.equ UDREaddr = 0x0026 ; UART Data Register Empty
		702	.equ UTXCaddr = 0x0028 ; UART, Tx Complete
		703	.equ ADCCaddr = 0x002a ; ADC Conversion Complete
		704	.equ ERDYaddr = 0x002c ; EEPROM Ready
		705	.equ ACIaddr = 0x002e ; Analog Comparator
		706
		707	.equ INT_VECTORS_SIZE = 48 ; size in words
		708
		709	#pragma AVRPART CORE INSTRUCTIONS_NOT_SUPPORTED break
		710
		711	#endif /* _M103DEF_INC_ */
		712
		713	; *** END OF FILE ****************************************************

Subversion Repositories Kolibri OS

(root)/contrib/toolchain/avra/includes/m103def.inc @ 6517 – Rev 6400