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4363 Serge 1 
/*
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 *
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 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
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 * All Rights Reserved.
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 *
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 * Permission is hereby granted, free of charge, to any person obtaining a
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 * copy of this software and associated documentation files (the
8 
 * "Software"), to deal in the Software without restriction, including
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 * without limitation the rights to use, copy, modify, merge, publish,
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 * distribute, sub license, and/or sell copies of the Software, and to
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 * permit persons to whom the Software is furnished to do so, subject to
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 * the following conditions:
13 
 *
14 
 * The above copyright notice and this permission notice (including the
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 * next paragraph) shall be included in all copies or substantial portions
16 
 * of the Software.
17 
 *
18 
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 
 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
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 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
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 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 
 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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 *
26 
 */
27 
 
28 
#ifndef _INTEL_CHIPSET_H
29 
#define _INTEL_CHIPSET_H
30 
 
31 
#define PCI_CHIP_I810			0x7121
32 
#define PCI_CHIP_I810_DC100		0x7123
33 
#define PCI_CHIP_I810_E			0x7125
34 
#define PCI_CHIP_I815			0x1132
35 
 
36 
#define PCI_CHIP_I830_M			0x3577
37 
#define PCI_CHIP_845_G			0x2562
38 
#define PCI_CHIP_I855_GM		0x3582
39 
#define PCI_CHIP_I865_G			0x2572
40 
 
41 
#define PCI_CHIP_I915_G			0x2582
42 
#define PCI_CHIP_E7221_G		0x258A
43 
#define PCI_CHIP_I915_GM		0x2592
44 
#define PCI_CHIP_I945_G			0x2772
45 
#define PCI_CHIP_I945_GM		0x27A2
46 
#define PCI_CHIP_I945_GME		0x27AE
47 
 
48 
#define PCI_CHIP_Q35_G			0x29B2
49 
#define PCI_CHIP_G33_G			0x29C2
50 
#define PCI_CHIP_Q33_G			0x29D2
51 
 
52 
#define PCI_CHIP_IGD_GM			0xA011
53 
#define PCI_CHIP_IGD_G			0xA001
54 
 
55 
#define IS_IGDGM(devid)		((devid) == PCI_CHIP_IGD_GM)
56 
#define IS_IGDG(devid)		((devid) == PCI_CHIP_IGD_G)
57 
#define IS_IGD(devid)		(IS_IGDG(devid) || IS_IGDGM(devid))
58 
 
59 
#define PCI_CHIP_I965_G			0x29A2
60 
#define PCI_CHIP_I965_Q			0x2992
61 
#define PCI_CHIP_I965_G_1		0x2982
62 
#define PCI_CHIP_I946_GZ		0x2972
63 
#define PCI_CHIP_I965_GM		0x2A02
64 
#define PCI_CHIP_I965_GME		0x2A12
65 
 
66 
#define PCI_CHIP_GM45_GM		0x2A42
67 
 
68 
#define PCI_CHIP_IGD_E_G		0x2E02
69 
#define PCI_CHIP_Q45_G			0x2E12
70 
#define PCI_CHIP_G45_G			0x2E22
71 
#define PCI_CHIP_G41_G			0x2E32
72 
 
73 
#define PCI_CHIP_ILD_G                  0x0042
74 
#define PCI_CHIP_ILM_G                  0x0046
75 
 
76 
#define PCI_CHIP_SANDYBRIDGE_GT1	0x0102 /* desktop */
77 
#define PCI_CHIP_SANDYBRIDGE_GT2	0x0112
78 
#define PCI_CHIP_SANDYBRIDGE_GT2_PLUS	0x0122
79 
#define PCI_CHIP_SANDYBRIDGE_M_GT1	0x0106 /* mobile */
80 
#define PCI_CHIP_SANDYBRIDGE_M_GT2	0x0116
81 
#define PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS	0x0126
82 
#define PCI_CHIP_SANDYBRIDGE_S		0x010A /* server */
83 
 
84 
#define PCI_CHIP_IVYBRIDGE_GT1		0x0152 /* desktop */
85 
#define PCI_CHIP_IVYBRIDGE_GT2		0x0162
86 
#define PCI_CHIP_IVYBRIDGE_M_GT1	0x0156 /* mobile */
87 
#define PCI_CHIP_IVYBRIDGE_M_GT2	0x0166
88 
#define PCI_CHIP_IVYBRIDGE_S		0x015a /* server */
89 
#define PCI_CHIP_IVYBRIDGE_S_GT2	0x016a /* server */
90 
 
91 
#define PCI_CHIP_HASWELL_GT1            0x0402 /* Desktop */
92 
#define PCI_CHIP_HASWELL_GT2            0x0412
93 
#define PCI_CHIP_HASWELL_GT3		0x0422
94 
#define PCI_CHIP_HASWELL_M_GT1          0x0406 /* Mobile */
95 
#define PCI_CHIP_HASWELL_M_GT2          0x0416
96 
#define PCI_CHIP_HASWELL_M_GT3		0x0426
97 
#define PCI_CHIP_HASWELL_S_GT1          0x040A /* Server */
98 
#define PCI_CHIP_HASWELL_S_GT2          0x041A
99 
#define PCI_CHIP_HASWELL_S_GT3		0x042A
100 
#define PCI_CHIP_HASWELL_B_GT1		0x040B /* Reserved */
101 
#define PCI_CHIP_HASWELL_B_GT2		0x041B
102 
#define PCI_CHIP_HASWELL_B_GT3		0x042B
103 
#define PCI_CHIP_HASWELL_E_GT1		0x040E /* Reserved */
104 
#define PCI_CHIP_HASWELL_E_GT2		0x041E
105 
#define PCI_CHIP_HASWELL_E_GT3		0x042E
106 
#define PCI_CHIP_HASWELL_SDV_GT1        0x0C02 /* Desktop */
107 
#define PCI_CHIP_HASWELL_SDV_GT2        0x0C12
108 
#define PCI_CHIP_HASWELL_SDV_GT3	0x0C22
109 
#define PCI_CHIP_HASWELL_SDV_M_GT1      0x0C06 /* Mobile */
110 
#define PCI_CHIP_HASWELL_SDV_M_GT2      0x0C16
111 
#define PCI_CHIP_HASWELL_SDV_M_GT3	0x0C26
112 
#define PCI_CHIP_HASWELL_SDV_S_GT1      0x0C0A /* Server */
113 
#define PCI_CHIP_HASWELL_SDV_S_GT2      0x0C1A
114 
#define PCI_CHIP_HASWELL_SDV_S_GT3	0x0C2A
115 
#define PCI_CHIP_HASWELL_SDV_B_GT1	0x0C0B /* Reserved */
116 
#define PCI_CHIP_HASWELL_SDV_B_GT2	0x0C1B
117 
#define PCI_CHIP_HASWELL_SDV_B_GT3	0x0C2B
118 
#define PCI_CHIP_HASWELL_SDV_E_GT1	0x0C0E /* Reserved */
119 
#define PCI_CHIP_HASWELL_SDV_E_GT2	0x0C1E
120 
#define PCI_CHIP_HASWELL_SDV_E_GT3	0x0C2E
121 
#define PCI_CHIP_HASWELL_ULT_GT1        0x0A02 /* Desktop */
122 
#define PCI_CHIP_HASWELL_ULT_GT2        0x0A12
123 
#define PCI_CHIP_HASWELL_ULT_GT3	0x0A22
124 
#define PCI_CHIP_HASWELL_ULT_M_GT1      0x0A06 /* Mobile */
125 
#define PCI_CHIP_HASWELL_ULT_M_GT2      0x0A16
126 
#define PCI_CHIP_HASWELL_ULT_M_GT3	0x0A26
127 
#define PCI_CHIP_HASWELL_ULT_S_GT1      0x0A0A /* Server */
128 
#define PCI_CHIP_HASWELL_ULT_S_GT2      0x0A1A
129 
#define PCI_CHIP_HASWELL_ULT_S_GT3	0x0A2A
130 
#define PCI_CHIP_HASWELL_ULT_B_GT1	0x0A0B /* Reserved */
131 
#define PCI_CHIP_HASWELL_ULT_B_GT2	0x0A1B
132 
#define PCI_CHIP_HASWELL_ULT_B_GT3	0x0A2B
133 
#define PCI_CHIP_HASWELL_ULT_E_GT1	0x0A0E /* Reserved */
134 
#define PCI_CHIP_HASWELL_ULT_E_GT2	0x0A1E
135 
#define PCI_CHIP_HASWELL_ULT_E_GT3	0x0A2E
136 
#define PCI_CHIP_HASWELL_CRW_GT1	0x0D02 /* Desktop */
137 
#define PCI_CHIP_HASWELL_CRW_GT2	0x0D12
138 
#define PCI_CHIP_HASWELL_CRW_GT3	0x0D22
139 
#define PCI_CHIP_HASWELL_CRW_M_GT1	0x0D06 /* Mobile */
140 
#define PCI_CHIP_HASWELL_CRW_M_GT2	0x0D16
141 
#define PCI_CHIP_HASWELL_CRW_M_GT3	0x0D26
142 
#define PCI_CHIP_HASWELL_CRW_S_GT1	0x0D0A /* Server */
143 
#define PCI_CHIP_HASWELL_CRW_S_GT2	0x0D1A
144 
#define PCI_CHIP_HASWELL_CRW_S_GT3	0x0D2A
145 
#define PCI_CHIP_HASWELL_CRW_B_GT1	0x0D0B /* Reserved */
146 
#define PCI_CHIP_HASWELL_CRW_B_GT2	0x0D1B
147 
#define PCI_CHIP_HASWELL_CRW_B_GT3	0x0D2B
148 
#define PCI_CHIP_HASWELL_CRW_E_GT1	0x0D0E /* Reserved */
149 
#define PCI_CHIP_HASWELL_CRW_E_GT2	0x0D1E
150 
#define PCI_CHIP_HASWELL_CRW_E_GT3	0x0D2E
151 
#define BDW_SPARE			0x2
152 
#define BDW_ULT				0x6
153 
#define BDW_SERVER			0xa
154 
#define BDW_IRIS			0xb
155 
#define BDW_WORKSTATION			0xd
156 
#define BDW_ULX				0xe
157 
 
158 
#define PCI_CHIP_VALLEYVIEW_PO		0x0f30 /* VLV PO board */
159 
#define PCI_CHIP_VALLEYVIEW_1		0x0f31
160 
#define PCI_CHIP_VALLEYVIEW_2		0x0f32
161 
#define PCI_CHIP_VALLEYVIEW_3		0x0f33
162 
 
163 
#define IS_MOBILE(devid)	((devid) == PCI_CHIP_I855_GM || \
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				 (devid) == PCI_CHIP_I915_GM || \
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				 (devid) == PCI_CHIP_I945_GM || \
166 
				 (devid) == PCI_CHIP_I945_GME || \
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				 (devid) == PCI_CHIP_I965_GM || \
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				 (devid) == PCI_CHIP_I965_GME || \
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				 (devid) == PCI_CHIP_GM45_GM || IS_IGD(devid) || \
170 
				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
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				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2)
172 
 
173 
#define IS_G45(devid)		((devid) == PCI_CHIP_IGD_E_G || \
174 
				 (devid) == PCI_CHIP_Q45_G || \
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				 (devid) == PCI_CHIP_G45_G || \
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				 (devid) == PCI_CHIP_G41_G)
177 
#define IS_GM45(devid)		((devid) == PCI_CHIP_GM45_GM)
178 
#define IS_G4X(devid)		(IS_G45(devid) || IS_GM45(devid))
179 
 
180 
#define IS_ILD(devid)		((devid) == PCI_CHIP_ILD_G)
181 
#define IS_ILM(devid)		((devid) == PCI_CHIP_ILM_G)
182 
 
183 
#define IS_915(devid)		((devid) == PCI_CHIP_I915_G || \
184 
				 (devid) == PCI_CHIP_E7221_G || \
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				 (devid) == PCI_CHIP_I915_GM)
186 
 
187 
#define IS_945GM(devid)		((devid) == PCI_CHIP_I945_GM || \
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				 (devid) == PCI_CHIP_I945_GME)
189 
 
190 
#define IS_945(devid)		((devid) == PCI_CHIP_I945_G || \
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				 (devid) == PCI_CHIP_I945_GM || \
192 
				 (devid) == PCI_CHIP_I945_GME || \
193 
				 IS_G33(devid))
194 
 
195 
#define IS_G33(devid)		((devid) == PCI_CHIP_G33_G || \
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				 (devid) == PCI_CHIP_Q33_G || \
197 
				 (devid) == PCI_CHIP_Q35_G || IS_IGD(devid))
198 
 
199 
#define IS_GEN2(devid)		((devid) == PCI_CHIP_I830_M || \
200 
				 (devid) == PCI_CHIP_845_G || \
201 
				 (devid) == PCI_CHIP_I855_GM || \
202 
				 (devid) == PCI_CHIP_I865_G)
203 
 
204 
#define IS_GEN3(devid)		(IS_945(devid) || IS_915(devid))
205 
 
206 
#define IS_GEN4(devid)		((devid) == PCI_CHIP_I965_G || \
207 
				 (devid) == PCI_CHIP_I965_Q || \
208 
				 (devid) == PCI_CHIP_I965_G_1 || \
209 
				 (devid) == PCI_CHIP_I965_GM || \
210 
				 (devid) == PCI_CHIP_I965_GME || \
211 
				 (devid) == PCI_CHIP_I946_GZ || \
212 
				 IS_G4X(devid))
213 
 
214 
#define IS_GEN5(devid)		(IS_ILD(devid) || IS_ILM(devid))
215 
 
216 
#define IS_GEN6(devid)		((devid) == PCI_CHIP_SANDYBRIDGE_GT1 || \
217 
				 (devid) == PCI_CHIP_SANDYBRIDGE_GT2 || \
218 
				 (devid) == PCI_CHIP_SANDYBRIDGE_GT2_PLUS || \
219 
				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT1 || \
220 
				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2 || \
221 
				 (devid) == PCI_CHIP_SANDYBRIDGE_M_GT2_PLUS || \
222 
				 (devid) == PCI_CHIP_SANDYBRIDGE_S)
223 
 
224 
#define IS_GEN7(devid)          (IS_IVYBRIDGE(devid) || \
225 
                                 IS_HASWELL(devid) || \
226 
				 IS_VALLEYVIEW(devid))
227 
 
228 
#define IS_IVYBRIDGE(devid)	((devid) == PCI_CHIP_IVYBRIDGE_GT1 || \
229 
				 (devid) == PCI_CHIP_IVYBRIDGE_GT2 || \
230 
				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT1 || \
231 
				 (devid) == PCI_CHIP_IVYBRIDGE_M_GT2 || \
232 
				 (devid) == PCI_CHIP_IVYBRIDGE_S || \
233 
				 (devid) == PCI_CHIP_IVYBRIDGE_S_GT2)
234 
 
235 
#define IS_VALLEYVIEW(devid)	((devid) == PCI_CHIP_VALLEYVIEW_PO || \
236 
				 (devid) == PCI_CHIP_VALLEYVIEW_1 || \
237 
				 (devid) == PCI_CHIP_VALLEYVIEW_2 || \
238 
				 (devid) == PCI_CHIP_VALLEYVIEW_3)
239 
 
240 
#define IS_HSW_GT1(devid)	((devid) == PCI_CHIP_HASWELL_GT1 || \
241 
				 (devid) == PCI_CHIP_HASWELL_M_GT1 || \
242 
				 (devid) == PCI_CHIP_HASWELL_S_GT1 || \
243 
				 (devid) == PCI_CHIP_HASWELL_B_GT1 || \
244 
				 (devid) == PCI_CHIP_HASWELL_E_GT1 || \
245 
				 (devid) == PCI_CHIP_HASWELL_SDV_GT1 || \
246 
				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT1 || \
247 
				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT1 || \
248 
				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT1 || \
249 
				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT1 || \
250 
				 (devid) == PCI_CHIP_HASWELL_ULT_GT1 || \
251 
				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT1 || \
252 
				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT1 || \
253 
				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT1 || \
254 
				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT1 || \
255 
				 (devid) == PCI_CHIP_HASWELL_CRW_GT1 || \
256 
				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT1 || \
257 
				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT1 || \
258 
				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT1 || \
259 
				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT1)
260 
#define IS_HSW_GT2(devid)	((devid) == PCI_CHIP_HASWELL_GT2 || \
261 
				 (devid) == PCI_CHIP_HASWELL_M_GT2 || \
262 
				 (devid) == PCI_CHIP_HASWELL_S_GT2 || \
263 
				 (devid) == PCI_CHIP_HASWELL_B_GT2 || \
264 
				 (devid) == PCI_CHIP_HASWELL_E_GT2 || \
265 
				 (devid) == PCI_CHIP_HASWELL_SDV_GT2 || \
266 
				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT2 || \
267 
				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT2 || \
268 
				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT2 || \
269 
				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT2 || \
270 
				 (devid) == PCI_CHIP_HASWELL_ULT_GT2 || \
271 
				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT2 || \
272 
				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT2 || \
273 
				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT2 || \
274 
				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT2 || \
275 
				 (devid) == PCI_CHIP_HASWELL_CRW_GT2 || \
276 
				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT2 || \
277 
				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT2 || \
278 
				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT2 || \
279 
				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT2)
280 
#define IS_HSW_GT3(devid)	((devid) == PCI_CHIP_HASWELL_GT3 || \
281 
				 (devid) == PCI_CHIP_HASWELL_M_GT3 || \
282 
				 (devid) == PCI_CHIP_HASWELL_S_GT3 || \
283 
				 (devid) == PCI_CHIP_HASWELL_B_GT3 || \
284 
				 (devid) == PCI_CHIP_HASWELL_E_GT3 || \
285 
				 (devid) == PCI_CHIP_HASWELL_SDV_GT3 || \
286 
				 (devid) == PCI_CHIP_HASWELL_SDV_M_GT3 || \
287 
				 (devid) == PCI_CHIP_HASWELL_SDV_S_GT3 || \
288 
				 (devid) == PCI_CHIP_HASWELL_SDV_B_GT3 || \
289 
				 (devid) == PCI_CHIP_HASWELL_SDV_E_GT3 || \
290 
				 (devid) == PCI_CHIP_HASWELL_ULT_GT3 || \
291 
				 (devid) == PCI_CHIP_HASWELL_ULT_M_GT3 || \
292 
				 (devid) == PCI_CHIP_HASWELL_ULT_S_GT3 || \
293 
				 (devid) == PCI_CHIP_HASWELL_ULT_B_GT3 || \
294 
				 (devid) == PCI_CHIP_HASWELL_ULT_E_GT3 || \
295 
				 (devid) == PCI_CHIP_HASWELL_CRW_GT3 || \
296 
				 (devid) == PCI_CHIP_HASWELL_CRW_M_GT3 || \
297 
				 (devid) == PCI_CHIP_HASWELL_CRW_S_GT3 || \
298 
				 (devid) == PCI_CHIP_HASWELL_CRW_B_GT3 || \
299 
				 (devid) == PCI_CHIP_HASWELL_CRW_E_GT3)
300 
 
301 
#define IS_HASWELL(devid)       (IS_HSW_GT1(devid) || \
302 
				 IS_HSW_GT2(devid) || \
303 
				 IS_HSW_GT3(devid))
304 
 
305 
#define IS_BROADWELL(devid)     (((devid & 0xff00) != 0x1600) ? 0 : \
306 
				(((devid & 0x00f0) >> 4) > 3) ? 0 : \
307 
				((devid & 0x000f) == BDW_SPARE) ? 1 : \
308 
				((devid & 0x000f) == BDW_ULT) ? 1 : \
309 
				((devid & 0x000f) == BDW_IRIS) ? 1 : \
310 
				((devid & 0x000f) == BDW_SERVER) ? 1 : \
311 
				((devid & 0x000f) == BDW_WORKSTATION) ? 1 : \
312 
				((devid & 0x000f) == BDW_ULX) ? 1 : 0)
313 
 
314 
 
315 
#define IS_GEN8(devid)		IS_BROADWELL(devid)
316 
 
317 
#define IS_9XX(dev)		(IS_GEN3(dev) || \
318 
				 IS_GEN4(dev) || \
319 
				 IS_GEN5(dev) || \
320 
				 IS_GEN6(dev) || \
321 
				 IS_GEN7(dev) || \
322 
				 IS_GEN8(dev))
323 
 
324 
 
325 
#endif /* _INTEL_CHIPSET_H */