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/* Definitions of target machine for GCC for IA-32.

   Copyright (C) 1988, 1992, 1994, 1995, 1996, 1997, 1998, 1999, 2000,

   2001, 2002, 2003, 2004, 2005, 2006, 2007, 2008, 2009, 2010

   Free Software Foundation, Inc.

This file is part of GCC.

GCC is free software; you can redistribute it and/or modify

it under the terms of the GNU General Public License as published by

the Free Software Foundation; either version 3, or (at your option)

any later version.

GCC is distributed in the hope that it will be useful,

but WITHOUT ANY WARRANTY; without even the implied warranty of

MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

GNU General Public License for more details.

Under Section 7 of GPL version 3, you are granted additional

permissions described in the GCC Runtime Library Exception, version

3.1, as published by the Free Software Foundation.

You should have received a copy of the GNU General Public License and

a copy of the GCC Runtime Library Exception along with this program;

see the files COPYING3 and COPYING.RUNTIME respectively.  If not, see

.  */

/* The purpose of this file is to define the characteristics of the i386,

   independent of assembler syntax or operating system.

   Three other files build on this one to describe a specific assembler syntax:

   bsd386.h, att386.h, and sun386.h.

   The actual tm.h file for a particular system should include

   this file, and then the file for the appropriate assembler syntax.

   Many macros that specify assembler syntax are omitted entirely from

   this file because they really belong in the files for particular

   assemblers.  These include RP, IP, LPREFIX, PUT_OP_SIZE, USE_STAR,

   ADDR_BEG, ADDR_END, PRINT_IREG, PRINT_SCALE, PRINT_B_I_S, and many

   that start with ASM_ or end in ASM_OP.  */

/* Redefines for option macros.  */

#define TARGET_64BIT	OPTION_ISA_64BIT

#define TARGET_MMX	OPTION_ISA_MMX

#define TARGET_3DNOW	OPTION_ISA_3DNOW

#define TARGET_3DNOW_A	OPTION_ISA_3DNOW_A

#define TARGET_SSE	OPTION_ISA_SSE

#define TARGET_SSE2	OPTION_ISA_SSE2

#define TARGET_SSE3	OPTION_ISA_SSE3

#define TARGET_SSSE3	OPTION_ISA_SSSE3

#define TARGET_SSE4_1	OPTION_ISA_SSE4_1

#define TARGET_SSE4_2	OPTION_ISA_SSE4_2

#define TARGET_AVX	OPTION_ISA_AVX

#define TARGET_FMA	OPTION_ISA_FMA

#define TARGET_SSE4A	OPTION_ISA_SSE4A

#define TARGET_FMA4	OPTION_ISA_FMA4

#define TARGET_XOP	OPTION_ISA_XOP

#define TARGET_LWP	OPTION_ISA_LWP

#define TARGET_ROUND	OPTION_ISA_ROUND

#define TARGET_ABM	OPTION_ISA_ABM

#define TARGET_POPCNT	OPTION_ISA_POPCNT

#define TARGET_SAHF	OPTION_ISA_SAHF

#define TARGET_MOVBE	OPTION_ISA_MOVBE

#define TARGET_CRC32	OPTION_ISA_CRC32

#define TARGET_AES	OPTION_ISA_AES

#define TARGET_PCLMUL	OPTION_ISA_PCLMUL

#define TARGET_CMPXCHG16B OPTION_ISA_CX16

/* SSE4.1 defines round instructions */

#define	OPTION_MASK_ISA_ROUND	OPTION_MASK_ISA_SSE4_1

#define	OPTION_ISA_ROUND	((ix86_isa_flags & OPTION_MASK_ISA_ROUND) != 0)

#include "config/vxworks-dummy.h"

/* Algorithm to expand string function with.  */

enum stringop_alg

{

   no_stringop,

   libcall,

   rep_prefix_1_byte,

   rep_prefix_4_byte,

   rep_prefix_8_byte,

   loop_1_byte,

   loop,

   unrolled_loop

};

#define NAX_STRINGOP_ALGS 4

/* Specify what algorithm to use for stringops on known size.

   When size is unknown, the UNKNOWN_SIZE alg is used.  When size is

   known at compile time or estimated via feedback, the SIZE array

   is walked in order until MAX is greater then the estimate (or -1

   means infinity).  Corresponding ALG is used then.

   For example initializer:

    {{256, loop}, {-1, rep_prefix_4_byte}}

   will use loop for blocks smaller or equal to 256 bytes, rep prefix will

   be used otherwise.  */

struct stringop_algs

{

  const enum stringop_alg unknown_size;

  const struct stringop_strategy {

    const int max;

    const enum stringop_alg alg;

  } size [NAX_STRINGOP_ALGS];

};

/* Define the specific costs for a given cpu */

struct processor_costs {

  const int add;		/* cost of an add instruction */

  const int lea;		/* cost of a lea instruction */

  const int shift_var;		/* variable shift costs */

  const int shift_const;	/* constant shift costs */

  const int mult_init[5];	/* cost of starting a multiply

				   in QImode, HImode, SImode, DImode, TImode*/

  const int mult_bit;		/* cost of multiply per each bit set */

  const int divide[5];		/* cost of a divide/mod

				   in QImode, HImode, SImode, DImode, TImode*/

  int movsx;			/* The cost of movsx operation.  */

  int movzx;			/* The cost of movzx operation.  */

  const int large_insn;		/* insns larger than this cost more */

  const int move_ratio;		/* The threshold of number of scalar

				   memory-to-memory move insns.  */

  const int movzbl_load;	/* cost of loading using movzbl */

  const int int_load[3];	/* cost of loading integer registers

				   in QImode, HImode and SImode relative

				   to reg-reg move (2).  */

  const int int_store[3];	/* cost of storing integer register

				   in QImode, HImode and SImode */

  const int fp_move;		/* cost of reg,reg fld/fst */

  const int fp_load[3];		/* cost of loading FP register

				   in SFmode, DFmode and XFmode */

  const int fp_store[3];	/* cost of storing FP register

				   in SFmode, DFmode and XFmode */

  const int mmx_move;		/* cost of moving MMX register.  */

  const int mmx_load[2];	/* cost of loading MMX register

				   in SImode and DImode */

  const int mmx_store[2];	/* cost of storing MMX register

				   in SImode and DImode */

  const int sse_move;		/* cost of moving SSE register.  */

  const int sse_load[3];	/* cost of loading SSE register

				   in SImode, DImode and TImode*/

  const int sse_store[3];	/* cost of storing SSE register

				   in SImode, DImode and TImode*/

  const int mmxsse_to_integer;	/* cost of moving mmxsse register to

				   integer and vice versa.  */

  const int l1_cache_size;	/* size of l1 cache, in kilobytes.  */

  const int l2_cache_size;	/* size of l2 cache, in kilobytes.  */

  const int prefetch_block;	/* bytes moved to cache for prefetch.  */

  const int simultaneous_prefetches; /* number of parallel prefetch

				   operations.  */

  const int branch_cost;	/* Default value for BRANCH_COST.  */

  const int fadd;		/* cost of FADD and FSUB instructions.  */

  const int fmul;		/* cost of FMUL instruction.  */

  const int fdiv;		/* cost of FDIV instruction.  */

  const int fabs;		/* cost of FABS instruction.  */

  const int fchs;		/* cost of FCHS instruction.  */

  const int fsqrt;		/* cost of FSQRT instruction.  */

				/* Specify what algorithm

				   to use for stringops on unknown size.  */

  struct stringop_algs memcpy[2], memset[2];

  const int scalar_stmt_cost;   /* Cost of any scalar operation, excluding

				   load and store.  */

  const int scalar_load_cost;   /* Cost of scalar load.  */

  const int scalar_store_cost;  /* Cost of scalar store.  */

  const int vec_stmt_cost;      /* Cost of any vector operation, excluding

                                   load, store, vector-to-scalar and

                                   scalar-to-vector operation.  */

  const int vec_to_scalar_cost;    /* Cost of vect-to-scalar operation.  */

  const int scalar_to_vec_cost;    /* Cost of scalar-to-vector operation.  */

  const int vec_align_load_cost;   /* Cost of aligned vector load.  */

  const int vec_unalign_load_cost; /* Cost of unaligned vector load.  */

  const int vec_store_cost;        /* Cost of vector store.  */

  const int cond_taken_branch_cost;    /* Cost of taken branch for vectorizer

					  cost model.  */

  const int cond_not_taken_branch_cost;/* Cost of not taken branch for

					  vectorizer cost model.  */

};

extern const struct processor_costs *ix86_cost;

extern const struct processor_costs ix86_size_cost;

#define ix86_cur_cost() \

  (optimize_insn_for_size_p () ? &ix86_size_cost: ix86_cost)

/* Macros used in the machine description to test the flags.  */

/* configure can arrange to make this 2, to force a 486.  */

#ifndef TARGET_CPU_DEFAULT

#define TARGET_CPU_DEFAULT TARGET_CPU_DEFAULT_generic

#endif

#ifndef TARGET_FPMATH_DEFAULT

#define TARGET_FPMATH_DEFAULT \

  (TARGET_64BIT && TARGET_SSE ? FPMATH_SSE : FPMATH_387)

#endif

#define TARGET_FLOAT_RETURNS_IN_80387 TARGET_FLOAT_RETURNS

/* 64bit Sledgehammer mode.  For libgcc2 we make sure this is a

   compile-time constant.  */

#ifdef IN_LIBGCC2

#undef TARGET_64BIT

#ifdef __x86_64__

#define TARGET_64BIT 1

#else

#define TARGET_64BIT 0

#endif

#else

#ifndef TARGET_BI_ARCH

#undef TARGET_64BIT

#if TARGET_64BIT_DEFAULT

#define TARGET_64BIT 1

#else

#define TARGET_64BIT 0

#endif

#endif

#endif

#define HAS_LONG_COND_BRANCH 1

#define HAS_LONG_UNCOND_BRANCH 1

#define TARGET_386 (ix86_tune == PROCESSOR_I386)

#define TARGET_486 (ix86_tune == PROCESSOR_I486)

#define TARGET_PENTIUM (ix86_tune == PROCESSOR_PENTIUM)

#define TARGET_PENTIUMPRO (ix86_tune == PROCESSOR_PENTIUMPRO)

#define TARGET_GEODE (ix86_tune == PROCESSOR_GEODE)

#define TARGET_K6 (ix86_tune == PROCESSOR_K6)

#define TARGET_ATHLON (ix86_tune == PROCESSOR_ATHLON)

#define TARGET_PENTIUM4 (ix86_tune == PROCESSOR_PENTIUM4)

#define TARGET_K8 (ix86_tune == PROCESSOR_K8)

#define TARGET_ATHLON_K8 (TARGET_K8 || TARGET_ATHLON)

#define TARGET_NOCONA (ix86_tune == PROCESSOR_NOCONA)

#define TARGET_CORE2 (ix86_tune == PROCESSOR_CORE2)

#define TARGET_GENERIC32 (ix86_tune == PROCESSOR_GENERIC32)

#define TARGET_GENERIC64 (ix86_tune == PROCESSOR_GENERIC64)

#define TARGET_GENERIC (TARGET_GENERIC32 || TARGET_GENERIC64)

#define TARGET_AMDFAM10 (ix86_tune == PROCESSOR_AMDFAM10)

#define TARGET_ATOM (ix86_tune == PROCESSOR_ATOM)

/* Feature tests against the various tunings.  */

enum ix86_tune_indices {

  X86_TUNE_USE_LEAVE,

  X86_TUNE_PUSH_MEMORY,

  X86_TUNE_ZERO_EXTEND_WITH_AND,

  X86_TUNE_UNROLL_STRLEN,

  X86_TUNE_DEEP_BRANCH_PREDICTION,

  X86_TUNE_BRANCH_PREDICTION_HINTS,

  X86_TUNE_DOUBLE_WITH_ADD,

  X86_TUNE_USE_SAHF,

  X86_TUNE_MOVX,

  X86_TUNE_PARTIAL_REG_STALL,

  X86_TUNE_PARTIAL_FLAG_REG_STALL,

  X86_TUNE_USE_HIMODE_FIOP,

  X86_TUNE_USE_SIMODE_FIOP,

  X86_TUNE_USE_MOV0,

  X86_TUNE_USE_CLTD,

  X86_TUNE_USE_XCHGB,

  X86_TUNE_SPLIT_LONG_MOVES,

  X86_TUNE_READ_MODIFY_WRITE,

  X86_TUNE_READ_MODIFY,

  X86_TUNE_PROMOTE_QIMODE,

  X86_TUNE_FAST_PREFIX,

  X86_TUNE_SINGLE_STRINGOP,

  X86_TUNE_QIMODE_MATH,

  X86_TUNE_HIMODE_MATH,

  X86_TUNE_PROMOTE_QI_REGS,

  X86_TUNE_PROMOTE_HI_REGS,

  X86_TUNE_ADD_ESP_4,

  X86_TUNE_ADD_ESP_8,

  X86_TUNE_SUB_ESP_4,

  X86_TUNE_SUB_ESP_8,

  X86_TUNE_INTEGER_DFMODE_MOVES,

  X86_TUNE_PARTIAL_REG_DEPENDENCY,

  X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY,

  X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL,

  X86_TUNE_SSE_SPLIT_REGS,

  X86_TUNE_SSE_TYPELESS_STORES,

  X86_TUNE_SSE_LOAD0_BY_PXOR,

  X86_TUNE_MEMORY_MISMATCH_STALL,

  X86_TUNE_PROLOGUE_USING_MOVE,

  X86_TUNE_EPILOGUE_USING_MOVE,

  X86_TUNE_SHIFT1,

  X86_TUNE_USE_FFREEP,

  X86_TUNE_INTER_UNIT_MOVES,

  X86_TUNE_INTER_UNIT_CONVERSIONS,

  X86_TUNE_FOUR_JUMP_LIMIT,

  X86_TUNE_SCHEDULE,

  X86_TUNE_USE_BT,

  X86_TUNE_USE_INCDEC,

  X86_TUNE_PAD_RETURNS,

  X86_TUNE_EXT_80387_CONSTANTS,

  X86_TUNE_SHORTEN_X87_SSE,

  X86_TUNE_AVOID_VECTOR_DECODE,

  X86_TUNE_PROMOTE_HIMODE_IMUL,

  X86_TUNE_SLOW_IMUL_IMM32_MEM,

  X86_TUNE_SLOW_IMUL_IMM8,

  X86_TUNE_MOVE_M1_VIA_OR,

  X86_TUNE_NOT_UNPAIRABLE,

  X86_TUNE_NOT_VECTORMODE,

  X86_TUNE_USE_VECTOR_FP_CONVERTS,

  X86_TUNE_USE_VECTOR_CONVERTS,

  X86_TUNE_FUSE_CMP_AND_BRANCH,

  X86_TUNE_OPT_AGU,

  X86_TUNE_LAST

};

extern unsigned char ix86_tune_features[X86_TUNE_LAST];

#define TARGET_USE_LEAVE	ix86_tune_features[X86_TUNE_USE_LEAVE]

#define TARGET_PUSH_MEMORY	ix86_tune_features[X86_TUNE_PUSH_MEMORY]

#define TARGET_ZERO_EXTEND_WITH_AND \

	ix86_tune_features[X86_TUNE_ZERO_EXTEND_WITH_AND]

#define TARGET_UNROLL_STRLEN	ix86_tune_features[X86_TUNE_UNROLL_STRLEN]

#define TARGET_DEEP_BRANCH_PREDICTION \

	ix86_tune_features[X86_TUNE_DEEP_BRANCH_PREDICTION]

#define TARGET_BRANCH_PREDICTION_HINTS \

	ix86_tune_features[X86_TUNE_BRANCH_PREDICTION_HINTS]

#define TARGET_DOUBLE_WITH_ADD	ix86_tune_features[X86_TUNE_DOUBLE_WITH_ADD]

#define TARGET_USE_SAHF		ix86_tune_features[X86_TUNE_USE_SAHF]

#define TARGET_MOVX		ix86_tune_features[X86_TUNE_MOVX]

#define TARGET_PARTIAL_REG_STALL ix86_tune_features[X86_TUNE_PARTIAL_REG_STALL]

#define TARGET_PARTIAL_FLAG_REG_STALL \

	ix86_tune_features[X86_TUNE_PARTIAL_FLAG_REG_STALL]

#define TARGET_USE_HIMODE_FIOP	ix86_tune_features[X86_TUNE_USE_HIMODE_FIOP]

#define TARGET_USE_SIMODE_FIOP	ix86_tune_features[X86_TUNE_USE_SIMODE_FIOP]

#define TARGET_USE_MOV0		ix86_tune_features[X86_TUNE_USE_MOV0]

#define TARGET_USE_CLTD		ix86_tune_features[X86_TUNE_USE_CLTD]

#define TARGET_USE_XCHGB	ix86_tune_features[X86_TUNE_USE_XCHGB]

#define TARGET_SPLIT_LONG_MOVES	ix86_tune_features[X86_TUNE_SPLIT_LONG_MOVES]

#define TARGET_READ_MODIFY_WRITE ix86_tune_features[X86_TUNE_READ_MODIFY_WRITE]

#define TARGET_READ_MODIFY	ix86_tune_features[X86_TUNE_READ_MODIFY]

#define TARGET_PROMOTE_QImode	ix86_tune_features[X86_TUNE_PROMOTE_QIMODE]

#define TARGET_FAST_PREFIX	ix86_tune_features[X86_TUNE_FAST_PREFIX]

#define TARGET_SINGLE_STRINGOP	ix86_tune_features[X86_TUNE_SINGLE_STRINGOP]

#define TARGET_QIMODE_MATH	ix86_tune_features[X86_TUNE_QIMODE_MATH]

#define TARGET_HIMODE_MATH	ix86_tune_features[X86_TUNE_HIMODE_MATH]

#define TARGET_PROMOTE_QI_REGS	ix86_tune_features[X86_TUNE_PROMOTE_QI_REGS]

#define TARGET_PROMOTE_HI_REGS	ix86_tune_features[X86_TUNE_PROMOTE_HI_REGS]

#define TARGET_ADD_ESP_4	ix86_tune_features[X86_TUNE_ADD_ESP_4]

#define TARGET_ADD_ESP_8	ix86_tune_features[X86_TUNE_ADD_ESP_8]

#define TARGET_SUB_ESP_4	ix86_tune_features[X86_TUNE_SUB_ESP_4]

#define TARGET_SUB_ESP_8	ix86_tune_features[X86_TUNE_SUB_ESP_8]

#define TARGET_INTEGER_DFMODE_MOVES \

	ix86_tune_features[X86_TUNE_INTEGER_DFMODE_MOVES]

#define TARGET_PARTIAL_REG_DEPENDENCY \

	ix86_tune_features[X86_TUNE_PARTIAL_REG_DEPENDENCY]

#define TARGET_SSE_PARTIAL_REG_DEPENDENCY \

	ix86_tune_features[X86_TUNE_SSE_PARTIAL_REG_DEPENDENCY]

#define TARGET_SSE_UNALIGNED_MOVE_OPTIMAL \

	ix86_tune_features[X86_TUNE_SSE_UNALIGNED_MOVE_OPTIMAL]

#define TARGET_SSE_SPLIT_REGS	ix86_tune_features[X86_TUNE_SSE_SPLIT_REGS]

#define TARGET_SSE_TYPELESS_STORES \

	ix86_tune_features[X86_TUNE_SSE_TYPELESS_STORES]

#define TARGET_SSE_LOAD0_BY_PXOR ix86_tune_features[X86_TUNE_SSE_LOAD0_BY_PXOR]

#define TARGET_MEMORY_MISMATCH_STALL \

	ix86_tune_features[X86_TUNE_MEMORY_MISMATCH_STALL]

#define TARGET_PROLOGUE_USING_MOVE \

	ix86_tune_features[X86_TUNE_PROLOGUE_USING_MOVE]

#define TARGET_EPILOGUE_USING_MOVE \

	ix86_tune_features[X86_TUNE_EPILOGUE_USING_MOVE]

#define TARGET_SHIFT1		ix86_tune_features[X86_TUNE_SHIFT1]

#define TARGET_USE_FFREEP	ix86_tune_features[X86_TUNE_USE_FFREEP]

#define TARGET_INTER_UNIT_MOVES	ix86_tune_features[X86_TUNE_INTER_UNIT_MOVES]

#define TARGET_INTER_UNIT_CONVERSIONS\

	ix86_tune_features[X86_TUNE_INTER_UNIT_CONVERSIONS]

#define TARGET_FOUR_JUMP_LIMIT	ix86_tune_features[X86_TUNE_FOUR_JUMP_LIMIT]

#define TARGET_SCHEDULE		ix86_tune_features[X86_TUNE_SCHEDULE]

#define TARGET_USE_BT		ix86_tune_features[X86_TUNE_USE_BT]

#define TARGET_USE_INCDEC	ix86_tune_features[X86_TUNE_USE_INCDEC]

#define TARGET_PAD_RETURNS	ix86_tune_features[X86_TUNE_PAD_RETURNS]

#define TARGET_EXT_80387_CONSTANTS \

	ix86_tune_features[X86_TUNE_EXT_80387_CONSTANTS]

#define TARGET_SHORTEN_X87_SSE	ix86_tune_features[X86_TUNE_SHORTEN_X87_SSE]

#define TARGET_AVOID_VECTOR_DECODE \

	ix86_tune_features[X86_TUNE_AVOID_VECTOR_DECODE]

#define TARGET_TUNE_PROMOTE_HIMODE_IMUL \

	ix86_tune_features[X86_TUNE_PROMOTE_HIMODE_IMUL]

#define TARGET_SLOW_IMUL_IMM32_MEM \

	ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM32_MEM]

#define TARGET_SLOW_IMUL_IMM8	ix86_tune_features[X86_TUNE_SLOW_IMUL_IMM8]

#define	TARGET_MOVE_M1_VIA_OR	ix86_tune_features[X86_TUNE_MOVE_M1_VIA_OR]

#define TARGET_NOT_UNPAIRABLE	ix86_tune_features[X86_TUNE_NOT_UNPAIRABLE]

#define TARGET_NOT_VECTORMODE	ix86_tune_features[X86_TUNE_NOT_VECTORMODE]

#define TARGET_USE_VECTOR_FP_CONVERTS \

	ix86_tune_features[X86_TUNE_USE_VECTOR_FP_CONVERTS]

#define TARGET_USE_VECTOR_CONVERTS \

	ix86_tune_features[X86_TUNE_USE_VECTOR_CONVERTS]

#define TARGET_FUSE_CMP_AND_BRANCH \

	ix86_tune_features[X86_TUNE_FUSE_CMP_AND_BRANCH]

#define TARGET_OPT_AGU ix86_tune_features[X86_TUNE_OPT_AGU]

/* Feature tests against the various architecture variations.  */

enum ix86_arch_indices {

  X86_ARCH_CMOVE,		/* || TARGET_SSE */

  X86_ARCH_CMPXCHG,

  X86_ARCH_CMPXCHG8B,

  X86_ARCH_XADD,

  X86_ARCH_BSWAP,

  X86_ARCH_LAST

};

extern unsigned char ix86_arch_features[X86_ARCH_LAST];

#define TARGET_CMOVE		ix86_arch_features[X86_ARCH_CMOVE]

#define TARGET_CMPXCHG		ix86_arch_features[X86_ARCH_CMPXCHG]

#define TARGET_CMPXCHG8B	ix86_arch_features[X86_ARCH_CMPXCHG8B]

#define TARGET_XADD		ix86_arch_features[X86_ARCH_XADD]

#define TARGET_BSWAP		ix86_arch_features[X86_ARCH_BSWAP]

#define TARGET_FISTTP		(TARGET_SSE3 && TARGET_80387)

extern int x86_prefetch_sse;

#define TARGET_PREFETCH_SSE	x86_prefetch_sse

#define ASSEMBLER_DIALECT	(ix86_asm_dialect)

#define TARGET_SSE_MATH		((ix86_fpmath & FPMATH_SSE) != 0)

#define TARGET_MIX_SSE_I387 \

 ((ix86_fpmath & (FPMATH_SSE | FPMATH_387)) == (FPMATH_SSE | FPMATH_387))

#define TARGET_GNU_TLS		(ix86_tls_dialect == TLS_DIALECT_GNU)

#define TARGET_GNU2_TLS		(ix86_tls_dialect == TLS_DIALECT_GNU2)

#define TARGET_ANY_GNU_TLS	(TARGET_GNU_TLS || TARGET_GNU2_TLS)

#define TARGET_SUN_TLS		0

extern int ix86_isa_flags;

#ifndef TARGET_64BIT_DEFAULT

#define TARGET_64BIT_DEFAULT 0

#endif

#ifndef TARGET_TLS_DIRECT_SEG_REFS_DEFAULT

#define TARGET_TLS_DIRECT_SEG_REFS_DEFAULT 0

#endif

/* Fence to use after loop using storent.  */

extern tree x86_mfence;

#define FENCE_FOLLOWING_MOVNT x86_mfence

/* Once GDB has been enhanced to deal with functions without frame

   pointers, we can change this to allow for elimination of

   the frame pointer in leaf functions.  */

#define TARGET_DEFAULT 0

/* Extra bits to force.  */

#define TARGET_SUBTARGET_DEFAULT 0

#define TARGET_SUBTARGET_ISA_DEFAULT 0

/* Extra bits to force on w/ 32-bit mode.  */

#define TARGET_SUBTARGET32_DEFAULT 0

#define TARGET_SUBTARGET32_ISA_DEFAULT 0

/* Extra bits to force on w/ 64-bit mode.  */

#define TARGET_SUBTARGET64_DEFAULT 0

#define TARGET_SUBTARGET64_ISA_DEFAULT 0

/* This is not really a target flag, but is done this way so that

   it's analogous to similar code for Mach-O on PowerPC.  darwin.h

   redefines this to 1.  */

#define TARGET_MACHO 0

/* Likewise, for the Windows 64-bit ABI.  */

#define TARGET_64BIT_MS_ABI (TARGET_64BIT && ix86_cfun_abi () == MS_ABI)

/* Available call abi.  */

enum calling_abi

{

  SYSV_ABI = 0,

  MS_ABI = 1

};

/* The abi used by target.  */

extern enum calling_abi ix86_abi;

/* The default abi used by target.  */

#define DEFAULT_ABI SYSV_ABI

/* Subtargets may reset this to 1 in order to enable 96-bit long double

   with the rounding mode forced to 53 bits.  */

#define TARGET_96_ROUND_53_LONG_DOUBLE 0

/* Sometimes certain combinations of command options do not make

   sense on a particular target machine.  You can define a macro

   `OVERRIDE_OPTIONS' to take account of this.  This macro, if

   defined, is executed once just after all the command options have

   been parsed.

   Don't use this macro to turn on various extra optimizations for

   `-O'.  That is what `OPTIMIZATION_OPTIONS' is for.  */

#define OVERRIDE_OPTIONS override_options (true)

/* Define this to change the optimizations performed by default.  */

#define OPTIMIZATION_OPTIONS(LEVEL, SIZE) \

  optimization_options ((LEVEL), (SIZE))

/* -march=native handling only makes sense with compiler running on

   an x86 or x86_64 chip.  If changing this condition, also change

   the condition in driver-i386.c.  */

#if defined(__i386__) || defined(__x86_64__)

/* In driver-i386.c.  */

extern const char *host_detect_local_cpu (int argc, const char **argv);

#define EXTRA_SPEC_FUNCTIONS \

  { "local_cpu_detect", host_detect_local_cpu },

#define HAVE_LOCAL_CPU_DETECT

#endif

#if TARGET_64BIT_DEFAULT

#define OPT_ARCH64 "!m32"

#define OPT_ARCH32 "m32"

#else

#define OPT_ARCH64 "m64"

#define OPT_ARCH32 "!m64"

#endif

/* Support for configure-time defaults of some command line options.

   The order here is important so that -march doesn't squash the

   tune or cpu values.  */

#define OPTION_DEFAULT_SPECS					   \

  {"tune", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" }, \

  {"tune_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \

  {"tune_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \

  {"cpu", "%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}" },  \

  {"cpu_32", "%{" OPT_ARCH32 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \

  {"cpu_64", "%{" OPT_ARCH64 ":%{!mtune=*:%{!mcpu=*:%{!march=*:-mtune=%(VALUE)}}}}" }, \

  {"arch", "%{!march=*:-march=%(VALUE)}"},			   \

  {"arch_32", "%{" OPT_ARCH32 ":%{!march=*:-march=%(VALUE)}}"},	   \

  {"arch_64", "%{" OPT_ARCH64 ":%{!march=*:-march=%(VALUE)}}"},

/* Specs for the compiler proper */

#ifndef CC1_CPU_SPEC

#define CC1_CPU_SPEC_1 "\

%{mcpu=*:-mtune=%* \

%n`-mcpu=' is deprecated. Use `-mtune=' or '-march=' instead.\n} \

%

%{mintel-syntax:-masm=intel \

%n`-mintel-syntax' is deprecated. Use `-masm=intel' instead.\n} \

%{msse5:-mavx \

%n'-msse5' was removed.\n} \

%{mno-intel-syntax:-masm=att \

%n`-mno-intel-syntax' is deprecated. Use `-masm=att' instead.\n}"

#ifndef HAVE_LOCAL_CPU_DETECT

#define CC1_CPU_SPEC CC1_CPU_SPEC_1

#else

#define CC1_CPU_SPEC CC1_CPU_SPEC_1 \

"%{march=native:%

  %{!mtune=*:%

%{mtune=native:%

#endif

#endif

/* Target CPU builtins.  */

#define TARGET_CPU_CPP_BUILTINS() ix86_target_macros ()

/* Target Pragmas.  */

#define REGISTER_TARGET_PRAGMAS() ix86_register_pragmas ()

enum target_cpu_default

{

  TARGET_CPU_DEFAULT_generic = 0,

  TARGET_CPU_DEFAULT_i386,

  TARGET_CPU_DEFAULT_i486,

  TARGET_CPU_DEFAULT_pentium,

  TARGET_CPU_DEFAULT_pentium_mmx,

  TARGET_CPU_DEFAULT_pentiumpro,

  TARGET_CPU_DEFAULT_pentium2,

  TARGET_CPU_DEFAULT_pentium3,

  TARGET_CPU_DEFAULT_pentium4,

  TARGET_CPU_DEFAULT_pentium_m,

  TARGET_CPU_DEFAULT_prescott,

  TARGET_CPU_DEFAULT_nocona,

  TARGET_CPU_DEFAULT_core2,

  TARGET_CPU_DEFAULT_atom,

  TARGET_CPU_DEFAULT_geode,

  TARGET_CPU_DEFAULT_k6,

  TARGET_CPU_DEFAULT_k6_2,

  TARGET_CPU_DEFAULT_k6_3,

  TARGET_CPU_DEFAULT_athlon,

  TARGET_CPU_DEFAULT_athlon_sse,

  TARGET_CPU_DEFAULT_k8,

  TARGET_CPU_DEFAULT_amdfam10,

  TARGET_CPU_DEFAULT_max

};

#ifndef CC1_SPEC

#define CC1_SPEC "%(cc1_cpu) "

#endif

/* This macro defines names of additional specifications to put in the

   specs that can be used in various specifications like CC1_SPEC.  Its

   definition is an initializer with a subgrouping for each command option.

   Each subgrouping contains a string constant, that defines the

   specification name, and a string constant that used by the GCC driver

   program.

   Do not define this macro if it does not need to do anything.  */

#ifndef SUBTARGET_EXTRA_SPECS

#define SUBTARGET_EXTRA_SPECS

#endif

#define EXTRA_SPECS							\

  { "cc1_cpu",  CC1_CPU_SPEC },						\

  SUBTARGET_EXTRA_SPECS

/* Set the value of FLT_EVAL_METHOD in float.h.  When using only the

   FPU, assume that the fpcw is set to extended precision; when using

   only SSE, rounding is correct; when using both SSE and the FPU,

   the rounding precision is indeterminate, since either may be chosen

   apparently at random.  */

#define TARGET_FLT_EVAL_METHOD \

  (TARGET_MIX_SSE_I387 ? -1 : TARGET_SSE_MATH ? 0 : 2)

/* Whether to allow x87 floating-point arithmetic on MODE (one of

   SFmode, DFmode and XFmode) in the current excess precision

   configuration.  */

#define X87_ENABLE_ARITH(MODE) \

  (flag_excess_precision == EXCESS_PRECISION_FAST || (MODE) == XFmode)

/* Likewise, whether to allow direct conversions from integer mode

   IMODE (HImode, SImode or DImode) to MODE.  */

#define X87_ENABLE_FLOAT(MODE, IMODE)			\

  (flag_excess_precision == EXCESS_PRECISION_FAST	\

   || (MODE) == XFmode					\

   || ((MODE) == DFmode && (IMODE) == SImode)		\

   || (IMODE) == HImode)

/* target machine storage layout */

#define SHORT_TYPE_SIZE 16

#define INT_TYPE_SIZE 32

#define FLOAT_TYPE_SIZE 32

#define LONG_TYPE_SIZE BITS_PER_WORD

#define DOUBLE_TYPE_SIZE 64

#define LONG_LONG_TYPE_SIZE 64

#define LONG_DOUBLE_TYPE_SIZE 80

#define WIDEST_HARDWARE_FP_SIZE LONG_DOUBLE_TYPE_SIZE

#if defined (TARGET_BI_ARCH) || TARGET_64BIT_DEFAULT

#define MAX_BITS_PER_WORD 64

#else

#define MAX_BITS_PER_WORD 32

#endif

/* Define this if most significant byte of a word is the lowest numbered.  */

/* That is true on the 80386.  */

#define BITS_BIG_ENDIAN 0

/* Define this if most significant byte of a word is the lowest numbered.  */

/* That is not true on the 80386.  */

#define BYTES_BIG_ENDIAN 0

/* Define this if most significant word of a multiword number is the lowest

   numbered.  */

/* Not true for 80386 */

#define WORDS_BIG_ENDIAN 0

/* Width of a word, in units (bytes).  */

#define UNITS_PER_WORD		(TARGET_64BIT ? 8 : 4)

#ifdef IN_LIBGCC2

#define MIN_UNITS_PER_WORD	(TARGET_64BIT ? 8 : 4)

#else

#define MIN_UNITS_PER_WORD	4

#endif

/* Allocation boundary (in *bits*) for storing arguments in argument list.  */

#define PARM_BOUNDARY BITS_PER_WORD

/* Boundary (in *bits*) on which stack pointer should be aligned.  */

#define STACK_BOUNDARY \

 (TARGET_64BIT && ix86_abi == MS_ABI ? 128 : BITS_PER_WORD)

/* Stack boundary of the main function guaranteed by OS.  */

#define MAIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)

/* Minimum stack boundary.  */

#define MIN_STACK_BOUNDARY (TARGET_64BIT ? 128 : 32)

/* Boundary (in *bits*) on which the stack pointer prefers to be

   aligned; the compiler cannot rely on having this alignment.  */

#define PREFERRED_STACK_BOUNDARY ix86_preferred_stack_boundary

/* It should be MIN_STACK_BOUNDARY.  But we set it to 128 bits for

   both 32bit and 64bit, to support codes that need 128 bit stack

   alignment for SSE instructions, but can't realign the stack.  */

#define PREFERRED_STACK_BOUNDARY_DEFAULT 128

/* 1 if -mstackrealign should be turned on by default.  It will

   generate an alternate prologue and epilogue that realigns the

   runtime stack if nessary.  This supports mixing codes that keep a

   4-byte aligned stack, as specified by i386 psABI, with codes that

   need a 16-byte aligned stack, as required by SSE instructions.  */

#define STACK_REALIGN_DEFAULT 0

/* Boundary (in *bits*) on which the incoming stack is aligned.  */

#define INCOMING_STACK_BOUNDARY ix86_incoming_stack_boundary

/* Target OS keeps a vector-aligned (128-bit, 16-byte) stack.  This is

   mandatory for the 64-bit ABI, and may or may not be true for other

   operating systems.  */

#define TARGET_KEEPS_VECTOR_ALIGNED_STACK TARGET_64BIT

/* Minimum allocation boundary for the code of a function.  */

#define FUNCTION_BOUNDARY 8

/* C++ stores the virtual bit in the lowest bit of function pointers.  */

#define TARGET_PTRMEMFUNC_VBIT_LOCATION ptrmemfunc_vbit_in_pfn

/* Alignment of field after `int : 0' in a structure.  */

#define EMPTY_FIELD_BOUNDARY BITS_PER_WORD

/* Minimum size in bits of the largest boundary to which any

   and all fundamental data types supported by the hardware

   might need to be aligned. No data type wants to be aligned

   rounder than this.

   Pentium+ prefers DFmode values to be aligned to 64 bit boundary

   and Pentium Pro XFmode values at 128 bit boundaries.  */

#define BIGGEST_ALIGNMENT (TARGET_AVX ? 256: 128)

/* Maximum stack alignment.  */

#define MAX_STACK_ALIGNMENT MAX_OFILE_ALIGNMENT

/* Alignment value for attribute ((aligned)).  It is a constant since

   it is the part of the ABI.  We shouldn't change it with -mavx.  */

#define ATTRIBUTE_ALIGNED_VALUE 128

/* Decide whether a variable of mode MODE should be 128 bit aligned.  */

#define ALIGN_MODE_128(MODE) \

 ((MODE) == XFmode || SSE_REG_MODE_P (MODE))

/* The published ABIs say that doubles should be aligned on word

   boundaries, so lower the alignment for structure fields unless

   -malign-double is set.  */

/* ??? Blah -- this macro is used directly by libobjc.  Since it

   supports no vector modes, cut out the complexity and fall back

   on BIGGEST_FIELD_ALIGNMENT.  */

#ifdef IN_TARGET_LIBS

#ifdef __x86_64__

#define BIGGEST_FIELD_ALIGNMENT 128

#else

#define BIGGEST_FIELD_ALIGNMENT 32

#endif

#else

#define ADJUST_FIELD_ALIGN(FIELD, COMPUTED) \

   x86_field_alignment (FIELD, COMPUTED)

#endif

/* If defined, a C expression to compute the alignment given to a

   constant that is being placed in memory.  EXP is the constant

   and ALIGN is the alignment that the object would ordinarily have.

   The value of this macro is used instead of that alignment to align

   the object.

   If this macro is not defined, then ALIGN is used.

   The typical use of this macro is to increase alignment for string

   constants to be word aligned so that `strcpy' calls that copy

   constants can be done inline.  */

#define CONSTANT_ALIGNMENT(EXP, ALIGN) ix86_constant_alignment ((EXP), (ALIGN))

/* If defined, a C expression to compute the alignment for a static

   variable.  TYPE is the data type, and ALIGN is the alignment that

   the object would ordinarily have.  The value of this macro is used

   instead of that alignment to align the object.

   If this macro is not defined, then ALIGN is used.

   One use of this macro is to increase alignment of medium-size

   data to make it all fit in fewer cache lines.  Another is to

   cause character arrays to be word-aligned so that `strcpy' calls

   that copy constants to character arrays can be done inline.  */

#define DATA_ALIGNMENT(TYPE, ALIGN) ix86_data_alignment ((TYPE), (ALIGN))

/* If defined, a C expression to compute the alignment for a local

   variable.  TYPE is the data type, and ALIGN is the alignment that

   the object would ordinarily have.  The value of this macro is used

   instead of that alignment to align the object.

   If this macro is not defined, then ALIGN is used.

   One use of this macro is to increase alignment of medium-size

   data to make it all fit in fewer cache lines.  */

#define LOCAL_ALIGNMENT(TYPE, ALIGN) \

  ix86_local_alignment ((TYPE), VOIDmode, (ALIGN))

/* If defined, a C expression to compute the alignment for stack slot.

   TYPE is the data type, MODE is the widest mode available, and ALIGN

   is the alignment that the slot would ordinarily have.  The value of

   this macro is used instead of that alignment to align the slot.

   If this macro is not defined, then ALIGN is used when TYPE is NULL,

   Otherwise, LOCAL_ALIGNMENT will be used.

   One use of this macro is to set alignment of stack slot to the

   maximum alignment of all possible modes which the slot may have.  */

#define STACK_SLOT_ALIGNMENT(TYPE, MODE, ALIGN) \

  ix86_local_alignment ((TYPE), (MODE), (ALIGN))

/* If defined, a C expression to compute the alignment for a local

   variable DECL.

   If this macro is not defined, then

   LOCAL_ALIGNMENT (TREE_TYPE (DECL), DECL_ALIGN (DECL)) will be used.

   One use of this macro is to increase alignment of medium-size

   data to make it all fit in fewer cache lines.  */

#define LOCAL_DECL_ALIGNMENT(DECL) \

  ix86_local_alignment ((DECL), VOIDmode, DECL_ALIGN (DECL))

/* If defined, a C expression to compute the minimum required alignment

   for dynamic stack realignment purposes for EXP (a TYPE or DECL),

   MODE, assuming normal alignment ALIGN.

   If this macro is not defined, then (ALIGN) will be used.  */

#define MINIMUM_ALIGNMENT(EXP, MODE, ALIGN) \

  ix86_minimum_alignment (EXP, MODE, ALIGN)

/* If defined, a C expression that gives the alignment boundary, in

   bits, of an argument with the specified mode and type.  If it is

   not defined, `PARM_BOUNDARY' is used for all arguments.  */

#define FUNCTION_ARG_BOUNDARY(MODE, TYPE) \

  ix86_function_arg_boundary ((MODE), (TYPE))

/* Set this nonzero if move instructions will actually fail to work

   when given unaligned data.  */

#define STRICT_ALIGNMENT 0

/* If bit field type is int, don't let it cross an int,

   and give entire struct the alignment of an int.  */

/* Required on the 386 since it doesn't have bit-field insns.  */

#define PCC_BITFIELD_TYPE_MATTERS 1

/* Standard register usage.  */

/* This processor has special stack-like registers.  See reg-stack.c

   for details.  */

#define STACK_REGS

#define IS_STACK_MODE(MODE)					\

  (((MODE) == SFmode && (!TARGET_SSE || !TARGET_SSE_MATH))	\

   || ((MODE) == DFmode && (!TARGET_SSE2 || !TARGET_SSE_MATH))  \

   || (MODE) == XFmode)

/* Cover class containing the stack registers.  */

#define STACK_REG_COVER_CLASS FLOAT_REGS

/* Number of actual hardware registers.

   The hardware registers are assigned numbers for the compiler

   from 0 to just below FIRST_PSEUDO_REGISTER.

   All registers that the compiler knows about must be given numbers,

   even those that are not normally considered general registers.

   In the 80386 we give the 8 general purpose registers the numbers 0-7.

   We number the floating point registers 8-15.

   Note that registers 0-7 can be accessed as a  short or int,

   while only 0-3 may be used with byte `mov' instructions.

   Reg 16 does not correspond to any hardware register, but instead

   appears in the RTL as an argument pointer prior to reload, and is

   eliminated during reloading in favor of either the stack or frame

   pointer.  */

#define FIRST_PSEUDO_REGISTER 53

/* Number of hardware registers that go into the DWARF-2 unwind info.

   If not defined, equals FIRST_PSEUDO_REGISTER.  */

#define DWARF_FRAME_REGISTERS 17

/* 1 for registers that have pervasive standard uses

   and are not available for the register allocator.

   On the 80386, the stack pointer is such, as is the arg pointer.

   The value is zero if the register is not fixed on either 32 or

   64 bit targets, one if the register if fixed on both 32 and 64

   bit targets, two if it is only fixed on 32bit targets and three

   if its only fixed on 64bit targets.

   Proper values are computed in the CONDITIONAL_REGISTER_USAGE.

 */

#define FIXED_REGISTERS						\

/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/	\

{  0, 0, 0, 0, 0, 0, 0, 1, 0,  0,  0,  0,  0,  0,  0,  0,	\

/*arg,flags,fpsr,fpcr,frame*/					\

    1,    1,   1,   1,    1,					\

/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/			\

     0,   0,   0,   0,   0,   0,   0,   0,			\

/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/			\

     0,   0,   0,   0,   0,   0,   0,   0,			\

/*  r8,  r9, r10, r11, r12, r13, r14, r15*/			\

     2,   2,   2,   2,   2,   2,   2,   2,			\

/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/		\

     2,   2,    2,    2,    2,    2,    2,    2 }

/* 1 for registers not available across function calls.

   These must include the FIXED_REGISTERS and also any

   registers that can be used without being saved.

   The latter must include the registers where values are returned

   and the register where structure-value addresses are passed.

   Aside from that, you can include as many other registers as you like.

   The value is zero if the register is not call used on either 32 or

   64 bit targets, one if the register if call used on both 32 and 64

   bit targets, two if it is only call used on 32bit targets and three

   if its only call used on 64bit targets.

   Proper values are computed in the CONDITIONAL_REGISTER_USAGE.

*/

#define CALL_USED_REGISTERS					\

/*ax,dx,cx,bx,si,di,bp,sp,st,st1,st2,st3,st4,st5,st6,st7*/	\

{  1, 1, 1, 0, 3, 3, 0, 1, 1,  1,  1,  1,  1,  1,  1,  1,	\

/*arg,flags,fpsr,fpcr,frame*/					\

    1,   1,    1,   1,    1,					\

/*xmm0,xmm1,xmm2,xmm3,xmm4,xmm5,xmm6,xmm7*/			\

     1,   1,   1,   1,   1,   1,   1,   1,			\

/* mm0, mm1, mm2, mm3, mm4, mm5, mm6, mm7*/			\

     1,   1,   1,   1,   1,   1,   1,   1,			\

/*  r8,  r9, r10, r11, r12, r13, r14, r15*/			\

     1,   1,   1,   1,   2,   2,   2,   2,			\

/*xmm8,xmm9,xmm10,xmm11,xmm12,xmm13,xmm14,xmm15*/		\

     1,   1,    1,    1,    1,    1,    1,    1 }

/* Order in which to allocate registers.  Each register must be

   listed once, even those in FIXED_REGISTERS.  List frame pointer

   late and fixed registers last.  Note that, in general, we prefer

   registers listed in CALL_USED_REGISTERS, keeping the others

   available for storage of persistent values.

   The ORDER_REGS_FOR_LOCAL_ALLOC actually overwrite the order,

   so this is just empty initializer for array.  */

#define REG_ALLOC_ORDER 					\

{  0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17,\

   18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32,	\

   33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,  \

   48, 49, 50, 51, 52 }

/* ORDER_REGS_FOR_LOCAL_ALLOC is a macro which permits reg_alloc_order

   to be rearranged based on a particular function.  When using sse math,

   we want to allocate SSE before x87 registers and vice versa.  */

#define ORDER_REGS_FOR_LOCAL_ALLOC x86_order_regs_for_local_alloc ()

#define OVERRIDE_ABI_FORMAT(FNDECL) ix86_call_abi_override (FNDECL)

/* Macro to conditionally modify fixed_regs/call_used_regs.  */

#define CONDITIONAL_REGISTER_USAGE  ix86_conditional_register_usage ()

/* Return number of consecutive hard regs needed starting at reg REGNO

   to hold something of mode MODE.

   This is ordinarily the length in words of a value of mode MODE

   but can be less for certain modes in special long registers.

   Actually there are no two word move instructions for consecutive

   registers.  And only registers 0-3 may have mov byte instructions

   applied to them.

   */

#define HARD_REGNO_NREGS(REGNO, MODE)					\

  (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO)	\

   ? (COMPLEX_MODE_P (MODE) ? 2 : 1)					\

   : ((MODE) == XFmode							\

      ? (TARGET_64BIT ? 2 : 3)						\

      : (MODE) == XCmode						\

      ? (TARGET_64BIT ? 4 : 6)						\

      : ((GET_MODE_SIZE (MODE) + UNITS_PER_WORD - 1) / UNITS_PER_WORD)))

#define HARD_REGNO_NREGS_HAS_PADDING(REGNO, MODE)			\

  ((TARGET_128BIT_LONG_DOUBLE && !TARGET_64BIT)				\

   ? (FP_REGNO_P (REGNO) || SSE_REGNO_P (REGNO) || MMX_REGNO_P (REGNO)	\

      ? 0								\

      : ((MODE) == XFmode || (MODE) == XCmode))				\

   : 0)

#define HARD_REGNO_NREGS_WITH_PADDING(REGNO, MODE) ((MODE) == XFmode ? 4 : 8)

#define VALID_AVX256_REG_MODE(MODE)					\

  ((MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode	\

   || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode)

#define VALID_SSE2_REG_MODE(MODE)					\

  ((MODE) == V16QImode || (MODE) == V8HImode || (MODE) == V2DFmode	\

   || (MODE) == V2DImode || (MODE) == DFmode)

#define VALID_SSE_REG_MODE(MODE)					\

  ((MODE) == V1TImode || (MODE) == TImode				\

   || (MODE) == V4SFmode || (MODE) == V4SImode				\

   || (MODE) == SFmode || (MODE) == TFmode)

#define VALID_MMX_REG_MODE_3DNOW(MODE) \

  ((MODE) == V2SFmode || (MODE) == SFmode)

#define VALID_MMX_REG_MODE(MODE)					\

  ((MODE == V1DImode) || (MODE) == DImode				\

   || (MODE) == V2SImode || (MODE) == SImode				\

   || (MODE) == V4HImode || (MODE) == V8QImode)

/* ??? No autovectorization into MMX or 3DNOW until we can reliably

   place emms and femms instructions.

   FIXME: AVX has 32byte floating point vector operations and 16byte

   integer vector operations.  But vectorizer doesn't support

   different sizes for integer and floating point vectors.  We limit

   vector size to 16byte.  */

#define UNITS_PER_SIMD_WORD(MODE)					\

  (TARGET_AVX ? (((MODE) == DFmode || (MODE) == SFmode) ? 16 : 16)	\

   	      : (TARGET_SSE ? 16 : UNITS_PER_WORD))

#define VALID_DFP_MODE_P(MODE) \

  ((MODE) == SDmode || (MODE) == DDmode || (MODE) == TDmode)

#define VALID_FP_MODE_P(MODE)						\

  ((MODE) == SFmode || (MODE) == DFmode || (MODE) == XFmode		\

   || (MODE) == SCmode || (MODE) == DCmode || (MODE) == XCmode)		\

#define VALID_INT_MODE_P(MODE)						\

  ((MODE) == QImode || (MODE) == HImode || (MODE) == SImode		\

   || (MODE) == DImode							\

   || (MODE) == CQImode || (MODE) == CHImode || (MODE) == CSImode	\

   || (MODE) == CDImode							\

   || (TARGET_64BIT && ((MODE) == TImode || (MODE) == CTImode		\

			|| (MODE) == TFmode || (MODE) == TCmode)))

/* Return true for modes passed in SSE registers.  */

#define SSE_REG_MODE_P(MODE)						\

  ((MODE) == V1TImode || (MODE) == TImode || (MODE) == V16QImode	\

   || (MODE) == TFmode || (MODE) == V8HImode || (MODE) == V2DFmode	\

   || (MODE) == V2DImode || (MODE) == V4SFmode || (MODE) == V4SImode	\

   || (MODE) == V32QImode || (MODE) == V16HImode || (MODE) == V8SImode	\

   || (MODE) == V4DImode || (MODE) == V8SFmode || (MODE) == V4DFmode)

/* Value is 1 if hard register REGNO can hold a value of machine-mode MODE.  */

#define HARD_REGNO_MODE_OK(REGNO, MODE)	\

   ix86_hard_regno_mode_ok ((REGNO), (MODE))

/* Value is 1 if it is a good idea to tie two pseudo registers

   when one has mode MODE1 and one has mode MODE2.

   If HARD_REGNO_MODE_OK could produce different values for MODE1 and MODE2,

   for any hard reg, then this must be 0 for correct output.  */

#define MODES_TIEABLE_P(MODE1, MODE2)  ix86_modes_tieable_p (MODE1, MODE2)

/* It is possible to write patterns to move flags; but until someone

   does it,  */

#define AVOID_CCMODE_COPIES

/* Specify the modes required to caller save a given hard regno.

   We do this on i386 to prevent flags from being saved at all.

   Kill any attempts to combine saving of modes.  */

#define HARD_REGNO_CALLER_SAVE_MODE(REGNO, NREGS, MODE)			\

  (CC_REGNO_P (REGNO) ? VOIDmode					\

   : (MODE) == VOIDmode && (NREGS) != 1 ? VOIDmode			\

   : (MODE) == VOIDmode ? choose_hard_reg_mode ((REGNO), (NREGS), false) \

   : (MODE) == HImode && !TARGET_PARTIAL_REG_STALL ? SImode		\

   : (MODE) == QImode && (REGNO) > BX_REG && !TARGET_64BIT ? SImode 	\

   : (MODE))

/* Specify the registers used for certain standard purposes.

   The values of these macros are register numbers.  */

/* on the 386 the pc register is %eip, and is not usable as a general

   register.  The ordinary mov instructions won't work */

/* #define PC_REGNUM  */

/* Register to use for pushing function arguments.  */

#define STACK_POINTER_REGNUM 7

/* Base register for access to local variables of the function.  */

#define HARD_FRAME_POINTER_REGNUM 6

/* Base register for access to local variables of the function.  */

#define FRAME_POINTER_REGNUM 20

/* First floating point reg */

#define FIRST_FLOAT_REG 8

/* First & last stack-like regs */

#define FIRST_STACK_REG FIRST_FLOAT_REG

#define LAST_STACK_REG (FIRST_FLOAT_REG + 7)

#define FIRST_SSE_REG (FRAME_POINTER_REGNUM + 1)

#define LAST_SSE_REG  (FIRST_SSE_REG + 7)

#define FIRST_MMX_REG  (LAST_SSE_REG + 1)

#define LAST_MMX_REG   (FIRST_MMX_REG + 7)

#define FIRST_REX_INT_REG  (LAST_MMX_REG + 1)

#define LAST_REX_INT_REG   (FIRST_REX_INT_REG + 7)

#define FIRST_REX_SSE_REG  (LAST_REX_INT_REG + 1)

#define LAST_REX_SSE_REG   (FIRST_REX_SSE_REG + 7)

/* Override this in other tm.h files to cope with various OS lossage

   requiring a frame pointer.  */

#ifndef SUBTARGET_FRAME_POINTER_REQUIRED

#define SUBTARGET_FRAME_POINTER_REQUIRED 0

#endif