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| 4358 | Serge | 1 | /* |
| 2 | * Copyright © 2009 Intel Corporation |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice (including the next |
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| 12 | * paragraph) shall be included in all copies or substantial portions of the |
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| 13 | * Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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| 21 | * IN THE SOFTWARE. |
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| 22 | * |
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| 23 | * Authors: |
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| 24 | * Eric Anholt |
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| 25 | * |
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| 26 | */ |
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| 27 | |||
| 28 | #include "intel_batchbuffer.h" |
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| 29 | #include "intel_fbo.h" |
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| 30 | #include "brw_context.h" |
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| 31 | #include "brw_defines.h" |
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| 32 | #include "brw_state.h" |
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| 33 | |||
| 34 | static void |
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| 35 | gen6_upload_depth_stencil_state(struct brw_context *brw) |
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| 36 | { |
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| 37 | struct gl_context *ctx = &brw->ctx; |
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| 38 | struct gen6_depth_stencil_state *ds; |
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| 39 | struct intel_renderbuffer *depth_irb; |
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| 40 | |||
| 41 | /* _NEW_BUFFERS */ |
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| 42 | depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH); |
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| 43 | |||
| 44 | ds = brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE, |
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| 45 | sizeof(*ds), 64, |
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| 46 | &brw->cc.depth_stencil_state_offset); |
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| 47 | memset(ds, 0, sizeof(*ds)); |
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| 48 | |||
| 49 | /* _NEW_STENCIL | _NEW_BUFFERS */ |
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| 50 | if (ctx->Stencil._Enabled) { |
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| 51 | int back = ctx->Stencil._BackFace; |
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| 52 | |||
| 53 | ds->ds0.stencil_enable = 1; |
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| 54 | ds->ds0.stencil_func = |
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| 55 | intel_translate_compare_func(ctx->Stencil.Function[0]); |
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| 56 | ds->ds0.stencil_fail_op = |
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| 57 | intel_translate_stencil_op(ctx->Stencil.FailFunc[0]); |
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| 58 | ds->ds0.stencil_pass_depth_fail_op = |
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| 59 | intel_translate_stencil_op(ctx->Stencil.ZFailFunc[0]); |
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| 60 | ds->ds0.stencil_pass_depth_pass_op = |
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| 61 | intel_translate_stencil_op(ctx->Stencil.ZPassFunc[0]); |
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| 62 | ds->ds1.stencil_write_mask = ctx->Stencil.WriteMask[0]; |
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| 63 | ds->ds1.stencil_test_mask = ctx->Stencil.ValueMask[0]; |
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| 64 | |||
| 65 | if (ctx->Stencil._TestTwoSide) { |
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| 66 | ds->ds0.bf_stencil_enable = 1; |
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| 67 | ds->ds0.bf_stencil_func = |
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| 68 | intel_translate_compare_func(ctx->Stencil.Function[back]); |
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| 69 | ds->ds0.bf_stencil_fail_op = |
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| 70 | intel_translate_stencil_op(ctx->Stencil.FailFunc[back]); |
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| 71 | ds->ds0.bf_stencil_pass_depth_fail_op = |
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| 72 | intel_translate_stencil_op(ctx->Stencil.ZFailFunc[back]); |
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| 73 | ds->ds0.bf_stencil_pass_depth_pass_op = |
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| 74 | intel_translate_stencil_op(ctx->Stencil.ZPassFunc[back]); |
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| 75 | ds->ds1.bf_stencil_write_mask = ctx->Stencil.WriteMask[back]; |
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| 76 | ds->ds1.bf_stencil_test_mask = ctx->Stencil.ValueMask[back]; |
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| 77 | } |
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| 78 | |||
| 79 | ds->ds0.stencil_write_enable = ctx->Stencil._WriteEnabled; |
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| 80 | } |
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| 81 | |||
| 82 | /* _NEW_DEPTH */ |
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| 83 | if (ctx->Depth.Test && depth_irb) { |
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| 84 | ds->ds2.depth_test_enable = ctx->Depth.Test; |
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| 85 | ds->ds2.depth_test_func = intel_translate_compare_func(ctx->Depth.Func); |
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| 86 | ds->ds2.depth_write_enable = ctx->Depth.Mask; |
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| 87 | } |
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| 88 | |||
| 89 | /* Point the GPU at the new indirect state. */ |
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| 90 | if (brw->gen == 6) { |
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| 91 | BEGIN_BATCH(4); |
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| 92 | OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2)); |
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| 93 | OUT_BATCH(0); |
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| 94 | OUT_BATCH(brw->cc.depth_stencil_state_offset | 1); |
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| 95 | OUT_BATCH(0); |
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| 96 | ADVANCE_BATCH(); |
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| 97 | } else { |
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| 98 | BEGIN_BATCH(2); |
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| 99 | OUT_BATCH(_3DSTATE_DEPTH_STENCIL_STATE_POINTERS << 16 | (2 - 2)); |
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| 100 | OUT_BATCH(brw->cc.depth_stencil_state_offset | 1); |
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| 101 | ADVANCE_BATCH(); |
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| 102 | } |
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| 103 | } |
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| 104 | |||
| 105 | const struct brw_tracked_state gen6_depth_stencil_state = { |
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| 106 | .dirty = { |
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| 107 | .mesa = _NEW_DEPTH | _NEW_STENCIL | _NEW_BUFFERS, |
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| 108 | .brw = BRW_NEW_BATCH | BRW_NEW_STATE_BASE_ADDRESS, |
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| 109 | .cache = 0, |
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| 110 | }, |
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| 111 | .emit = gen6_upload_depth_stencil_state, |
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| 112 | }; |