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| 4358 | Serge | 1 | /* |
| 2 | Copyright (C) Intel Corp. 2006. All Rights Reserved. |
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| 3 | Intel funded Tungsten Graphics (http://www.tungstengraphics.com) to |
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| 4 | develop this 3D driver. |
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| 5 | |||
| 6 | Permission is hereby granted, free of charge, to any person obtaining |
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| 7 | a copy of this software and associated documentation files (the |
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| 8 | "Software"), to deal in the Software without restriction, including |
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| 9 | without limitation the rights to use, copy, modify, merge, publish, |
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| 10 | distribute, sublicense, and/or sell copies of the Software, and to |
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| 11 | permit persons to whom the Software is furnished to do so, subject to |
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| 12 | the following conditions: |
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| 13 | |||
| 14 | The above copyright notice and this permission notice (including the |
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| 15 | next paragraph) shall be included in all copies or substantial |
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| 16 | portions of the Software. |
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| 17 | |||
| 18 | THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
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| 19 | EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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| 20 | MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
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| 21 | IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE |
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| 22 | LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION |
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| 23 | OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION |
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| 24 | WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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| 25 | |||
| 26 | **********************************************************************/ |
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| 27 | /* |
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| 28 | * Authors: |
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| 29 | * Keith Whitwell |
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| 30 | */ |
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| 31 | |||
| 32 | |||
| 33 | |||
| 34 | #include "intel_fbo.h" |
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| 35 | #include "brw_context.h" |
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| 36 | #include "brw_state.h" |
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| 37 | #include "brw_defines.h" |
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| 38 | #include "brw_wm.h" |
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| 39 | |||
| 40 | /*********************************************************************** |
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| 41 | * WM unit - fragment programs and rasterization |
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| 42 | */ |
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| 43 | |||
| 44 | bool |
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| 45 | brw_color_buffer_write_enabled(struct brw_context *brw) |
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| 46 | { |
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| 47 | struct gl_context *ctx = &brw->ctx; |
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| 48 | const struct gl_fragment_program *fp = brw->fragment_program; |
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| 49 | int i; |
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| 50 | |||
| 51 | /* _NEW_BUFFERS */ |
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| 52 | for (i = 0; i < ctx->DrawBuffer->_NumColorDrawBuffers; i++) { |
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| 53 | struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[i]; |
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| 54 | |||
| 55 | /* _NEW_COLOR */ |
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| 56 | if (rb && |
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| 57 | (fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_COLOR) || |
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| 58 | fp->Base.OutputsWritten & BITFIELD64_BIT(FRAG_RESULT_DATA0 + i)) && |
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| 59 | (ctx->Color.ColorMask[i][0] || |
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| 60 | ctx->Color.ColorMask[i][1] || |
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| 61 | ctx->Color.ColorMask[i][2] || |
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| 62 | ctx->Color.ColorMask[i][3])) { |
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| 63 | return true; |
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| 64 | } |
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| 65 | } |
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| 66 | |||
| 67 | return false; |
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| 68 | } |
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| 69 | |||
| 70 | /** |
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| 71 | * Setup wm hardware state. See page 225 of Volume 2 |
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| 72 | */ |
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| 73 | static void |
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| 74 | brw_upload_wm_unit(struct brw_context *brw) |
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| 75 | { |
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| 76 | struct gl_context *ctx = &brw->ctx; |
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| 77 | const struct gl_fragment_program *fp = brw->fragment_program; |
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| 78 | struct brw_wm_unit_state *wm; |
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| 79 | |||
| 80 | wm = brw_state_batch(brw, AUB_TRACE_WM_STATE, |
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| 81 | sizeof(*wm), 32, &brw->wm.state_offset); |
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| 82 | memset(wm, 0, sizeof(*wm)); |
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| 83 | |||
| 84 | if (brw->wm.prog_data->prog_offset_16) { |
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| 85 | /* These two fields should be the same pre-gen6, which is why we |
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| 86 | * only have one hardware field to program for both dispatch |
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| 87 | * widths. |
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| 88 | */ |
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| 89 | assert(brw->wm.prog_data->first_curbe_grf == |
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| 90 | brw->wm.prog_data->first_curbe_grf_16); |
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| 91 | } |
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| 92 | |||
| 93 | /* BRW_NEW_PROGRAM_CACHE | CACHE_NEW_WM_PROG */ |
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| 94 | wm->thread0.grf_reg_count = brw->wm.prog_data->reg_blocks; |
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| 95 | wm->wm9.grf_reg_count_2 = brw->wm.prog_data->reg_blocks_16; |
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| 96 | |||
| 97 | wm->thread0.kernel_start_pointer = |
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| 98 | brw_program_reloc(brw, |
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| 99 | brw->wm.state_offset + |
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| 100 | offsetof(struct brw_wm_unit_state, thread0), |
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| 101 | brw->wm.prog_offset + |
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| 102 | (wm->thread0.grf_reg_count << 1)) >> 6; |
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| 103 | |||
| 104 | wm->wm9.kernel_start_pointer_2 = |
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| 105 | brw_program_reloc(brw, |
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| 106 | brw->wm.state_offset + |
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| 107 | offsetof(struct brw_wm_unit_state, wm9), |
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| 108 | brw->wm.prog_offset + |
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| 109 | brw->wm.prog_data->prog_offset_16 + |
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| 110 | (wm->wm9.grf_reg_count_2 << 1)) >> 6; |
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| 111 | |||
| 112 | wm->thread1.depth_coef_urb_read_offset = 1; |
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| 113 | /* Use ALT floating point mode for ARB fragment programs, because they |
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| 114 | * require 0^0 == 1. Even though _CurrentFragmentProgram is used for |
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| 115 | * rendering, CurrentFragmentProgram is used for this check to |
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| 116 | * differentiate between the GLSL and non-GLSL cases. |
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| 117 | */ |
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| 118 | if (ctx->Shader.CurrentFragmentProgram == NULL) |
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| 119 | wm->thread1.floating_point_mode = BRW_FLOATING_POINT_NON_IEEE_754; |
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| 120 | else |
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| 121 | wm->thread1.floating_point_mode = BRW_FLOATING_POINT_IEEE_754; |
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| 122 | |||
| 123 | wm->thread1.binding_table_entry_count = 0; |
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| 124 | |||
| 125 | if (brw->wm.prog_data->total_scratch != 0) { |
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| 126 | wm->thread2.scratch_space_base_pointer = |
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| 127 | brw->wm.scratch_bo->offset >> 10; /* reloc */ |
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| 128 | wm->thread2.per_thread_scratch_space = |
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| 129 | ffs(brw->wm.prog_data->total_scratch) - 11; |
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| 130 | } else { |
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| 131 | wm->thread2.scratch_space_base_pointer = 0; |
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| 132 | wm->thread2.per_thread_scratch_space = 0; |
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| 133 | } |
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| 134 | |||
| 135 | wm->thread3.dispatch_grf_start_reg = brw->wm.prog_data->first_curbe_grf; |
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| 136 | wm->thread3.urb_entry_read_length = brw->wm.prog_data->urb_read_length; |
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| 137 | wm->thread3.urb_entry_read_offset = 0; |
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| 138 | wm->thread3.const_urb_entry_read_length = |
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| 139 | brw->wm.prog_data->curb_read_length; |
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| 140 | /* BRW_NEW_CURBE_OFFSETS */ |
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| 141 | wm->thread3.const_urb_entry_read_offset = brw->curbe.wm_start * 2; |
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| 142 | |||
| 143 | if (brw->gen == 5) |
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| 144 | wm->wm4.sampler_count = 0; /* hardware requirement */ |
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| 145 | else { |
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| 146 | /* CACHE_NEW_SAMPLER */ |
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| 147 | wm->wm4.sampler_count = (brw->sampler.count + 1) / 4; |
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| 148 | } |
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| 149 | |||
| 150 | if (brw->sampler.count) { |
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| 151 | /* reloc */ |
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| 152 | wm->wm4.sampler_state_pointer = (brw->batch.bo->offset + |
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| 153 | brw->sampler.offset) >> 5; |
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| 154 | } else { |
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| 155 | wm->wm4.sampler_state_pointer = 0; |
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| 156 | } |
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| 157 | |||
| 158 | /* BRW_NEW_FRAGMENT_PROGRAM */ |
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| 159 | wm->wm5.program_uses_depth = (fp->Base.InputsRead & |
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| 160 | (1 << VARYING_SLOT_POS)) != 0; |
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| 161 | wm->wm5.program_computes_depth = (fp->Base.OutputsWritten & |
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| 162 | BITFIELD64_BIT(FRAG_RESULT_DEPTH)) != 0; |
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| 163 | /* _NEW_BUFFERS |
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| 164 | * Override for NULL depthbuffer case, required by the Pixel Shader Computed |
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| 165 | * Depth field. |
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| 166 | */ |
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| 167 | if (!intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH)) |
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| 168 | wm->wm5.program_computes_depth = 0; |
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| 169 | |||
| 170 | /* _NEW_COLOR */ |
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| 171 | wm->wm5.program_uses_killpixel = fp->UsesKill || ctx->Color.AlphaEnabled; |
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| 172 | |||
| 173 | wm->wm5.enable_8_pix = 1; |
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| 174 | if (brw->wm.prog_data->prog_offset_16) |
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| 175 | wm->wm5.enable_16_pix = 1; |
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| 176 | |||
| 177 | wm->wm5.max_threads = brw->max_wm_threads - 1; |
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| 178 | |||
| 179 | /* _NEW_BUFFERS | _NEW_COLOR */ |
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| 180 | if (brw_color_buffer_write_enabled(brw) || |
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| 181 | wm->wm5.program_uses_killpixel || |
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| 182 | wm->wm5.program_computes_depth) { |
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| 183 | wm->wm5.thread_dispatch_enable = 1; |
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| 184 | } |
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| 185 | |||
| 186 | wm->wm5.legacy_line_rast = 0; |
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| 187 | wm->wm5.legacy_global_depth_bias = 0; |
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| 188 | wm->wm5.early_depth_test = 1; /* never need to disable */ |
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| 189 | wm->wm5.line_aa_region_width = 0; |
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| 190 | wm->wm5.line_endcap_aa_region_width = 1; |
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| 191 | |||
| 192 | /* _NEW_POLYGONSTIPPLE */ |
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| 193 | wm->wm5.polygon_stipple = ctx->Polygon.StippleFlag; |
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| 194 | |||
| 195 | /* _NEW_POLYGON */ |
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| 196 | if (ctx->Polygon.OffsetFill) { |
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| 197 | wm->wm5.depth_offset = 1; |
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| 198 | /* Something wierd going on with legacy_global_depth_bias, |
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| 199 | * offset_constant, scaling and MRD. This value passes glean |
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| 200 | * but gives some odd results elsewere (eg. the |
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| 201 | * quad-offset-units test). |
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| 202 | */ |
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| 203 | wm->global_depth_offset_constant = ctx->Polygon.OffsetUnits * 2; |
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| 204 | |||
| 205 | /* This is the only value that passes glean: |
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| 206 | */ |
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| 207 | wm->global_depth_offset_scale = ctx->Polygon.OffsetFactor; |
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| 208 | } |
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| 209 | |||
| 210 | /* _NEW_LINE */ |
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| 211 | wm->wm5.line_stipple = ctx->Line.StippleFlag; |
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| 212 | |||
| 213 | /* BRW_NEW_STATS_WM */ |
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| 214 | if (unlikely(INTEL_DEBUG & DEBUG_STATS) || brw->stats_wm) |
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| 215 | wm->wm4.stats_enable = 1; |
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| 216 | |||
| 217 | /* Emit scratch space relocation */ |
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| 218 | if (brw->wm.prog_data->total_scratch != 0) { |
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| 219 | drm_intel_bo_emit_reloc(brw->batch.bo, |
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| 220 | brw->wm.state_offset + |
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| 221 | offsetof(struct brw_wm_unit_state, thread2), |
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| 222 | brw->wm.scratch_bo, |
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| 223 | wm->thread2.per_thread_scratch_space, |
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| 224 | I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER); |
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| 225 | } |
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| 226 | |||
| 227 | /* Emit sampler state relocation */ |
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| 228 | if (brw->sampler.count != 0) { |
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| 229 | drm_intel_bo_emit_reloc(brw->batch.bo, |
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| 230 | brw->wm.state_offset + |
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| 231 | offsetof(struct brw_wm_unit_state, wm4), |
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| 232 | brw->batch.bo, (brw->sampler.offset | |
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| 233 | wm->wm4.stats_enable | |
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| 234 | (wm->wm4.sampler_count << 2)), |
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| 235 | I915_GEM_DOMAIN_INSTRUCTION, 0); |
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| 236 | } |
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| 237 | |||
| 238 | brw->state.dirty.cache |= CACHE_NEW_WM_UNIT; |
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| 239 | } |
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| 240 | |||
| 241 | const struct brw_tracked_state brw_wm_unit = { |
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| 242 | .dirty = { |
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| 243 | .mesa = (_NEW_POLYGON | |
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| 244 | _NEW_POLYGONSTIPPLE | |
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| 245 | _NEW_LINE | |
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| 246 | _NEW_COLOR | |
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| 247 | _NEW_BUFFERS), |
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| 248 | |||
| 249 | .brw = (BRW_NEW_BATCH | |
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| 250 | BRW_NEW_PROGRAM_CACHE | |
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| 251 | BRW_NEW_FRAGMENT_PROGRAM | |
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| 252 | BRW_NEW_CURBE_OFFSETS | |
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| 253 | BRW_NEW_STATS_WM), |
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| 254 | |||
| 255 | .cache = (CACHE_NEW_WM_PROG | |
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| 256 | CACHE_NEW_SAMPLER) |
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| 257 | }, |
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| 258 | .emit = brw_upload_wm_unit, |
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| 259 | }; |
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| 260 |