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4358 | Serge | 1 | /* |
2 | * Copyright © 2010 Intel Corporation |
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3 | * |
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4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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5 | * copy of this software and associated documentation files (the "Software"), |
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6 | * to deal in the Software without restriction, including without limitation |
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7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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8 | * and/or sell copies of the Software, and to permit persons to whom the |
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9 | * Software is furnished to do so, subject to the following conditions: |
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10 | * |
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11 | * The above copyright notice and this permission notice (including the next |
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12 | * paragraph) shall be included in all copies or substantial portions of the |
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13 | * Software. |
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14 | * |
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15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER |
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21 | * DEALINGS IN THE SOFTWARE. |
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22 | */ |
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23 | |||
24 | /** |
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25 | * \file brw_wm_channel_expressions.cpp |
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26 | * |
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27 | * Breaks vector operations down into operations on each component. |
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28 | * |
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29 | * The 965 fragment shader receives 8 or 16 pixels at a time, so each |
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30 | * channel of a vector is laid out as 1 or 2 8-float registers. Each |
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31 | * ALU operation operates on one of those channel registers. As a |
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32 | * result, there is no value to the 965 fragment shader in tracking |
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33 | * "vector" expressions in the sense of GLSL fragment shaders, when |
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34 | * doing a channel at a time may help in constant folding, algebraic |
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35 | * simplification, and reducing the liveness of channel registers. |
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36 | * |
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37 | * The exception to the desire to break everything down to floats is |
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38 | * texturing. The texture sampler returns a writemasked masked |
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39 | * 4/8-register sequence containing the texture values. We don't want |
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40 | * to dispatch to the sampler separately for each channel we need, so |
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41 | * we do retain the vector types in that case. |
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42 | */ |
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43 | |||
44 | extern "C" { |
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45 | #include "main/core.h" |
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46 | #include "brw_wm.h" |
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47 | } |
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48 | #include "glsl/ir.h" |
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49 | #include "glsl/ir_expression_flattening.h" |
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50 | #include "glsl/glsl_types.h" |
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51 | |||
52 | class ir_channel_expressions_visitor : public ir_hierarchical_visitor { |
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53 | public: |
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54 | ir_channel_expressions_visitor() |
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55 | { |
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56 | this->progress = false; |
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57 | this->mem_ctx = NULL; |
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58 | } |
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59 | |||
60 | ir_visitor_status visit_leave(ir_assignment *); |
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61 | |||
62 | ir_rvalue *get_element(ir_variable *var, unsigned int element); |
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63 | void assign(ir_assignment *ir, int elem, ir_rvalue *val); |
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64 | |||
65 | bool progress; |
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66 | void *mem_ctx; |
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67 | }; |
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68 | |||
69 | static bool |
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70 | channel_expressions_predicate(ir_instruction *ir) |
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71 | { |
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72 | ir_expression *expr = ir->as_expression(); |
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73 | unsigned int i; |
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74 | |||
75 | if (!expr) |
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76 | return false; |
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77 | |||
78 | for (i = 0; i < expr->get_num_operands(); i++) { |
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79 | if (expr->operands[i]->type->is_vector()) |
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80 | return true; |
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81 | } |
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82 | |||
83 | return false; |
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84 | } |
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85 | |||
86 | bool |
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87 | brw_do_channel_expressions(exec_list *instructions) |
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88 | { |
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89 | ir_channel_expressions_visitor v; |
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90 | |||
91 | /* Pull out any matrix expression to a separate assignment to a |
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92 | * temp. This will make our handling of the breakdown to |
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93 | * operations on the matrix's vector components much easier. |
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94 | */ |
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95 | do_expression_flattening(instructions, channel_expressions_predicate); |
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96 | |||
97 | visit_list_elements(&v, instructions); |
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98 | |||
99 | return v.progress; |
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100 | } |
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101 | |||
102 | ir_rvalue * |
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103 | ir_channel_expressions_visitor::get_element(ir_variable *var, unsigned int elem) |
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104 | { |
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105 | ir_dereference *deref; |
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106 | |||
107 | if (var->type->is_scalar()) |
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108 | return new(mem_ctx) ir_dereference_variable(var); |
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109 | |||
110 | assert(elem < var->type->components()); |
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111 | deref = new(mem_ctx) ir_dereference_variable(var); |
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112 | return new(mem_ctx) ir_swizzle(deref, elem, 0, 0, 0, 1); |
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113 | } |
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114 | |||
115 | void |
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116 | ir_channel_expressions_visitor::assign(ir_assignment *ir, int elem, ir_rvalue *val) |
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117 | { |
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118 | ir_dereference *lhs = ir->lhs->clone(mem_ctx, NULL); |
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119 | ir_assignment *assign; |
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120 | |||
121 | /* This assign-of-expression should have been generated by the |
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122 | * expression flattening visitor (since we never short circit to |
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123 | * not flatten, even for plain assignments of variables), so the |
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124 | * writemask is always full. |
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125 | */ |
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126 | assert(ir->write_mask == (1 << ir->lhs->type->components()) - 1); |
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127 | |||
128 | assign = new(mem_ctx) ir_assignment(lhs, val, NULL, (1 << elem)); |
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129 | ir->insert_before(assign); |
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130 | } |
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131 | |||
132 | ir_visitor_status |
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133 | ir_channel_expressions_visitor::visit_leave(ir_assignment *ir) |
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134 | { |
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135 | ir_expression *expr = ir->rhs->as_expression(); |
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136 | bool found_vector = false; |
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137 | unsigned int i, vector_elements = 1; |
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138 | ir_variable *op_var[3]; |
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139 | |||
140 | if (!expr) |
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141 | return visit_continue; |
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142 | |||
143 | if (!this->mem_ctx) |
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144 | this->mem_ctx = ralloc_parent(ir); |
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145 | |||
146 | for (i = 0; i < expr->get_num_operands(); i++) { |
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147 | if (expr->operands[i]->type->is_vector()) { |
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148 | found_vector = true; |
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149 | vector_elements = expr->operands[i]->type->vector_elements; |
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150 | break; |
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151 | } |
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152 | } |
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153 | if (!found_vector) |
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154 | return visit_continue; |
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155 | |||
156 | /* Store the expression operands in temps so we can use them |
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157 | * multiple times. |
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158 | */ |
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159 | for (i = 0; i < expr->get_num_operands(); i++) { |
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160 | ir_assignment *assign; |
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161 | ir_dereference *deref; |
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162 | |||
163 | assert(!expr->operands[i]->type->is_matrix()); |
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164 | |||
165 | op_var[i] = new(mem_ctx) ir_variable(expr->operands[i]->type, |
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166 | "channel_expressions", |
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167 | ir_var_temporary); |
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168 | ir->insert_before(op_var[i]); |
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169 | |||
170 | deref = new(mem_ctx) ir_dereference_variable(op_var[i]); |
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171 | assign = new(mem_ctx) ir_assignment(deref, |
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172 | expr->operands[i], |
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173 | NULL); |
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174 | ir->insert_before(assign); |
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175 | } |
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176 | |||
177 | const glsl_type *element_type = glsl_type::get_instance(ir->lhs->type->base_type, |
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178 | 1, 1); |
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179 | |||
180 | /* OK, time to break down this vector operation. */ |
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181 | switch (expr->operation) { |
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182 | case ir_unop_bit_not: |
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183 | case ir_unop_logic_not: |
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184 | case ir_unop_neg: |
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185 | case ir_unop_abs: |
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186 | case ir_unop_sign: |
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187 | case ir_unop_rcp: |
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188 | case ir_unop_rsq: |
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189 | case ir_unop_sqrt: |
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190 | case ir_unop_exp: |
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191 | case ir_unop_log: |
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192 | case ir_unop_exp2: |
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193 | case ir_unop_log2: |
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194 | case ir_unop_bitcast_i2f: |
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195 | case ir_unop_bitcast_f2i: |
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196 | case ir_unop_bitcast_f2u: |
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197 | case ir_unop_bitcast_u2f: |
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198 | case ir_unop_i2u: |
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199 | case ir_unop_u2i: |
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200 | case ir_unop_f2i: |
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201 | case ir_unop_f2u: |
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202 | case ir_unop_i2f: |
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203 | case ir_unop_f2b: |
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204 | case ir_unop_b2f: |
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205 | case ir_unop_i2b: |
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206 | case ir_unop_b2i: |
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207 | case ir_unop_u2f: |
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208 | case ir_unop_trunc: |
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209 | case ir_unop_ceil: |
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210 | case ir_unop_floor: |
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211 | case ir_unop_fract: |
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212 | case ir_unop_round_even: |
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213 | case ir_unop_sin: |
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214 | case ir_unop_cos: |
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215 | case ir_unop_sin_reduced: |
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216 | case ir_unop_cos_reduced: |
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217 | case ir_unop_dFdx: |
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218 | case ir_unop_dFdy: |
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219 | case ir_unop_bitfield_reverse: |
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220 | case ir_unop_bit_count: |
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221 | case ir_unop_find_msb: |
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222 | case ir_unop_find_lsb: |
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223 | for (i = 0; i < vector_elements; i++) { |
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224 | ir_rvalue *op0 = get_element(op_var[0], i); |
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225 | |||
226 | assign(ir, i, new(mem_ctx) ir_expression(expr->operation, |
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227 | element_type, |
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228 | op0, |
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229 | NULL)); |
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230 | } |
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231 | break; |
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232 | |||
233 | case ir_binop_add: |
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234 | case ir_binop_sub: |
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235 | case ir_binop_mul: |
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236 | case ir_binop_div: |
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237 | case ir_binop_mod: |
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238 | case ir_binop_min: |
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239 | case ir_binop_max: |
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240 | case ir_binop_pow: |
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241 | case ir_binop_lshift: |
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242 | case ir_binop_rshift: |
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243 | case ir_binop_bit_and: |
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244 | case ir_binop_bit_xor: |
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245 | case ir_binop_bit_or: |
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246 | case ir_binop_less: |
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247 | case ir_binop_greater: |
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248 | case ir_binop_lequal: |
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249 | case ir_binop_gequal: |
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250 | case ir_binop_equal: |
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251 | case ir_binop_nequal: |
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252 | for (i = 0; i < vector_elements; i++) { |
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253 | ir_rvalue *op0 = get_element(op_var[0], i); |
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254 | ir_rvalue *op1 = get_element(op_var[1], i); |
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255 | |||
256 | assign(ir, i, new(mem_ctx) ir_expression(expr->operation, |
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257 | element_type, |
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258 | op0, |
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259 | op1)); |
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260 | } |
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261 | break; |
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262 | |||
263 | case ir_unop_any: { |
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264 | ir_expression *temp; |
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265 | temp = new(mem_ctx) ir_expression(ir_binop_logic_or, |
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266 | element_type, |
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267 | get_element(op_var[0], 0), |
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268 | get_element(op_var[0], 1)); |
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269 | |||
270 | for (i = 2; i < vector_elements; i++) { |
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271 | temp = new(mem_ctx) ir_expression(ir_binop_logic_or, |
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272 | element_type, |
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273 | get_element(op_var[0], i), |
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274 | temp); |
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275 | } |
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276 | assign(ir, 0, temp); |
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277 | break; |
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278 | } |
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279 | |||
280 | case ir_binop_dot: { |
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281 | ir_expression *last = NULL; |
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282 | for (i = 0; i < vector_elements; i++) { |
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283 | ir_rvalue *op0 = get_element(op_var[0], i); |
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284 | ir_rvalue *op1 = get_element(op_var[1], i); |
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285 | ir_expression *temp; |
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286 | |||
287 | temp = new(mem_ctx) ir_expression(ir_binop_mul, |
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288 | element_type, |
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289 | op0, |
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290 | op1); |
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291 | if (last) { |
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292 | last = new(mem_ctx) ir_expression(ir_binop_add, |
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293 | element_type, |
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294 | temp, |
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295 | last); |
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296 | } else { |
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297 | last = temp; |
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298 | } |
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299 | } |
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300 | assign(ir, 0, last); |
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301 | break; |
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302 | } |
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303 | |||
304 | case ir_binop_logic_and: |
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305 | case ir_binop_logic_xor: |
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306 | case ir_binop_logic_or: |
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307 | ir->print(); |
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308 | printf("\n"); |
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309 | assert(!"not reached: expression operates on scalars only"); |
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310 | break; |
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311 | case ir_binop_all_equal: |
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312 | case ir_binop_any_nequal: { |
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313 | ir_expression *last = NULL; |
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314 | for (i = 0; i < vector_elements; i++) { |
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315 | ir_rvalue *op0 = get_element(op_var[0], i); |
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316 | ir_rvalue *op1 = get_element(op_var[1], i); |
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317 | ir_expression *temp; |
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318 | ir_expression_operation join; |
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319 | |||
320 | if (expr->operation == ir_binop_all_equal) |
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321 | join = ir_binop_logic_and; |
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322 | else |
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323 | join = ir_binop_logic_or; |
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324 | |||
325 | temp = new(mem_ctx) ir_expression(expr->operation, |
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326 | element_type, |
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327 | op0, |
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328 | op1); |
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329 | if (last) { |
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330 | last = new(mem_ctx) ir_expression(join, |
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331 | element_type, |
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332 | temp, |
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333 | last); |
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334 | } else { |
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335 | last = temp; |
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336 | } |
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337 | } |
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338 | assign(ir, 0, last); |
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339 | break; |
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340 | } |
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341 | case ir_unop_noise: |
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342 | assert(!"noise should have been broken down to function call"); |
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343 | break; |
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344 | |||
345 | case ir_binop_bfm: { |
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346 | /* Does not need to be scalarized, since its result will be identical |
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347 | * for all channels. |
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348 | */ |
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349 | ir_rvalue *op0 = get_element(op_var[0], 0); |
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350 | ir_rvalue *op1 = get_element(op_var[1], 0); |
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351 | |||
352 | assign(ir, 0, new(mem_ctx) ir_expression(expr->operation, |
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353 | element_type, |
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354 | op0, |
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355 | op1)); |
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356 | break; |
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357 | } |
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358 | |||
359 | case ir_binop_ubo_load: |
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360 | assert(!"not yet supported"); |
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361 | break; |
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362 | |||
363 | case ir_triop_lrp: |
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364 | case ir_triop_bitfield_extract: |
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365 | for (i = 0; i < vector_elements; i++) { |
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366 | ir_rvalue *op0 = get_element(op_var[0], i); |
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367 | ir_rvalue *op1 = get_element(op_var[1], i); |
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368 | ir_rvalue *op2 = get_element(op_var[2], i); |
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369 | |||
370 | assign(ir, i, new(mem_ctx) ir_expression(expr->operation, |
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371 | element_type, |
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372 | op0, |
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373 | op1, |
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374 | op2)); |
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375 | } |
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376 | break; |
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377 | |||
378 | case ir_triop_bfi: { |
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379 | /* Only a single BFM is needed for multiple BFIs. */ |
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380 | ir_rvalue *op0 = get_element(op_var[0], 0); |
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381 | |||
382 | for (i = 0; i < vector_elements; i++) { |
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383 | ir_rvalue *op1 = get_element(op_var[1], i); |
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384 | ir_rvalue *op2 = get_element(op_var[2], i); |
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385 | |||
386 | assign(ir, i, new(mem_ctx) ir_expression(expr->operation, |
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387 | element_type, |
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388 | op0->clone(mem_ctx, NULL), |
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389 | op1, |
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390 | op2)); |
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391 | } |
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392 | break; |
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393 | } |
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394 | |||
395 | case ir_unop_pack_snorm_2x16: |
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396 | case ir_unop_pack_snorm_4x8: |
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397 | case ir_unop_pack_unorm_2x16: |
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398 | case ir_unop_pack_unorm_4x8: |
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399 | case ir_unop_pack_half_2x16: |
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400 | case ir_unop_unpack_snorm_2x16: |
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401 | case ir_unop_unpack_snorm_4x8: |
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402 | case ir_unop_unpack_unorm_2x16: |
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403 | case ir_unop_unpack_unorm_4x8: |
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404 | case ir_unop_unpack_half_2x16: |
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405 | case ir_binop_vector_extract: |
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406 | case ir_triop_vector_insert: |
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407 | case ir_quadop_bitfield_insert: |
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408 | case ir_quadop_vector: |
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409 | assert(!"should have been lowered"); |
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410 | break; |
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411 | |||
412 | case ir_unop_unpack_half_2x16_split_x: |
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413 | case ir_unop_unpack_half_2x16_split_y: |
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414 | case ir_binop_pack_half_2x16_split: |
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415 | assert("!not reached: expression operates on scalars only"); |
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416 | break; |
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417 | } |
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418 | |||
419 | ir->remove(); |
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420 | this->progress = true; |
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421 | |||
422 | return visit_continue; |
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423 | }>>>>>>>>>><>><>>> |