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4358 | Serge | 1 | /************************************************************************** |
2 | * |
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3 | * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. |
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4 | * All Rights Reserved. |
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5 | * |
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6 | * Permission is hereby granted, free of charge, to any person obtaining a |
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7 | * copy of this software and associated documentation files (the |
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8 | * "Software"), to deal in the Software without restriction, including |
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9 | * without limitation the rights to use, copy, modify, merge, publish, |
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10 | * distribute, sub license, and/or sell copies of the Software, and to |
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11 | * permit persons to whom the Software is furnished to do so, subject to |
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12 | * the following conditions: |
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13 | * |
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14 | * The above copyright notice and this permission notice (including the |
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15 | * next paragraph) shall be included in all copies or substantial portions |
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16 | * of the Software. |
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17 | * |
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18 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
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19 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
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20 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. |
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21 | * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR |
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22 | * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, |
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23 | * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE |
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24 | * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. |
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25 | * |
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26 | **************************************************************************/ |
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27 | |||
28 | |||
29 | #ifndef _I915_REG_H_ |
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30 | #define _I915_REG_H_ |
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31 | |||
32 | |||
33 | #include "intel_reg.h" |
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34 | |||
35 | #define I915_SET_FIELD( var, mask, value ) (var &= ~(mask), var |= value) |
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36 | |||
37 | #define PRIM3D_INLINE (CMD_3D | (0x1f<<24)) |
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38 | #define PRIM3D_TRILIST (0x0<<18) |
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39 | #define PRIM3D_TRISTRIP (0x1<<18) |
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40 | #define PRIM3D_TRISTRIP_RVRSE (0x2<<18) |
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41 | #define PRIM3D_TRIFAN (0x3<<18) |
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42 | #define PRIM3D_POLY (0x4<<18) |
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43 | #define PRIM3D_LINELIST (0x5<<18) |
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44 | #define PRIM3D_LINESTRIP (0x6<<18) |
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45 | #define PRIM3D_RECTLIST (0x7<<18) |
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46 | #define PRIM3D_POINTLIST (0x8<<18) |
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47 | #define PRIM3D_DIB (0x9<<18) |
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48 | #define PRIM3D_CLEAR_RECT (0xa<<18) |
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49 | #define PRIM3D_ZONE_INIT (0xd<<18) |
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50 | #define PRIM3D_MASK (0x1f<<18) |
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51 | |||
52 | /* p137 */ |
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53 | #define _3DSTATE_AA_CMD (CMD_3D | (0x06<<24)) |
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54 | #define AA_LINE_ECAAR_WIDTH_ENABLE (1<<16) |
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55 | #define AA_LINE_ECAAR_WIDTH_0_5 0 |
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56 | #define AA_LINE_ECAAR_WIDTH_1_0 (1<<14) |
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57 | #define AA_LINE_ECAAR_WIDTH_2_0 (2<<14) |
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58 | #define AA_LINE_ECAAR_WIDTH_4_0 (3<<14) |
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59 | #define AA_LINE_REGION_WIDTH_ENABLE (1<<8) |
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60 | #define AA_LINE_REGION_WIDTH_0_5 0 |
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61 | #define AA_LINE_REGION_WIDTH_1_0 (1<<6) |
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62 | #define AA_LINE_REGION_WIDTH_2_0 (2<<6) |
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63 | #define AA_LINE_REGION_WIDTH_4_0 (3<<6) |
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64 | |||
65 | /* 3DSTATE_BACKFACE_STENCIL_OPS, p138*/ |
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66 | #define _3DSTATE_BACKFACE_STENCIL_OPS (CMD_3D | (0x8<<24)) |
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67 | #define BFO_ENABLE_STENCIL_REF (1<<23) |
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68 | #define BFO_STENCIL_REF_SHIFT 15 |
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69 | #define BFO_STENCIL_REF_MASK (0xff<<15) |
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70 | #define BFO_ENABLE_STENCIL_FUNCS (1<<14) |
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71 | #define BFO_STENCIL_TEST_SHIFT 11 |
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72 | #define BFO_STENCIL_TEST_MASK (0x7<<11) |
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73 | #define BFO_STENCIL_FAIL_SHIFT 8 |
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74 | #define BFO_STENCIL_FAIL_MASK (0x7<<8) |
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75 | #define BFO_STENCIL_PASS_Z_FAIL_SHIFT 5 |
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76 | #define BFO_STENCIL_PASS_Z_FAIL_MASK (0x7<<5) |
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77 | #define BFO_STENCIL_PASS_Z_PASS_SHIFT 2 |
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78 | #define BFO_STENCIL_PASS_Z_PASS_MASK (0x7<<2) |
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79 | #define BFO_ENABLE_STENCIL_TWO_SIDE (1<<1) |
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80 | #define BFO_STENCIL_TWO_SIDE (1<<0) |
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81 | |||
82 | |||
83 | /* 3DSTATE_BACKFACE_STENCIL_MASKS, p140 */ |
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84 | #define _3DSTATE_BACKFACE_STENCIL_MASKS (CMD_3D | (0x9<<24)) |
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85 | #define BFM_ENABLE_STENCIL_TEST_MASK (1<<17) |
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86 | #define BFM_ENABLE_STENCIL_WRITE_MASK (1<<16) |
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87 | #define BFM_STENCIL_TEST_MASK_SHIFT 8 |
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88 | #define BFM_STENCIL_TEST_MASK_MASK (0xff<<8) |
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89 | #define BFM_STENCIL_TEST_MASK(x) (((x)&0xff) << 8) |
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90 | #define BFM_STENCIL_WRITE_MASK_SHIFT 0 |
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91 | #define BFM_STENCIL_WRITE_MASK_MASK (0xff<<0) |
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92 | #define BFM_STENCIL_WRITE_MASK(x) ((x)&0xff) |
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93 | |||
94 | |||
95 | |||
96 | /* 3DSTATE_BIN_CONTROL p141 */ |
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97 | |||
98 | /* 3DSTATE_CHROMA_KEY */ |
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99 | |||
100 | /* 3DSTATE_CLEAR_PARAMETERS, p150 */ |
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101 | /* |
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102 | * Sets the color, depth and stencil clear values used by the |
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103 | * CLEAR_RECT and ZONE_INIT primitive types, respectively. These |
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104 | * primitives set override most 3d state and only take a minimal x/y |
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105 | * vertex. The color/z/stencil information is supplied here and |
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106 | * therefore cannot vary per vertex. |
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107 | */ |
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108 | #define _3DSTATE_CLEAR_PARAMETERS (CMD_3D | (0x1d<<24) | (0x9c<<16) | 5) |
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109 | /* Dword 1 */ |
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110 | #define CLEARPARAM_CLEAR_RECT (1 << 16) |
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111 | #define CLEARPARAM_ZONE_INIT (0 << 16) |
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112 | #define CLEARPARAM_WRITE_COLOR (1 << 2) |
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113 | #define CLEARPARAM_WRITE_DEPTH (1 << 1) |
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114 | #define CLEARPARAM_WRITE_STENCIL (1 << 0) |
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115 | |||
116 | /* 3DSTATE_CONSTANT_BLEND_COLOR, p153 */ |
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117 | #define _3DSTATE_CONST_BLEND_COLOR_CMD (CMD_3D | (0x1d<<24) | (0x88<<16)) |
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118 | |||
119 | |||
120 | |||
121 | /* 3DSTATE_COORD_SET_BINDINGS, p154 */ |
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122 | #define _3DSTATE_COORD_SET_BINDINGS (CMD_3D | (0x16<<24)) |
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123 | #define CSB_TCB(iunit, eunit) ((eunit)<<(iunit*3)) |
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124 | |||
125 | /* p156 */ |
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126 | #define _3DSTATE_DFLT_DIFFUSE_CMD (CMD_3D | (0x1d<<24) | (0x99<<16)) |
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127 | |||
128 | /* p157 */ |
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129 | #define _3DSTATE_DFLT_SPEC_CMD (CMD_3D | (0x1d<<24) | (0x9a<<16)) |
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130 | |||
131 | /* p158 */ |
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132 | #define _3DSTATE_DFLT_Z_CMD (CMD_3D | (0x1d<<24) | (0x98<<16)) |
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133 | |||
134 | |||
135 | /* 3DSTATE_DEPTH_OFFSET_SCALE, p159 */ |
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136 | #define _3DSTATE_DEPTH_OFFSET_SCALE (CMD_3D | (0x1d<<24) | (0x97<<16)) |
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137 | /* scale in dword 1 */ |
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138 | |||
139 | |||
140 | /* 3DSTATE_DEPTH_SUBRECT_DISABLE, p160 */ |
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141 | #define _3DSTATE_DEPTH_SUBRECT_DISABLE (CMD_3D | (0x1c<<24) | (0x11<<19) | 0x2) |
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142 | |||
143 | /* p161 */ |
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144 | #define _3DSTATE_DST_BUF_VARS_CMD (CMD_3D | (0x1d<<24) | (0x85<<16)) |
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145 | /* Dword 1 */ |
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146 | #define CLASSIC_EARLY_DEPTH (1<<31) |
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147 | #define TEX_DEFAULT_COLOR_OGL (0<<30) |
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148 | #define TEX_DEFAULT_COLOR_D3D (1<<30) |
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149 | #define ZR_EARLY_DEPTH (1<<29) |
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150 | #define LOD_PRECLAMP_OGL (1<<28) |
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151 | #define LOD_PRECLAMP_D3D (0<<28) |
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152 | #define DITHER_FULL_ALWAYS (0<<26) |
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153 | #define DITHER_FULL_ON_FB_BLEND (1<<26) |
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154 | #define DITHER_CLAMPED_ALWAYS (2<<26) |
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155 | #define LINEAR_GAMMA_BLEND_32BPP (1<<25) |
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156 | #define DEBUG_DISABLE_ENH_DITHER (1<<24) |
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157 | #define DSTORG_HORT_BIAS(x) ((x)<<20) |
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158 | #define DSTORG_VERT_BIAS(x) ((x)<<16) |
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159 | #define COLOR_4_2_2_CHNL_WRT_ALL 0 |
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160 | #define COLOR_4_2_2_CHNL_WRT_Y (1<<12) |
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161 | #define COLOR_4_2_2_CHNL_WRT_CR (2<<12) |
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162 | #define COLOR_4_2_2_CHNL_WRT_CB (3<<12) |
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163 | #define COLOR_4_2_2_CHNL_WRT_CRCB (4<<12) |
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164 | #define COLR_BUF_8BIT 0 |
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165 | #define COLR_BUF_RGB555 (1<<8) |
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166 | #define COLR_BUF_RGB565 (2<<8) |
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167 | #define COLR_BUF_ARGB8888 (3<<8) |
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168 | #define DEPTH_FRMT_16_FIXED 0 |
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169 | #define DEPTH_FRMT_16_FLOAT (1<<2) |
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170 | #define DEPTH_FRMT_24_FIXED_8_OTHER (2<<2) |
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171 | #define VERT_LINE_STRIDE_1 (1<<1) |
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172 | #define VERT_LINE_STRIDE_0 (0<<1) |
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173 | #define VERT_LINE_STRIDE_OFS_1 1 |
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174 | #define VERT_LINE_STRIDE_OFS_0 0 |
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175 | |||
176 | /* p166 */ |
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177 | #define _3DSTATE_DRAW_RECT_CMD (CMD_3D|(0x1d<<24)|(0x80<<16)|3) |
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178 | /* Dword 1 */ |
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179 | #define DRAW_RECT_DIS_DEPTH_OFS (1<<30) |
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180 | #define DRAW_DITHER_OFS_X(x) ((x)<<26) |
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181 | #define DRAW_DITHER_OFS_Y(x) ((x)<<24) |
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182 | /* Dword 2 */ |
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183 | #define DRAW_YMIN(x) ((x)<<16) |
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184 | #define DRAW_XMIN(x) (x) |
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185 | /* Dword 3 */ |
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186 | #define DRAW_YMAX(x) ((x)<<16) |
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187 | #define DRAW_XMAX(x) (x) |
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188 | /* Dword 4 */ |
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189 | #define DRAW_YORG(x) ((x)<<16) |
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190 | #define DRAW_XORG(x) (x) |
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191 | |||
192 | |||
193 | /* 3DSTATE_FILTER_COEFFICIENTS_4X4, p170 */ |
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194 | |||
195 | /* 3DSTATE_FILTER_COEFFICIENTS_6X5, p172 */ |
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196 | |||
197 | |||
198 | /* _3DSTATE_FOG_COLOR, p173 */ |
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199 | #define _3DSTATE_FOG_COLOR_CMD (CMD_3D|(0x15<<24)) |
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200 | #define FOG_COLOR_RED(x) ((x)<<16) |
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201 | #define FOG_COLOR_GREEN(x) ((x)<<8) |
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202 | #define FOG_COLOR_BLUE(x) (x) |
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203 | |||
204 | /* _3DSTATE_FOG_MODE, p174 */ |
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205 | #define _3DSTATE_FOG_MODE_CMD (CMD_3D|(0x1d<<24)|(0x89<<16)|2) |
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206 | /* Dword 1 */ |
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207 | #define FMC1_FOGFUNC_MODIFY_ENABLE (1<<31) |
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208 | #define FMC1_FOGFUNC_VERTEX (0<<28) |
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209 | #define FMC1_FOGFUNC_PIXEL_EXP (1<<28) |
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210 | #define FMC1_FOGFUNC_PIXEL_EXP2 (2<<28) |
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211 | #define FMC1_FOGFUNC_PIXEL_LINEAR (3<<28) |
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212 | #define FMC1_FOGFUNC_MASK (3<<28) |
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213 | #define FMC1_FOGINDEX_MODIFY_ENABLE (1<<27) |
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214 | #define FMC1_FOGINDEX_Z (0<<25) |
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215 | #define FMC1_FOGINDEX_W (1<<25) |
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216 | #define FMC1_C1_C2_MODIFY_ENABLE (1<<24) |
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217 | #define FMC1_DENSITY_MODIFY_ENABLE (1<<23) |
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218 | #define FMC1_C1_ONE (1<<13) |
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219 | #define FMC1_C1_MASK (0xffff<<4) |
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220 | /* Dword 2 */ |
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221 | #define FMC2_C2_ONE (1<<16) |
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222 | /* Dword 3 */ |
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223 | #define FMC3_D_ONE (1<<16) |
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224 | |||
225 | |||
226 | |||
227 | /* _3DSTATE_INDEPENDENT_ALPHA_BLEND, p177 */ |
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228 | #define _3DSTATE_INDEPENDENT_ALPHA_BLEND_CMD (CMD_3D|(0x0b<<24)) |
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229 | #define IAB_MODIFY_ENABLE (1<<23) |
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230 | #define IAB_ENABLE (1<<22) |
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231 | #define IAB_MODIFY_FUNC (1<<21) |
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232 | #define IAB_FUNC_SHIFT 16 |
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233 | #define IAB_MODIFY_SRC_FACTOR (1<<11) |
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234 | #define IAB_SRC_FACTOR_SHIFT 6 |
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235 | #define IAB_SRC_FACTOR_MASK (BLENDFACT_MASK<<6) |
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236 | #define IAB_MODIFY_DST_FACTOR (1<<5) |
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237 | #define IAB_DST_FACTOR_SHIFT 0 |
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238 | #define IAB_DST_FACTOR_MASK (BLENDFACT_MASK<<0) |
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239 | |||
240 | |||
241 | #define BLENDFUNC_ADD 0x0 |
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242 | #define BLENDFUNC_SUBTRACT 0x1 |
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243 | #define BLENDFUNC_REVERSE_SUBTRACT 0x2 |
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244 | #define BLENDFUNC_MIN 0x3 |
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245 | #define BLENDFUNC_MAX 0x4 |
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246 | #define BLENDFUNC_MASK 0x7 |
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247 | |||
248 | /* 3DSTATE_LOAD_INDIRECT, p180 */ |
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249 | |||
250 | #define _3DSTATE_LOAD_INDIRECT (CMD_3D|(0x1d<<24)|(0x7<<16)) |
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251 | #define LI0_STATE_STATIC_INDIRECT (0x01<<8) |
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252 | #define LI0_STATE_DYNAMIC_INDIRECT (0x02<<8) |
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253 | #define LI0_STATE_SAMPLER (0x04<<8) |
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254 | #define LI0_STATE_MAP (0x08<<8) |
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255 | #define LI0_STATE_PROGRAM (0x10<<8) |
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256 | #define LI0_STATE_CONSTANTS (0x20<<8) |
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257 | |||
258 | #define SIS0_BUFFER_ADDRESS(x) ((x)&~0x3) |
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259 | #define SIS0_FORCE_LOAD (1<<1) |
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260 | #define SIS0_BUFFER_VALID (1<<0) |
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261 | #define SIS1_BUFFER_LENGTH(x) ((x)&0xff) |
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262 | |||
263 | #define DIS0_BUFFER_ADDRESS(x) ((x)&~0x3) |
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264 | #define DIS0_BUFFER_RESET (1<<1) |
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265 | #define DIS0_BUFFER_VALID (1<<0) |
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266 | |||
267 | #define SSB0_BUFFER_ADDRESS(x) ((x)&~0x3) |
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268 | #define SSB0_FORCE_LOAD (1<<1) |
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269 | #define SSB0_BUFFER_VALID (1<<0) |
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270 | #define SSB1_BUFFER_LENGTH(x) ((x)&0xff) |
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271 | |||
272 | #define MSB0_BUFFER_ADDRESS(x) ((x)&~0x3) |
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273 | #define MSB0_FORCE_LOAD (1<<1) |
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274 | #define MSB0_BUFFER_VALID (1<<0) |
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275 | #define MSB1_BUFFER_LENGTH(x) ((x)&0xff) |
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276 | |||
277 | #define PSP0_BUFFER_ADDRESS(x) ((x)&~0x3) |
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278 | #define PSP0_FORCE_LOAD (1<<1) |
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279 | #define PSP0_BUFFER_VALID (1<<0) |
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280 | #define PSP1_BUFFER_LENGTH(x) ((x)&0xff) |
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281 | |||
282 | #define PSC0_BUFFER_ADDRESS(x) ((x)&~0x3) |
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283 | #define PSC0_FORCE_LOAD (1<<1) |
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284 | #define PSC0_BUFFER_VALID (1<<0) |
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285 | #define PSC1_BUFFER_LENGTH(x) ((x)&0xff) |
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286 | |||
287 | |||
288 | |||
289 | |||
290 | |||
291 | /* _3DSTATE_RASTERIZATION_RULES */ |
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292 | #define _3DSTATE_RASTER_RULES_CMD (CMD_3D|(0x07<<24)) |
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293 | #define ENABLE_POINT_RASTER_RULE (1<<15) |
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294 | #define OGL_POINT_RASTER_RULE (1<<13) |
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295 | #define ENABLE_TEXKILL_3D_4D (1<<10) |
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296 | #define TEXKILL_3D (0<<9) |
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297 | #define TEXKILL_4D (1<<9) |
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298 | #define ENABLE_LINE_STRIP_PROVOKE_VRTX (1<<8) |
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299 | #define ENABLE_TRI_FAN_PROVOKE_VRTX (1<<5) |
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300 | #define LINE_STRIP_PROVOKE_VRTX_MASK (3 << 6) |
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301 | #define LINE_STRIP_PROVOKE_VRTX(x) ((x)<<6) |
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302 | #define TRI_FAN_PROVOKE_VRTX_MASK (3 << 3) |
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303 | #define TRI_FAN_PROVOKE_VRTX(x) ((x)<<3) |
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304 | |||
305 | /* _3DSTATE_SCISSOR_ENABLE, p256 */ |
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306 | #define _3DSTATE_SCISSOR_ENABLE_CMD (CMD_3D|(0x1c<<24)|(0x10<<19)) |
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307 | #define ENABLE_SCISSOR_RECT ((1<<1) | 1) |
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308 | #define DISABLE_SCISSOR_RECT (1<<1) |
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309 | |||
310 | /* _3DSTATE_SCISSOR_RECTANGLE_0, p257 */ |
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311 | #define _3DSTATE_SCISSOR_RECT_0_CMD (CMD_3D|(0x1d<<24)|(0x81<<16)|1) |
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312 | /* Dword 1 */ |
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313 | #define SCISSOR_RECT_0_YMIN(x) ((x)<<16) |
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314 | #define SCISSOR_RECT_0_XMIN(x) (x) |
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315 | /* Dword 2 */ |
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316 | #define SCISSOR_RECT_0_YMAX(x) ((x)<<16) |
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317 | #define SCISSOR_RECT_0_XMAX(x) (x) |
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318 | |||
319 | /* Helper macros for blend factors |
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320 | */ |
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321 | #define DST_BLND_FACT(f) ((f)< |
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322 | #define SRC_BLND_FACT(f) ((f)< |
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323 | #define DST_ABLND_FACT(f) ((f)< |
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324 | #define SRC_ABLND_FACT(f) ((f)< |
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325 | |||
326 | |||
327 | |||
328 | |||
329 | /* 3DSTATE_MAP_DEINTERLACER_PARAMETERS */ |
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330 | |||
331 | /* 3DSTATE_MAP_PALETTE_LOAD_32, p206 */ |
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332 | #define _3DSTATE_MAP_PALETTE_LOAD_32 (CMD_3D|(0x1d<<24)|(0x8f<<16)) |
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333 | /* subsequent dwords up to length (max 16) are ARGB8888 color values */ |
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334 | |||
335 | /* _3DSTATE_MODES_4, p218 */ |
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336 | #define _3DSTATE_MODES_4_CMD (CMD_3D|(0x0d<<24)) |
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337 | #define ENABLE_LOGIC_OP_FUNC (1<<23) |
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338 | #define LOGIC_OP_FUNC(x) ((x)<<18) |
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339 | #define LOGICOP_MASK (0xf<<18) |
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340 | #define MODE4_ENABLE_STENCIL_TEST_MASK ((1<<17)|(0xff00)) |
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341 | #define ENABLE_STENCIL_TEST_MASK (1<<17) |
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342 | #define STENCIL_TEST_MASK(x) (((x)&0xff)<<8) |
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343 | #define MODE4_ENABLE_STENCIL_WRITE_MASK ((1<<16)|(0x00ff)) |
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344 | #define ENABLE_STENCIL_WRITE_MASK (1<<16) |
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345 | #define STENCIL_WRITE_MASK(x) ((x)&0xff) |
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346 | |||
347 | /* _3DSTATE_MODES_5, p220 */ |
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348 | #define _3DSTATE_MODES_5_CMD (CMD_3D|(0x0c<<24)) |
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349 | #define PIPELINE_FLUSH_RENDER_CACHE (1<<18) |
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350 | #define PIPELINE_FLUSH_TEXTURE_CACHE (1<<16) |
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351 | |||
352 | |||
353 | /* p221 */ |
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354 | #define _3DSTATE_PIXEL_SHADER_CONSTANTS (CMD_3D|(0x1d<<24)|(0x6<<16)) |
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355 | #define PS1_REG(n) (1<<(n)) |
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356 | #define PS2_CONST_X(n) (n) |
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357 | #define PS3_CONST_Y(n) (n) |
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358 | #define PS4_CONST_Z(n) (n) |
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359 | #define PS5_CONST_W(n) (n) |
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360 | |||
361 | /* p222 */ |
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362 | |||
363 | |||
364 | /* Each instruction is 3 dwords long, though most don't require all |
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365 | * this space. Maximum of 123 instructions. Smaller maxes per insn |
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366 | * type. |
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367 | */ |
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368 | #define _3DSTATE_PIXEL_SHADER_PROGRAM (CMD_3D|(0x1d<<24)|(0x5<<16)) |
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369 | |||
370 | #define REG_TYPE_R 0 /* temporary regs, no need to |
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371 | * dcl, must be written before |
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372 | * read -- Preserved between |
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373 | * phases. |
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374 | */ |
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375 | #define REG_TYPE_T 1 /* Interpolated values, must be |
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376 | * dcl'ed before use. |
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377 | * |
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378 | * 0..7: texture coord, |
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379 | * 8: diffuse spec, |
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380 | * 9: specular color, |
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381 | * 10: fog parameter in w. |
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382 | */ |
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383 | #define REG_TYPE_CONST 2 /* Restriction: only one const |
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384 | * can be referenced per |
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385 | * instruction, though it may be |
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386 | * selected for multiple inputs. |
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387 | * Constants not initialized |
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388 | * default to zero. |
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389 | */ |
||
390 | #define REG_TYPE_S 3 /* sampler */ |
||
391 | #define REG_TYPE_OC 4 /* output color (rgba) */ |
||
392 | #define REG_TYPE_OD 5 /* output depth (w), xyz are |
||
393 | * temporaries. If not written, |
||
394 | * interpolated depth is used? |
||
395 | */ |
||
396 | #define REG_TYPE_U 6 /* unpreserved temporaries */ |
||
397 | #define REG_TYPE_MASK 0x7 |
||
398 | #define REG_NR_MASK 0xf |
||
399 | |||
400 | |||
401 | /* REG_TYPE_T: |
||
402 | */ |
||
403 | #define T_TEX0 0 |
||
404 | #define T_TEX1 1 |
||
405 | #define T_TEX2 2 |
||
406 | #define T_TEX3 3 |
||
407 | #define T_TEX4 4 |
||
408 | #define T_TEX5 5 |
||
409 | #define T_TEX6 6 |
||
410 | #define T_TEX7 7 |
||
411 | #define T_DIFFUSE 8 |
||
412 | #define T_SPECULAR 9 |
||
413 | #define T_FOG_W 10 /* interpolated fog is in W coord */ |
||
414 | |||
415 | /* Arithmetic instructions */ |
||
416 | |||
417 | /* .replicate_swizzle == selection and replication of a particular |
||
418 | * scalar channel, ie., .xxxx, .yyyy, .zzzz or .wwww |
||
419 | */ |
||
420 | #define A0_NOP (0x0<<24) /* no operation */ |
||
421 | #define A0_ADD (0x1<<24) /* dst = src0 + src1 */ |
||
422 | #define A0_MOV (0x2<<24) /* dst = src0 */ |
||
423 | #define A0_MUL (0x3<<24) /* dst = src0 * src1 */ |
||
424 | #define A0_MAD (0x4<<24) /* dst = src0 * src1 + src2 */ |
||
425 | #define A0_DP2ADD (0x5<<24) /* dst.xyzw = src0.xy dot src1.xy + src2.replicate_swizzle */ |
||
426 | #define A0_DP3 (0x6<<24) /* dst.xyzw = src0.xyz dot src1.xyz */ |
||
427 | #define A0_DP4 (0x7<<24) /* dst.xyzw = src0.xyzw dot src1.xyzw */ |
||
428 | #define A0_FRC (0x8<<24) /* dst = src0 - floor(src0) */ |
||
429 | #define A0_RCP (0x9<<24) /* dst.xyzw = 1/(src0.replicate_swizzle) */ |
||
430 | #define A0_RSQ (0xa<<24) /* dst.xyzw = 1/(sqrt(abs(src0.replicate_swizzle))) */ |
||
431 | #define A0_EXP (0xb<<24) /* dst.xyzw = exp2(src0.replicate_swizzle) */ |
||
432 | #define A0_LOG (0xc<<24) /* dst.xyzw = log2(abs(src0.replicate_swizzle)) */ |
||
433 | #define A0_CMP (0xd<<24) /* dst = (src0 >= 0.0) ? src1 : src2 */ |
||
434 | #define A0_MIN (0xe<<24) /* dst = (src0 < src1) ? src0 : src1 */ |
||
435 | #define A0_MAX (0xf<<24) /* dst = (src0 >= src1) ? src0 : src1 */ |
||
436 | #define A0_FLR (0x10<<24) /* dst = floor(src0) */ |
||
437 | #define A0_MOD (0x11<<24) /* dst = src0 fmod 1.0 */ |
||
438 | #define A0_TRC (0x12<<24) /* dst = int(src0) */ |
||
439 | #define A0_SGE (0x13<<24) /* dst = src0 >= src1 ? 1.0 : 0.0 */ |
||
440 | #define A0_SLT (0x14<<24) /* dst = src0 < src1 ? 1.0 : 0.0 */ |
||
441 | #define A0_DEST_SATURATE (1<<22) |
||
442 | #define A0_DEST_TYPE_SHIFT 19 |
||
443 | /* Allow: R, OC, OD, U */ |
||
444 | #define A0_DEST_NR_SHIFT 14 |
||
445 | /* Allow R: 0..15, OC,OD: 0..0, U: 0..2 */ |
||
446 | #define A0_DEST_CHANNEL_X (1<<10) |
||
447 | #define A0_DEST_CHANNEL_Y (2<<10) |
||
448 | #define A0_DEST_CHANNEL_Z (4<<10) |
||
449 | #define A0_DEST_CHANNEL_W (8<<10) |
||
450 | #define A0_DEST_CHANNEL_ALL (0xf<<10) |
||
451 | #define A0_DEST_CHANNEL_SHIFT 10 |
||
452 | #define A0_SRC0_TYPE_SHIFT 7 |
||
453 | #define A0_SRC0_NR_SHIFT 2 |
||
454 | |||
455 | #define A0_DEST_CHANNEL_XY (A0_DEST_CHANNEL_X|A0_DEST_CHANNEL_Y) |
||
456 | #define A0_DEST_CHANNEL_XYZ (A0_DEST_CHANNEL_XY|A0_DEST_CHANNEL_Z) |
||
457 | |||
458 | |||
459 | #define SRC_X 0 |
||
460 | #define SRC_Y 1 |
||
461 | #define SRC_Z 2 |
||
462 | #define SRC_W 3 |
||
463 | #define SRC_ZERO 4 |
||
464 | #define SRC_ONE 5 |
||
465 | |||
466 | #define A1_SRC0_CHANNEL_X_NEGATE (1<<31) |
||
467 | #define A1_SRC0_CHANNEL_X_SHIFT 28 |
||
468 | #define A1_SRC0_CHANNEL_Y_NEGATE (1<<27) |
||
469 | #define A1_SRC0_CHANNEL_Y_SHIFT 24 |
||
470 | #define A1_SRC0_CHANNEL_Z_NEGATE (1<<23) |
||
471 | #define A1_SRC0_CHANNEL_Z_SHIFT 20 |
||
472 | #define A1_SRC0_CHANNEL_W_NEGATE (1<<19) |
||
473 | #define A1_SRC0_CHANNEL_W_SHIFT 16 |
||
474 | #define A1_SRC1_TYPE_SHIFT 13 |
||
475 | #define A1_SRC1_NR_SHIFT 8 |
||
476 | #define A1_SRC1_CHANNEL_X_NEGATE (1<<7) |
||
477 | #define A1_SRC1_CHANNEL_X_SHIFT 4 |
||
478 | #define A1_SRC1_CHANNEL_Y_NEGATE (1<<3) |
||
479 | #define A1_SRC1_CHANNEL_Y_SHIFT 0 |
||
480 | |||
481 | #define A2_SRC1_CHANNEL_Z_NEGATE (1<<31) |
||
482 | #define A2_SRC1_CHANNEL_Z_SHIFT 28 |
||
483 | #define A2_SRC1_CHANNEL_W_NEGATE (1<<27) |
||
484 | #define A2_SRC1_CHANNEL_W_SHIFT 24 |
||
485 | #define A2_SRC2_TYPE_SHIFT 21 |
||
486 | #define A2_SRC2_NR_SHIFT 16 |
||
487 | #define A2_SRC2_CHANNEL_X_NEGATE (1<<15) |
||
488 | #define A2_SRC2_CHANNEL_X_SHIFT 12 |
||
489 | #define A2_SRC2_CHANNEL_Y_NEGATE (1<<11) |
||
490 | #define A2_SRC2_CHANNEL_Y_SHIFT 8 |
||
491 | #define A2_SRC2_CHANNEL_Z_NEGATE (1<<7) |
||
492 | #define A2_SRC2_CHANNEL_Z_SHIFT 4 |
||
493 | #define A2_SRC2_CHANNEL_W_NEGATE (1<<3) |
||
494 | #define A2_SRC2_CHANNEL_W_SHIFT 0 |
||
495 | |||
496 | |||
497 | |||
498 | /* Texture instructions */ |
||
499 | #define T0_TEXLD (0x15<<24) /* Sample texture using predeclared |
||
500 | * sampler and address, and output |
||
501 | * filtered texel data to destination |
||
502 | * register */ |
||
503 | #define T0_TEXLDP (0x16<<24) /* Same as texld but performs a |
||
504 | * perspective divide of the texture |
||
505 | * coordinate .xyz values by .w before |
||
506 | * sampling. */ |
||
507 | #define T0_TEXLDB (0x17<<24) /* Same as texld but biases the |
||
508 | * computed LOD by w. Only S4.6 two's |
||
509 | * comp is used. This implies that a |
||
510 | * float to fixed conversion is |
||
511 | * done. */ |
||
512 | #define T0_TEXKILL (0x18<<24) /* Does not perform a sampling |
||
513 | * operation. Simply kills the pixel |
||
514 | * if any channel of the address |
||
515 | * register is < 0.0. */ |
||
516 | #define T0_DEST_TYPE_SHIFT 19 |
||
517 | /* Allow: R, OC, OD, U */ |
||
518 | /* Note: U (unpreserved) regs do not retain their values between |
||
519 | * phases (cannot be used for feedback) |
||
520 | * |
||
521 | * Note: oC and OD registers can only be used as the destination of a |
||
522 | * texture instruction once per phase (this is an implementation |
||
523 | * restriction). |
||
524 | */ |
||
525 | #define T0_DEST_NR_SHIFT 14 |
||
526 | /* Allow R: 0..15, OC,OD: 0..0, U: 0..2 */ |
||
527 | #define T0_SAMPLER_NR_SHIFT 0 /* This field ignored for TEXKILL */ |
||
528 | #define T0_SAMPLER_NR_MASK (0xf<<0) |
||
529 | |||
530 | #define T1_ADDRESS_REG_TYPE_SHIFT 24 /* Reg to use as texture coord */ |
||
531 | /* Allow R, T, OC, OD -- R, OC, OD are 'dependent' reads, new program phase */ |
||
532 | #define T1_ADDRESS_REG_NR_SHIFT 17 |
||
533 | #define T2_MBZ 0 |
||
534 | |||
535 | /* Declaration instructions */ |
||
536 | #define D0_DCL (0x19<<24) /* Declare a t (interpolated attrib) |
||
537 | * register or an s (sampler) |
||
538 | * register. */ |
||
539 | #define D0_SAMPLE_TYPE_SHIFT 22 |
||
540 | #define D0_SAMPLE_TYPE_2D (0x0<<22) |
||
541 | #define D0_SAMPLE_TYPE_CUBE (0x1<<22) |
||
542 | #define D0_SAMPLE_TYPE_VOLUME (0x2<<22) |
||
543 | #define D0_SAMPLE_TYPE_MASK (0x3<<22) |
||
544 | |||
545 | #define D0_TYPE_SHIFT 19 |
||
546 | /* Allow: T, S */ |
||
547 | #define D0_NR_SHIFT 14 |
||
548 | /* Allow T: 0..10, S: 0..15 */ |
||
549 | #define D0_CHANNEL_X (1<<10) |
||
550 | #define D0_CHANNEL_Y (2<<10) |
||
551 | #define D0_CHANNEL_Z (4<<10) |
||
552 | #define D0_CHANNEL_W (8<<10) |
||
553 | #define D0_CHANNEL_ALL (0xf<<10) |
||
554 | #define D0_CHANNEL_NONE (0<<10) |
||
555 | |||
556 | #define D0_CHANNEL_XY (D0_CHANNEL_X|D0_CHANNEL_Y) |
||
557 | #define D0_CHANNEL_XYZ (D0_CHANNEL_XY|D0_CHANNEL_Z) |
||
558 | |||
559 | /* I915 Errata: Do not allow (xz), (xw), (xzw) combinations for diffuse |
||
560 | * or specular declarations. |
||
561 | * |
||
562 | * For T dcls, only allow: (x), (xy), (xyz), (w), (xyzw) |
||
563 | * |
||
564 | * Must be zero for S (sampler) dcls |
||
565 | */ |
||
566 | #define D1_MBZ 0 |
||
567 | #define D2_MBZ 0 |
||
568 | |||
569 | |||
570 | |||
571 | /* p207 */ |
||
572 | #define _3DSTATE_MAP_STATE (CMD_3D|(0x1d<<24)|(0x0<<16)) |
||
573 | |||
574 | #define MS1_MAPMASK_SHIFT 0 |
||
575 | #define MS1_MAPMASK_MASK (0x8fff<<0) |
||
576 | |||
577 | #define MS2_UNTRUSTED_SURFACE (1<<31) |
||
578 | #define MS2_ADDRESS_MASK 0xfffffffc |
||
579 | #define MS2_VERTICAL_LINE_STRIDE (1<<1) |
||
580 | #define MS2_VERTICAL_OFFSET (1<<1) |
||
581 | |||
582 | #define MS3_HEIGHT_SHIFT 21 |
||
583 | #define MS3_WIDTH_SHIFT 10 |
||
584 | #define MS3_PALETTE_SELECT (1<<9) |
||
585 | #define MS3_MAPSURF_FORMAT_SHIFT 7 |
||
586 | #define MS3_MAPSURF_FORMAT_MASK (0x7<<7) |
||
587 | #define MAPSURF_8BIT (1<<7) |
||
588 | #define MAPSURF_16BIT (2<<7) |
||
589 | #define MAPSURF_32BIT (3<<7) |
||
590 | #define MAPSURF_422 (5<<7) |
||
591 | #define MAPSURF_COMPRESSED (6<<7) |
||
592 | #define MAPSURF_4BIT_INDEXED (7<<7) |
||
593 | #define MS3_MT_FORMAT_MASK (0x7 << 3) |
||
594 | #define MS3_MT_FORMAT_SHIFT 3 |
||
595 | #define MT_4BIT_IDX_ARGB8888 (7<<3) /* SURFACE_4BIT_INDEXED */ |
||
596 | #define MT_8BIT_I8 (0<<3) /* SURFACE_8BIT */ |
||
597 | #define MT_8BIT_L8 (1<<3) |
||
598 | #define MT_8BIT_A8 (4<<3) |
||
599 | #define MT_8BIT_MONO8 (5<<3) |
||
600 | #define MT_16BIT_RGB565 (0<<3) /* SURFACE_16BIT */ |
||
601 | #define MT_16BIT_ARGB1555 (1<<3) |
||
602 | #define MT_16BIT_ARGB4444 (2<<3) |
||
603 | #define MT_16BIT_AY88 (3<<3) |
||
604 | #define MT_16BIT_88DVDU (5<<3) |
||
605 | #define MT_16BIT_BUMP_655LDVDU (6<<3) |
||
606 | #define MT_16BIT_I16 (7<<3) |
||
607 | #define MT_16BIT_L16 (8<<3) |
||
608 | #define MT_16BIT_A16 (9<<3) |
||
609 | #define MT_32BIT_ARGB8888 (0<<3) /* SURFACE_32BIT */ |
||
610 | #define MT_32BIT_ABGR8888 (1<<3) |
||
611 | #define MT_32BIT_XRGB8888 (2<<3) |
||
612 | #define MT_32BIT_XBGR8888 (3<<3) |
||
613 | #define MT_32BIT_QWVU8888 (4<<3) |
||
614 | #define MT_32BIT_AXVU8888 (5<<3) |
||
615 | #define MT_32BIT_LXVU8888 (6<<3) |
||
616 | #define MT_32BIT_XLVU8888 (7<<3) |
||
617 | #define MT_32BIT_ARGB2101010 (8<<3) |
||
618 | #define MT_32BIT_ABGR2101010 (9<<3) |
||
619 | #define MT_32BIT_AWVU2101010 (0xA<<3) |
||
620 | #define MT_32BIT_GR1616 (0xB<<3) |
||
621 | #define MT_32BIT_VU1616 (0xC<<3) |
||
622 | #define MT_32BIT_x8I24 (0xD<<3) |
||
623 | #define MT_32BIT_x8L24 (0xE<<3) |
||
624 | #define MT_32BIT_x8A24 (0xF<<3) |
||
625 | #define MT_422_YCRCB_SWAPY (0<<3) /* SURFACE_422 */ |
||
626 | #define MT_422_YCRCB_NORMAL (1<<3) |
||
627 | #define MT_422_YCRCB_SWAPUV (2<<3) |
||
628 | #define MT_422_YCRCB_SWAPUVY (3<<3) |
||
629 | #define MT_COMPRESS_DXT1 (0<<3) /* SURFACE_COMPRESSED */ |
||
630 | #define MT_COMPRESS_DXT2_3 (1<<3) |
||
631 | #define MT_COMPRESS_DXT4_5 (2<<3) |
||
632 | #define MT_COMPRESS_FXT1 (3<<3) |
||
633 | #define MT_COMPRESS_DXT1_RGB (4<<3) |
||
634 | #define MS3_USE_FENCE_REGS (1<<2) |
||
635 | #define MS3_TILED_SURFACE (1<<1) |
||
636 | #define MS3_TILE_WALK (1<<0) |
||
637 | |||
638 | #define MS4_PITCH_SHIFT 21 |
||
639 | #define MS4_CUBE_FACE_ENA_NEGX (1<<20) |
||
640 | #define MS4_CUBE_FACE_ENA_POSX (1<<19) |
||
641 | #define MS4_CUBE_FACE_ENA_NEGY (1<<18) |
||
642 | #define MS4_CUBE_FACE_ENA_POSY (1<<17) |
||
643 | #define MS4_CUBE_FACE_ENA_NEGZ (1<<16) |
||
644 | #define MS4_CUBE_FACE_ENA_POSZ (1<<15) |
||
645 | #define MS4_CUBE_FACE_ENA_MASK (0x3f<<15) |
||
646 | #define MS4_MAX_LOD_SHIFT 9 |
||
647 | #define MS4_MAX_LOD_MASK (0x3f<<9) |
||
648 | #define MS4_MIP_LAYOUT_LEGACY (0<<8) |
||
649 | #define MS4_MIP_LAYOUT_BELOW_LPT (0<<8) |
||
650 | #define MS4_MIP_LAYOUT_RIGHT_LPT (1<<8) |
||
651 | #define MS4_VOLUME_DEPTH_SHIFT 0 |
||
652 | #define MS4_VOLUME_DEPTH_MASK (0xff<<0) |
||
653 | |||
654 | /* p244 */ |
||
655 | #define _3DSTATE_SAMPLER_STATE (CMD_3D|(0x1d<<24)|(0x1<<16)) |
||
656 | |||
657 | #define SS1_MAPMASK_SHIFT 0 |
||
658 | #define SS1_MAPMASK_MASK (0x8fff<<0) |
||
659 | |||
660 | #define SS2_REVERSE_GAMMA_ENABLE (1<<31) |
||
661 | #define SS2_PACKED_TO_PLANAR_ENABLE (1<<30) |
||
662 | #define SS2_COLORSPACE_CONVERSION (1<<29) |
||
663 | #define SS2_CHROMAKEY_SHIFT 27 |
||
664 | #define SS2_BASE_MIP_LEVEL_SHIFT 22 |
||
665 | #define SS2_BASE_MIP_LEVEL_MASK (0x1f<<22) |
||
666 | #define SS2_MIP_FILTER_SHIFT 20 |
||
667 | #define SS2_MIP_FILTER_MASK (0x3<<20) |
||
668 | #define MIPFILTER_NONE 0 |
||
669 | #define MIPFILTER_NEAREST 1 |
||
670 | #define MIPFILTER_LINEAR 3 |
||
671 | #define SS2_MAG_FILTER_SHIFT 17 |
||
672 | #define SS2_MAG_FILTER_MASK (0x7<<17) |
||
673 | #define FILTER_NEAREST 0 |
||
674 | #define FILTER_LINEAR 1 |
||
675 | #define FILTER_ANISOTROPIC 2 |
||
676 | #define FILTER_4X4_1 3 |
||
677 | #define FILTER_4X4_2 4 |
||
678 | #define FILTER_4X4_FLAT 5 |
||
679 | #define FILTER_6X5_MONO 6 /* XXX - check */ |
||
680 | #define SS2_MIN_FILTER_SHIFT 14 |
||
681 | #define SS2_MIN_FILTER_MASK (0x7<<14) |
||
682 | #define SS2_LOD_BIAS_SHIFT 5 |
||
683 | #define SS2_LOD_BIAS_ONE (0x10<<5) |
||
684 | #define SS2_LOD_BIAS_MASK (0x1ff<<5) |
||
685 | /* Shadow requires: |
||
686 | * MT_X8{I,L,A}24 or MT_{I,L,A}16 texture format |
||
687 | * FILTER_4X4_x MIN and MAG filters |
||
688 | */ |
||
689 | #define SS2_SHADOW_ENABLE (1<<4) |
||
690 | #define SS2_MAX_ANISO_MASK (1<<3) |
||
691 | #define SS2_MAX_ANISO_2 (0<<3) |
||
692 | #define SS2_MAX_ANISO_4 (1<<3) |
||
693 | #define SS2_SHADOW_FUNC_SHIFT 0 |
||
694 | #define SS2_SHADOW_FUNC_MASK (0x7<<0) |
||
695 | /* SS2_SHADOW_FUNC values: see COMPAREFUNC_* */ |
||
696 | |||
697 | #define SS3_MIN_LOD_SHIFT 24 |
||
698 | #define SS3_MIN_LOD_ONE (0x10<<24) |
||
699 | #define SS3_MIN_LOD_MASK (0xff<<24) |
||
700 | #define SS3_KILL_PIXEL_ENABLE (1<<17) |
||
701 | #define SS3_TCX_ADDR_MODE_SHIFT 12 |
||
702 | #define SS3_TCX_ADDR_MODE_MASK (0x7<<12) |
||
703 | #define TEXCOORDMODE_WRAP 0 |
||
704 | #define TEXCOORDMODE_MIRROR 1 |
||
705 | #define TEXCOORDMODE_CLAMP_EDGE 2 |
||
706 | #define TEXCOORDMODE_CUBE 3 |
||
707 | #define TEXCOORDMODE_CLAMP_BORDER 4 |
||
708 | #define TEXCOORDMODE_MIRROR_ONCE 5 |
||
709 | #define SS3_TCY_ADDR_MODE_SHIFT 9 |
||
710 | #define SS3_TCY_ADDR_MODE_MASK (0x7<<9) |
||
711 | #define SS3_TCZ_ADDR_MODE_SHIFT 6 |
||
712 | #define SS3_TCZ_ADDR_MODE_MASK (0x7<<6) |
||
713 | #define SS3_NORMALIZED_COORDS (1<<5) |
||
714 | #define SS3_TEXTUREMAP_INDEX_SHIFT 1 |
||
715 | #define SS3_TEXTUREMAP_INDEX_MASK (0xf<<1) |
||
716 | #define SS3_DEINTERLACER_ENABLE (1<<0) |
||
717 | |||
718 | #define SS4_BORDER_COLOR_MASK (~0) |
||
719 | |||
720 | /* 3DSTATE_SPAN_STIPPLE, p258 |
||
721 | */ |
||
722 | #define _3DSTATE_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) |
||
723 | #define ST1_ENABLE (1<<16) |
||
724 | #define ST1_MASK (0xffff) |
||
725 | |||
726 | #define _3DSTATE_DEFAULT_Z ((0x3<<29)|(0x1d<<24)|(0x98<<16)) |
||
727 | #define _3DSTATE_DEFAULT_DIFFUSE ((0x3<<29)|(0x1d<<24)|(0x99<<16)) |
||
728 | #define _3DSTATE_DEFAULT_SPECULAR ((0x3<<29)|(0x1d<<24)|(0x9a<<16)) |
||
729 | |||
730 | #endif16)) |