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| Rev | Author | Line No. | Line |
|---|---|---|---|
| 4358 | Serge | 1 | /* |
| 2 | * Copyright (c) 2013 Rob Clark |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice (including the next |
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| 12 | * paragraph) shall be included in all copies or substantial portions of the |
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| 13 | * Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
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| 20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
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| 21 | * SOFTWARE. |
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| 22 | */ |
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| 23 | |||
| 24 | #include "ir-a3xx.h" |
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| 25 | |||
| 26 | #include |
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| 27 | #include |
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| 28 | #include |
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| 29 | #include |
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| 30 | #include |
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| 31 | #include |
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| 32 | |||
| 33 | #include "freedreno_util.h" |
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| 34 | #include "instr-a3xx.h" |
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| 35 | |||
| 36 | /* simple allocator to carve allocations out of an up-front allocated heap, |
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| 37 | * so that we can free everything easily in one shot. |
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| 38 | */ |
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| 39 | static void * ir3_alloc(struct ir3_shader *shader, int sz) |
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| 40 | { |
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| 41 | void *ptr = &shader->heap[shader->heap_idx]; |
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| 42 | shader->heap_idx += align(sz, 4); |
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| 43 | return ptr; |
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| 44 | } |
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| 45 | |||
| 46 | struct ir3_shader * ir3_shader_create(void) |
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| 47 | { |
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| 48 | return calloc(1, sizeof(struct ir3_shader)); |
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| 49 | } |
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| 50 | |||
| 51 | void ir3_shader_destroy(struct ir3_shader *shader) |
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| 52 | { |
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| 53 | free(shader); |
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| 54 | } |
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| 55 | |||
| 56 | #define iassert(cond) do { \ |
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| 57 | if (!(cond)) { \ |
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| 58 | assert(cond); \ |
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| 59 | return -1; \ |
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| 60 | } } while (0) |
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| 61 | |||
| 62 | static uint32_t reg(struct ir3_register *reg, struct ir3_shader_info *info, |
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| 63 | uint32_t repeat, uint32_t valid_flags) |
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| 64 | { |
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| 65 | reg_t val = { .dummy32 = 0 }; |
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| 66 | |||
| 67 | assert(!(reg->flags & ~valid_flags)); |
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| 68 | |||
| 69 | if (!(reg->flags & IR3_REG_R)) |
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| 70 | repeat = 0; |
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| 71 | |||
| 72 | if (reg->flags & IR3_REG_IMMED) { |
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| 73 | val.iim_val = reg->iim_val; |
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| 74 | } else { |
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| 75 | int8_t max = (reg->num + repeat) >> 2; |
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| 76 | |||
| 77 | val.comp = reg->num & 0x3; |
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| 78 | val.num = reg->num >> 2; |
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| 79 | |||
| 80 | if (reg->flags & IR3_REG_CONST) { |
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| 81 | info->max_const = MAX2(info->max_const, max); |
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| 82 | } else if ((max != REG_A0) && (max != REG_P0)) { |
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| 83 | if (reg->flags & IR3_REG_HALF) { |
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| 84 | info->max_half_reg = MAX2(info->max_half_reg, max); |
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| 85 | } else { |
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| 86 | info->max_reg = MAX2(info->max_reg, max); |
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| 87 | } |
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| 88 | } |
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| 89 | } |
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| 90 | |||
| 91 | return val.dummy32; |
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| 92 | } |
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| 93 | |||
| 94 | static int emit_cat0(struct ir3_instruction *instr, void *ptr, |
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| 95 | struct ir3_shader_info *info) |
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| 96 | { |
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| 97 | instr_cat0_t *cat0 = ptr; |
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| 98 | |||
| 99 | cat0->immed = instr->cat0.immed; |
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| 100 | cat0->repeat = instr->repeat; |
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| 101 | cat0->ss = !!(instr->flags & IR3_INSTR_SS); |
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| 102 | cat0->inv = instr->cat0.inv; |
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| 103 | cat0->comp = instr->cat0.comp; |
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| 104 | cat0->opc = instr->opc; |
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| 105 | cat0->jmp_tgt = !!(instr->flags & IR3_INSTR_JP); |
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| 106 | cat0->sync = !!(instr->flags & IR3_INSTR_SY); |
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| 107 | cat0->opc_cat = 0; |
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| 108 | |||
| 109 | return 0; |
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| 110 | } |
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| 111 | |||
| 112 | static uint32_t type_flags(type_t type) |
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| 113 | { |
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| 114 | return (type_size(type) == 32) ? 0 : IR3_REG_HALF; |
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| 115 | } |
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| 116 | |||
| 117 | static int emit_cat1(struct ir3_instruction *instr, void *ptr, |
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| 118 | struct ir3_shader_info *info) |
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| 119 | { |
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| 120 | struct ir3_register *dst = instr->regs[0]; |
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| 121 | struct ir3_register *src = instr->regs[1]; |
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| 122 | instr_cat1_t *cat1 = ptr; |
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| 123 | |||
| 124 | iassert(instr->regs_count == 2); |
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| 125 | iassert(!((dst->flags ^ type_flags(instr->cat1.dst_type)) & IR3_REG_HALF)); |
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| 126 | iassert((src->flags & IR3_REG_IMMED) || |
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| 127 | !((src->flags ^ type_flags(instr->cat1.src_type)) & IR3_REG_HALF)); |
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| 128 | |||
| 129 | if (src->flags & IR3_REG_IMMED) { |
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| 130 | cat1->iim_val = src->iim_val; |
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| 131 | cat1->src_im = 1; |
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| 132 | } else if (src->flags & IR3_REG_RELATIV) { |
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| 133 | cat1->off = src->offset; |
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| 134 | cat1->src_rel = 1; |
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| 135 | cat1->must_be_3 = 3; |
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| 136 | } else { |
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| 137 | cat1->src = reg(src, info, instr->repeat, |
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| 138 | IR3_REG_IMMED | IR3_REG_RELATIV | |
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| 139 | IR3_REG_R | IR3_REG_CONST | IR3_REG_HALF); |
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| 140 | } |
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| 141 | |||
| 142 | cat1->dst = reg(dst, info, instr->repeat, |
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| 143 | IR3_REG_RELATIV | IR3_REG_EVEN | |
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| 144 | IR3_REG_R | IR3_REG_POS_INF | IR3_REG_HALF); |
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| 145 | cat1->repeat = instr->repeat; |
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| 146 | cat1->src_r = !!(src->flags & IR3_REG_R); |
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| 147 | cat1->ss = !!(instr->flags & IR3_INSTR_SS); |
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| 148 | cat1->dst_type = instr->cat1.dst_type; |
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| 149 | cat1->dst_rel = !!(dst->flags & IR3_REG_RELATIV); |
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| 150 | cat1->src_type = instr->cat1.src_type; |
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| 151 | cat1->src_c = !!(src->flags & IR3_REG_CONST); |
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| 152 | cat1->even = !!(dst->flags & IR3_REG_EVEN); |
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| 153 | cat1->pos_inf = !!(dst->flags & IR3_REG_POS_INF); |
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| 154 | cat1->jmp_tgt = !!(instr->flags & IR3_INSTR_JP); |
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| 155 | cat1->sync = !!(instr->flags & IR3_INSTR_SY); |
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| 156 | cat1->opc_cat = 1; |
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| 157 | |||
| 158 | return 0; |
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| 159 | } |
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| 160 | |||
| 161 | static int emit_cat2(struct ir3_instruction *instr, void *ptr, |
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| 162 | struct ir3_shader_info *info) |
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| 163 | { |
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| 164 | struct ir3_register *dst = instr->regs[0]; |
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| 165 | struct ir3_register *src1 = instr->regs[1]; |
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| 166 | struct ir3_register *src2 = instr->regs[2]; |
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| 167 | instr_cat2_t *cat2 = ptr; |
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| 168 | |||
| 169 | iassert((instr->regs_count == 2) || (instr->regs_count == 3)); |
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| 170 | |||
| 171 | cat2->src1 = reg(src1, info, instr->repeat, |
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| 172 | IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_IMMED | |
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| 173 | IR3_REG_NEGATE | IR3_REG_ABS | IR3_REG_R | IR3_REG_HALF); |
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| 174 | cat2->src1_rel = !!(src1->flags & IR3_REG_RELATIV); |
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| 175 | cat2->src1_c = !!(src1->flags & IR3_REG_CONST); |
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| 176 | cat2->src1_im = !!(src1->flags & IR3_REG_IMMED); |
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| 177 | cat2->src1_neg = !!(src1->flags & IR3_REG_NEGATE); |
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| 178 | cat2->src1_abs = !!(src1->flags & IR3_REG_ABS); |
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| 179 | cat2->src1_r = !!(src1->flags & IR3_REG_R); |
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| 180 | |||
| 181 | if (src2) { |
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| 182 | iassert((src2->flags & IR3_REG_IMMED) || |
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| 183 | !((src1->flags ^ src2->flags) & IR3_REG_HALF)); |
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| 184 | cat2->src2 = reg(src2, info, instr->repeat, |
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| 185 | IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_IMMED | |
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| 186 | IR3_REG_NEGATE | IR3_REG_ABS | IR3_REG_R | IR3_REG_HALF); |
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| 187 | cat2->src2_rel = !!(src2->flags & IR3_REG_RELATIV); |
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| 188 | cat2->src2_c = !!(src2->flags & IR3_REG_CONST); |
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| 189 | cat2->src2_im = !!(src2->flags & IR3_REG_IMMED); |
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| 190 | cat2->src2_neg = !!(src2->flags & IR3_REG_NEGATE); |
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| 191 | cat2->src2_abs = !!(src2->flags & IR3_REG_ABS); |
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| 192 | cat2->src2_r = !!(src2->flags & IR3_REG_R); |
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| 193 | } |
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| 194 | |||
| 195 | cat2->dst = reg(dst, info, instr->repeat, |
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| 196 | IR3_REG_R | IR3_REG_EI | IR3_REG_HALF); |
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| 197 | cat2->repeat = instr->repeat; |
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| 198 | cat2->ss = !!(instr->flags & IR3_INSTR_SS); |
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| 199 | cat2->ul = !!(instr->flags & IR3_INSTR_UL); |
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| 200 | cat2->dst_half = !!((src1->flags ^ dst->flags) & IR3_REG_HALF); |
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| 201 | cat2->ei = !!(dst->flags & IR3_REG_EI); |
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| 202 | cat2->cond = instr->cat2.condition; |
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| 203 | cat2->full = ! (src1->flags & IR3_REG_HALF); |
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| 204 | cat2->opc = instr->opc; |
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| 205 | cat2->jmp_tgt = !!(instr->flags & IR3_INSTR_JP); |
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| 206 | cat2->sync = !!(instr->flags & IR3_INSTR_SY); |
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| 207 | cat2->opc_cat = 2; |
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| 208 | |||
| 209 | return 0; |
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| 210 | } |
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| 211 | |||
| 212 | static int emit_cat3(struct ir3_instruction *instr, void *ptr, |
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| 213 | struct ir3_shader_info *info) |
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| 214 | { |
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| 215 | struct ir3_register *dst = instr->regs[0]; |
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| 216 | struct ir3_register *src1 = instr->regs[1]; |
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| 217 | struct ir3_register *src2 = instr->regs[2]; |
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| 218 | struct ir3_register *src3 = instr->regs[3]; |
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| 219 | instr_cat3_t *cat3 = ptr; |
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| 220 | uint32_t src_flags = 0; |
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| 221 | |||
| 222 | switch (instr->opc) { |
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| 223 | case OPC_MAD_F16: |
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| 224 | case OPC_MAD_U16: |
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| 225 | case OPC_MAD_S16: |
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| 226 | case OPC_SEL_B16: |
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| 227 | case OPC_SEL_S16: |
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| 228 | case OPC_SEL_F16: |
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| 229 | case OPC_SAD_S16: |
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| 230 | case OPC_SAD_S32: // really?? |
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| 231 | src_flags |= IR3_REG_HALF; |
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| 232 | break; |
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| 233 | default: |
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| 234 | break; |
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| 235 | } |
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| 236 | |||
| 237 | iassert(instr->regs_count == 4); |
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| 238 | iassert(!((src1->flags ^ src_flags) & IR3_REG_HALF)); |
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| 239 | iassert(!((src2->flags ^ src_flags) & IR3_REG_HALF)); |
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| 240 | iassert(!((src3->flags ^ src_flags) & IR3_REG_HALF)); |
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| 241 | |||
| 242 | cat3->src1 = reg(src1, info, instr->repeat, |
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| 243 | IR3_REG_RELATIV | IR3_REG_CONST | |
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| 244 | IR3_REG_NEGATE | IR3_REG_R | IR3_REG_HALF); |
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| 245 | cat3->src1_rel = !!(src1->flags & IR3_REG_RELATIV); |
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| 246 | cat3->src1_c = !!(src1->flags & IR3_REG_CONST); |
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| 247 | cat3->src1_neg = !!(src1->flags & IR3_REG_NEGATE); |
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| 248 | cat3->src1_r = !!(src1->flags & IR3_REG_R); |
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| 249 | |||
| 250 | cat3->src2 = reg(src2, info, instr->repeat, |
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| 251 | IR3_REG_CONST | IR3_REG_NEGATE | |
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| 252 | IR3_REG_R | IR3_REG_HALF); |
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| 253 | cat3->src2_c = !!(src2->flags & IR3_REG_CONST); |
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| 254 | cat3->src2_neg = !!(src2->flags & IR3_REG_NEGATE); |
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| 255 | cat3->src2_r = !!(src2->flags & IR3_REG_R); |
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| 256 | |||
| 257 | cat3->src3 = reg(src3, info, instr->repeat, |
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| 258 | IR3_REG_RELATIV | IR3_REG_CONST | |
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| 259 | IR3_REG_NEGATE | IR3_REG_R | IR3_REG_HALF); |
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| 260 | cat3->src3_rel = !!(src3->flags & IR3_REG_RELATIV); |
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| 261 | cat3->src3_c = !!(src3->flags & IR3_REG_CONST); |
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| 262 | cat3->src3_neg = !!(src3->flags & IR3_REG_NEGATE); |
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| 263 | cat3->src3_r = !!(src3->flags & IR3_REG_R); |
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| 264 | |||
| 265 | cat3->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF); |
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| 266 | cat3->repeat = instr->repeat; |
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| 267 | cat3->ss = !!(instr->flags & IR3_INSTR_SS); |
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| 268 | cat3->ul = !!(instr->flags & IR3_INSTR_UL); |
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| 269 | cat3->dst_half = !!((src_flags ^ dst->flags) & IR3_REG_HALF); |
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| 270 | cat3->opc = instr->opc; |
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| 271 | cat3->jmp_tgt = !!(instr->flags & IR3_INSTR_JP); |
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| 272 | cat3->sync = !!(instr->flags & IR3_INSTR_SY); |
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| 273 | cat3->opc_cat = 3; |
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| 274 | |||
| 275 | return 0; |
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| 276 | } |
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| 277 | |||
| 278 | static int emit_cat4(struct ir3_instruction *instr, void *ptr, |
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| 279 | struct ir3_shader_info *info) |
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| 280 | { |
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| 281 | struct ir3_register *dst = instr->regs[0]; |
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| 282 | struct ir3_register *src = instr->regs[1]; |
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| 283 | instr_cat4_t *cat4 = ptr; |
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| 284 | |||
| 285 | iassert(instr->regs_count == 2); |
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| 286 | |||
| 287 | cat4->src = reg(src, info, instr->repeat, |
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| 288 | IR3_REG_RELATIV | IR3_REG_CONST | IR3_REG_IMMED | |
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| 289 | IR3_REG_NEGATE | IR3_REG_ABS | IR3_REG_R | |
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| 290 | IR3_REG_HALF); |
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| 291 | cat4->src_rel = !!(src->flags & IR3_REG_RELATIV); |
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| 292 | cat4->src_c = !!(src->flags & IR3_REG_CONST); |
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| 293 | cat4->src_im = !!(src->flags & IR3_REG_IMMED); |
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| 294 | cat4->src_neg = !!(src->flags & IR3_REG_NEGATE); |
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| 295 | cat4->src_abs = !!(src->flags & IR3_REG_ABS); |
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| 296 | cat4->src_r = !!(src->flags & IR3_REG_R); |
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| 297 | |||
| 298 | cat4->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF); |
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| 299 | cat4->repeat = instr->repeat; |
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| 300 | cat4->ss = !!(instr->flags & IR3_INSTR_SS); |
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| 301 | cat4->ul = !!(instr->flags & IR3_INSTR_UL); |
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| 302 | cat4->dst_half = !!((src->flags ^ dst->flags) & IR3_REG_HALF); |
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| 303 | cat4->full = ! (src->flags & IR3_REG_HALF); |
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| 304 | cat4->opc = instr->opc; |
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| 305 | cat4->jmp_tgt = !!(instr->flags & IR3_INSTR_JP); |
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| 306 | cat4->sync = !!(instr->flags & IR3_INSTR_SY); |
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| 307 | cat4->opc_cat = 4; |
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| 308 | |||
| 309 | return 0; |
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| 310 | } |
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| 311 | |||
| 312 | static int emit_cat5(struct ir3_instruction *instr, void *ptr, |
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| 313 | struct ir3_shader_info *info) |
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| 314 | { |
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| 315 | struct ir3_register *dst = instr->regs[0]; |
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| 316 | struct ir3_register *src1 = instr->regs[1]; |
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| 317 | struct ir3_register *src2 = instr->regs[2]; |
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| 318 | struct ir3_register *src3 = instr->regs[3]; |
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| 319 | instr_cat5_t *cat5 = ptr; |
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| 320 | |||
| 321 | iassert(!((dst->flags ^ type_flags(instr->cat5.type)) & IR3_REG_HALF)); |
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| 322 | |||
| 323 | if (src1) { |
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| 324 | cat5->full = ! (src1->flags & IR3_REG_HALF); |
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| 325 | cat5->src1 = reg(src1, info, instr->repeat, IR3_REG_HALF); |
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| 326 | } |
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| 327 | |||
| 328 | |||
| 329 | if (instr->flags & IR3_INSTR_S2EN) { |
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| 330 | if (src2) { |
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| 331 | iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF)); |
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| 332 | cat5->s2en.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF); |
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| 333 | } |
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| 334 | if (src3) { |
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| 335 | iassert(src3->flags & IR3_REG_HALF); |
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| 336 | cat5->s2en.src3 = reg(src3, info, instr->repeat, IR3_REG_HALF); |
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| 337 | } |
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| 338 | iassert(!(instr->cat5.samp | instr->cat5.tex)); |
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| 339 | } else { |
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| 340 | iassert(!src3); |
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| 341 | if (src2) { |
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| 342 | iassert(!((src1->flags ^ src2->flags) & IR3_REG_HALF)); |
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| 343 | cat5->norm.src2 = reg(src2, info, instr->repeat, IR3_REG_HALF); |
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| 344 | } |
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| 345 | cat5->norm.samp = instr->cat5.samp; |
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| 346 | cat5->norm.tex = instr->cat5.tex; |
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| 347 | } |
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| 348 | |||
| 349 | cat5->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF); |
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| 350 | cat5->wrmask = dst->wrmask; |
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| 351 | cat5->type = instr->cat5.type; |
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| 352 | cat5->is_3d = !!(instr->flags & IR3_INSTR_3D); |
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| 353 | cat5->is_a = !!(instr->flags & IR3_INSTR_A); |
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| 354 | cat5->is_s = !!(instr->flags & IR3_INSTR_S); |
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| 355 | cat5->is_s2en = !!(instr->flags & IR3_INSTR_S2EN); |
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| 356 | cat5->is_o = !!(instr->flags & IR3_INSTR_O); |
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| 357 | cat5->is_p = !!(instr->flags & IR3_INSTR_P); |
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| 358 | cat5->opc = instr->opc; |
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| 359 | cat5->jmp_tgt = !!(instr->flags & IR3_INSTR_JP); |
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| 360 | cat5->sync = !!(instr->flags & IR3_INSTR_SY); |
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| 361 | cat5->opc_cat = 5; |
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| 362 | |||
| 363 | return 0; |
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| 364 | } |
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| 365 | |||
| 366 | static int emit_cat6(struct ir3_instruction *instr, void *ptr, |
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| 367 | struct ir3_shader_info *info) |
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| 368 | { |
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| 369 | struct ir3_register *dst = instr->regs[0]; |
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| 370 | struct ir3_register *src = instr->regs[1]; |
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| 371 | instr_cat6_t *cat6 = ptr; |
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| 372 | |||
| 373 | iassert(instr->regs_count == 2); |
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| 374 | |||
| 375 | switch (instr->opc) { |
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| 376 | /* load instructions: */ |
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| 377 | case OPC_LDG: |
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| 378 | case OPC_LDP: |
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| 379 | case OPC_LDL: |
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| 380 | case OPC_LDLW: |
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| 381 | case OPC_LDLV: |
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| 382 | case OPC_PREFETCH: { |
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| 383 | instr_cat6a_t *cat6a = ptr; |
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| 384 | |||
| 385 | iassert(!((dst->flags ^ type_flags(instr->cat6.type)) & IR3_REG_HALF)); |
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| 386 | |||
| 387 | cat6a->must_be_one1 = 1; |
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| 388 | cat6a->must_be_one2 = 1; |
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| 389 | cat6a->off = instr->cat6.offset; |
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| 390 | cat6a->src = reg(src, info, instr->repeat, 0); |
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| 391 | cat6a->dst = reg(dst, info, instr->repeat, IR3_REG_R | IR3_REG_HALF); |
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| 392 | break; |
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| 393 | } |
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| 394 | /* store instructions: */ |
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| 395 | case OPC_STG: |
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| 396 | case OPC_STP: |
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| 397 | case OPC_STL: |
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| 398 | case OPC_STLW: |
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| 399 | case OPC_STI: { |
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| 400 | instr_cat6b_t *cat6b = ptr; |
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| 401 | uint32_t src_flags = type_flags(instr->cat6.type); |
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| 402 | uint32_t dst_flags = (instr->opc == OPC_STI) ? IR3_REG_HALF : 0; |
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| 403 | |||
| 404 | iassert(!((src->flags ^ src_flags) & IR3_REG_HALF)); |
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| 405 | |||
| 406 | cat6b->must_be_one1 = 1; |
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| 407 | cat6b->must_be_one2 = 1; |
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| 408 | cat6b->src = reg(src, info, instr->repeat, src_flags); |
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| 409 | cat6b->off_hi = instr->cat6.offset >> 8; |
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| 410 | cat6b->off = instr->cat6.offset; |
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| 411 | cat6b->dst = reg(dst, info, instr->repeat, IR3_REG_R | dst_flags); |
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| 412 | |||
| 413 | break; |
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| 414 | } |
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| 415 | default: |
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| 416 | // TODO |
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| 417 | break; |
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| 418 | } |
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| 419 | |||
| 420 | cat6->iim_val = instr->cat6.iim_val; |
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| 421 | cat6->type = instr->cat6.type; |
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| 422 | cat6->opc = instr->opc; |
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| 423 | cat6->jmp_tgt = !!(instr->flags & IR3_INSTR_JP); |
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| 424 | cat6->sync = !!(instr->flags & IR3_INSTR_SY); |
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| 425 | cat6->opc_cat = 6; |
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| 426 | |||
| 427 | return 0; |
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| 428 | } |
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| 429 | |||
| 430 | static int (*emit[])(struct ir3_instruction *instr, void *ptr, |
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| 431 | struct ir3_shader_info *info) = { |
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| 432 | emit_cat0, emit_cat1, emit_cat2, emit_cat3, emit_cat4, emit_cat5, emit_cat6, |
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| 433 | }; |
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| 434 | |||
| 435 | void * ir3_shader_assemble(struct ir3_shader *shader, struct ir3_shader_info *info) |
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| 436 | { |
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| 437 | uint32_t *ptr, *dwords; |
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| 438 | uint32_t i; |
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| 439 | |||
| 440 | info->max_reg = -1; |
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| 441 | info->max_half_reg = -1; |
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| 442 | info->max_const = -1; |
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| 443 | |||
| 444 | /* need a integer number of instruction "groups" (sets of four |
||
| 445 | * instructions), so pad out w/ NOPs if needed: |
||
| 446 | */ |
||
| 447 | while (shader->instrs_count != align(shader->instrs_count, 4)) |
||
| 448 | ir3_instr_create(shader, 0, OPC_NOP); |
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| 449 | |||
| 450 | /* each instruction is 64bits: */ |
||
| 451 | info->sizedwords = 2 * shader->instrs_count; |
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| 452 | |||
| 453 | ptr = dwords = calloc(1, 4 * info->sizedwords); |
||
| 454 | |||
| 455 | for (i = 0; i < shader->instrs_count; i++) { |
||
| 456 | struct ir3_instruction *instr = shader->instrs[i]; |
||
| 457 | int ret = emit[instr->category](instr, dwords, info); |
||
| 458 | if (ret) |
||
| 459 | goto fail; |
||
| 460 | dwords += 2; |
||
| 461 | } |
||
| 462 | |||
| 463 | return ptr; |
||
| 464 | |||
| 465 | fail: |
||
| 466 | free(ptr); |
||
| 467 | return NULL; |
||
| 468 | } |
||
| 469 | |||
| 470 | static struct ir3_register * reg_create(struct ir3_shader *shader, |
||
| 471 | int num, int flags) |
||
| 472 | { |
||
| 473 | struct ir3_register *reg = |
||
| 474 | ir3_alloc(shader, sizeof(struct ir3_register)); |
||
| 475 | reg->flags = flags; |
||
| 476 | reg->num = num; |
||
| 477 | return reg; |
||
| 478 | } |
||
| 479 | |||
| 480 | static void insert_instr(struct ir3_shader *shader, |
||
| 481 | struct ir3_instruction *instr) |
||
| 482 | { |
||
| 483 | assert(shader->instrs_count < ARRAY_SIZE(shader->instrs)); |
||
| 484 | shader->instrs[shader->instrs_count++] = instr; |
||
| 485 | } |
||
| 486 | |||
| 487 | struct ir3_instruction * ir3_instr_create(struct ir3_shader *shader, |
||
| 488 | int category, opc_t opc) |
||
| 489 | { |
||
| 490 | struct ir3_instruction *instr = |
||
| 491 | ir3_alloc(shader, sizeof(struct ir3_instruction)); |
||
| 492 | instr->shader = shader; |
||
| 493 | instr->category = category; |
||
| 494 | instr->opc = opc; |
||
| 495 | insert_instr(shader, instr); |
||
| 496 | return instr; |
||
| 497 | } |
||
| 498 | |||
| 499 | struct ir3_instruction * ir3_instr_clone(struct ir3_instruction *instr) |
||
| 500 | { |
||
| 501 | struct ir3_instruction *new_instr = |
||
| 502 | ir3_alloc(instr->shader, sizeof(struct ir3_instruction)); |
||
| 503 | unsigned i; |
||
| 504 | |||
| 505 | *new_instr = *instr; |
||
| 506 | insert_instr(instr->shader, new_instr); |
||
| 507 | |||
| 508 | /* clone registers: */ |
||
| 509 | new_instr->regs_count = 0; |
||
| 510 | for (i = 0; i < instr->regs_count; i++) { |
||
| 511 | struct ir3_register *reg = instr->regs[i]; |
||
| 512 | struct ir3_register *new_reg = |
||
| 513 | ir3_reg_create(new_instr, reg->num, reg->flags); |
||
| 514 | *new_reg = *reg; |
||
| 515 | } |
||
| 516 | |||
| 517 | return new_instr; |
||
| 518 | } |
||
| 519 | |||
| 520 | struct ir3_register * ir3_reg_create(struct ir3_instruction *instr, |
||
| 521 | int num, int flags) |
||
| 522 | { |
||
| 523 | struct ir3_register *reg = reg_create(instr->shader, num, flags); |
||
| 524 | assert(instr->regs_count < ARRAY_SIZE(instr->regs)); |
||
| 525 | instr->regs[instr->regs_count++] = reg; |
||
| 526 | return reg; |
||
| 527 | } |