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| Rev | Author | Line No. | Line |
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| 5564 | serge | 1 | /* |
| 2 | * Copyright © 2009 Intel Corporation |
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| 3 | * |
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| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
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| 5 | * copy of this software and associated documentation files (the "Software"), |
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| 6 | * to deal in the Software without restriction, including without limitation |
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| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
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| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
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| 9 | * Software is furnished to do so, subject to the following conditions: |
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| 10 | * |
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| 11 | * The above copyright notice and this permission notice (including the next |
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| 12 | * paragraph) shall be included in all copies or substantial portions of the |
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| 13 | * Software. |
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| 14 | * |
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| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
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| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
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| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
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| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
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| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
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| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
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| 21 | * IN THE SOFTWARE. |
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| 22 | * |
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| 23 | * Authors: |
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| 24 | * Eric Anholt |
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| 25 | * |
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| 26 | */ |
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| 27 | |||
| 28 | #include "brw_context.h" |
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| 29 | #include "brw_state.h" |
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| 30 | #include "brw_defines.h" |
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| 31 | #include "brw_util.h" |
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| 32 | #include "intel_batchbuffer.h" |
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| 33 | #include "main/macros.h" |
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| 34 | #include "main/enums.h" |
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| 35 | #include "main/glformats.h" |
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| 36 | #include "main/stencil.h" |
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| 37 | |||
| 38 | static void |
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| 39 | gen6_upload_blend_state(struct brw_context *brw) |
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| 40 | { |
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| 41 | bool is_buffer_zero_integer_format = false; |
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| 42 | struct gl_context *ctx = &brw->ctx; |
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| 43 | struct gen6_blend_state *blend; |
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| 44 | int b; |
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| 45 | int nr_draw_buffers = ctx->DrawBuffer->_NumColorDrawBuffers; |
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| 46 | int size; |
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| 47 | |||
| 48 | /* We need at least one BLEND_STATE written, because we might do |
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| 49 | * thread dispatch even if _NumColorDrawBuffers is 0 (for example |
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| 50 | * for computed depth or alpha test), which will do an FB write |
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| 51 | * with render target 0, which will reference BLEND_STATE[0] for |
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| 52 | * alpha test enable. |
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| 53 | */ |
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| 54 | if (nr_draw_buffers == 0 && ctx->Color.AlphaEnabled) |
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| 55 | nr_draw_buffers = 1; |
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| 56 | |||
| 57 | size = sizeof(*blend) * nr_draw_buffers; |
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| 58 | blend = brw_state_batch(brw, AUB_TRACE_BLEND_STATE, |
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| 59 | size, 64, &brw->cc.blend_state_offset); |
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| 60 | |||
| 61 | memset(blend, 0, size); |
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| 62 | |||
| 63 | for (b = 0; b < nr_draw_buffers; b++) { |
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| 64 | /* _NEW_BUFFERS */ |
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| 65 | struct gl_renderbuffer *rb = ctx->DrawBuffer->_ColorDrawBuffers[b]; |
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| 66 | GLenum rb_type; |
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| 67 | bool integer; |
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| 68 | |||
| 69 | if (rb) |
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| 70 | rb_type = _mesa_get_format_datatype(rb->Format); |
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| 71 | else |
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| 72 | rb_type = GL_UNSIGNED_NORMALIZED; |
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| 73 | |||
| 74 | /* Used for implementing the following bit of GL_EXT_texture_integer: |
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| 75 | * "Per-fragment operations that require floating-point color |
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| 76 | * components, including multisample alpha operations, alpha test, |
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| 77 | * blending, and dithering, have no effect when the corresponding |
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| 78 | * colors are written to an integer color buffer." |
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| 79 | */ |
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| 80 | integer = (rb_type == GL_INT || rb_type == GL_UNSIGNED_INT); |
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| 81 | |||
| 82 | if(b == 0 && integer) |
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| 83 | is_buffer_zero_integer_format = true; |
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| 84 | |||
| 85 | /* _NEW_COLOR */ |
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| 86 | if (ctx->Color.ColorLogicOpEnabled) { |
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| 87 | /* Floating point RTs should have no effect from LogicOp, |
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| 88 | * except for disabling of blending, but other types should. |
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| 89 | * |
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| 90 | * However, from the Sandy Bridge PRM, Vol 2 Par 1, Section 8.1.11, |
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| 91 | * "Logic Ops", |
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| 92 | * |
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| 93 | * "Logic Ops are only supported on *_UNORM surfaces (excluding |
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| 94 | * _SRGB variants), otherwise Logic Ops must be DISABLED." |
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| 95 | */ |
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| 96 | WARN_ONCE(ctx->Color.LogicOp != GL_COPY && |
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| 97 | rb_type != GL_UNSIGNED_NORMALIZED && |
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| 98 | rb_type != GL_FLOAT, "Ignoring %s logic op on %s " |
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| 99 | "renderbuffer\n", |
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| 100 | _mesa_lookup_enum_by_nr(ctx->Color.LogicOp), |
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| 101 | _mesa_lookup_enum_by_nr(rb_type)); |
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| 102 | if (rb_type == GL_UNSIGNED_NORMALIZED) { |
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| 103 | blend[b].blend1.logic_op_enable = 1; |
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| 104 | blend[b].blend1.logic_op_func = |
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| 105 | intel_translate_logic_op(ctx->Color.LogicOp); |
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| 106 | } |
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| 107 | } else if (ctx->Color.BlendEnabled & (1 << b) && !integer) { |
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| 108 | GLenum eqRGB = ctx->Color.Blend[b].EquationRGB; |
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| 109 | GLenum eqA = ctx->Color.Blend[b].EquationA; |
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| 110 | GLenum srcRGB = ctx->Color.Blend[b].SrcRGB; |
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| 111 | GLenum dstRGB = ctx->Color.Blend[b].DstRGB; |
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| 112 | GLenum srcA = ctx->Color.Blend[b].SrcA; |
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| 113 | GLenum dstA = ctx->Color.Blend[b].DstA; |
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| 114 | |||
| 115 | if (eqRGB == GL_MIN || eqRGB == GL_MAX) { |
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| 116 | srcRGB = dstRGB = GL_ONE; |
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| 117 | } |
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| 118 | |||
| 119 | if (eqA == GL_MIN || eqA == GL_MAX) { |
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| 120 | srcA = dstA = GL_ONE; |
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| 121 | } |
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| 122 | |||
| 123 | /* Due to hardware limitations, the destination may have information |
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| 124 | * in an alpha channel even when the format specifies no alpha |
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| 125 | * channel. In order to avoid getting any incorrect blending due to |
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| 126 | * that alpha channel, coerce the blend factors to values that will |
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| 127 | * not read the alpha channel, but will instead use the correct |
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| 128 | * implicit value for alpha. |
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| 129 | */ |
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| 130 | if (rb && !_mesa_base_format_has_channel(rb->_BaseFormat, GL_TEXTURE_ALPHA_TYPE)) |
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| 131 | { |
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| 132 | srcRGB = brw_fix_xRGB_alpha(srcRGB); |
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| 133 | srcA = brw_fix_xRGB_alpha(srcA); |
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| 134 | dstRGB = brw_fix_xRGB_alpha(dstRGB); |
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| 135 | dstA = brw_fix_xRGB_alpha(dstA); |
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| 136 | } |
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| 137 | |||
| 138 | blend[b].blend0.dest_blend_factor = brw_translate_blend_factor(dstRGB); |
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| 139 | blend[b].blend0.source_blend_factor = brw_translate_blend_factor(srcRGB); |
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| 140 | blend[b].blend0.blend_func = brw_translate_blend_equation(eqRGB); |
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| 141 | |||
| 142 | blend[b].blend0.ia_dest_blend_factor = brw_translate_blend_factor(dstA); |
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| 143 | blend[b].blend0.ia_source_blend_factor = brw_translate_blend_factor(srcA); |
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| 144 | blend[b].blend0.ia_blend_func = brw_translate_blend_equation(eqA); |
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| 145 | |||
| 146 | blend[b].blend0.blend_enable = 1; |
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| 147 | blend[b].blend0.ia_blend_enable = (srcA != srcRGB || |
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| 148 | dstA != dstRGB || |
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| 149 | eqA != eqRGB); |
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| 150 | } |
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| 151 | |||
| 152 | /* See section 8.1.6 "Pre-Blend Color Clamping" of the |
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| 153 | * SandyBridge PRM Volume 2 Part 1 for HW requirements. |
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| 154 | * |
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| 155 | * We do our ARB_color_buffer_float CLAMP_FRAGMENT_COLOR |
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| 156 | * clamping in the fragment shader. For its clamping of |
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| 157 | * blending, the spec says: |
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| 158 | * |
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| 159 | * "RESOLVED: For fixed-point color buffers, the inputs and |
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| 160 | * the result of the blending equation are clamped. For |
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| 161 | * floating-point color buffers, no clamping occurs." |
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| 162 | * |
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| 163 | * So, generally, we want clamping to the render target's range. |
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| 164 | * And, good news, the hardware tables for both pre- and |
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| 165 | * post-blend color clamping are either ignored, or any are |
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| 166 | * allowed, or clamping is required but RT range clamping is a |
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| 167 | * valid option. |
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| 168 | */ |
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| 169 | blend[b].blend1.pre_blend_clamp_enable = 1; |
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| 170 | blend[b].blend1.post_blend_clamp_enable = 1; |
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| 171 | blend[b].blend1.clamp_range = BRW_RENDERTARGET_CLAMPRANGE_FORMAT; |
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| 172 | |||
| 173 | /* _NEW_COLOR */ |
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| 174 | if (ctx->Color.AlphaEnabled && !integer) { |
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| 175 | blend[b].blend1.alpha_test_enable = 1; |
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| 176 | blend[b].blend1.alpha_test_func = |
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| 177 | intel_translate_compare_func(ctx->Color.AlphaFunc); |
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| 178 | |||
| 179 | } |
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| 180 | |||
| 181 | /* _NEW_COLOR */ |
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| 182 | if (ctx->Color.DitherFlag && !integer) { |
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| 183 | blend[b].blend1.dither_enable = 1; |
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| 184 | blend[b].blend1.y_dither_offset = 0; |
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| 185 | blend[b].blend1.x_dither_offset = 0; |
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| 186 | } |
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| 187 | |||
| 188 | blend[b].blend1.write_disable_r = !ctx->Color.ColorMask[b][0]; |
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| 189 | blend[b].blend1.write_disable_g = !ctx->Color.ColorMask[b][1]; |
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| 190 | blend[b].blend1.write_disable_b = !ctx->Color.ColorMask[b][2]; |
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| 191 | blend[b].blend1.write_disable_a = !ctx->Color.ColorMask[b][3]; |
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| 192 | |||
| 193 | /* OpenGL specification 3.3 (page 196), section 4.1.3 says: |
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| 194 | * "If drawbuffer zero is not NONE and the buffer it references has an |
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| 195 | * integer format, the SAMPLE_ALPHA_TO_COVERAGE and SAMPLE_ALPHA_TO_ONE |
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| 196 | * operations are skipped." |
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| 197 | */ |
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| 198 | if(!is_buffer_zero_integer_format) { |
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| 199 | /* _NEW_MULTISAMPLE */ |
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| 200 | blend[b].blend1.alpha_to_coverage = |
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| 201 | ctx->Multisample._Enabled && ctx->Multisample.SampleAlphaToCoverage; |
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| 202 | |||
| 203 | /* From SandyBridge PRM, volume 2 Part 1, section 8.2.3, BLEND_STATE: |
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| 204 | * DWord 1, Bit 30 (AlphaToOne Enable): |
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| 205 | * "If Dual Source Blending is enabled, this bit must be disabled" |
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| 206 | */ |
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| 207 | WARN_ONCE(ctx->Color.Blend[b]._UsesDualSrc && |
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| 208 | ctx->Multisample._Enabled && |
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| 209 | ctx->Multisample.SampleAlphaToOne, |
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| 210 | "HW workaround: disabling alpha to one with dual src " |
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| 211 | "blending\n"); |
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| 212 | if (ctx->Color.Blend[b]._UsesDualSrc) |
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| 213 | blend[b].blend1.alpha_to_one = false; |
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| 214 | else |
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| 215 | blend[b].blend1.alpha_to_one = |
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| 216 | ctx->Multisample._Enabled && ctx->Multisample.SampleAlphaToOne; |
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| 217 | |||
| 218 | blend[b].blend1.alpha_to_coverage_dither = (brw->gen >= 7); |
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| 219 | } |
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| 220 | else { |
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| 221 | blend[b].blend1.alpha_to_coverage = false; |
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| 222 | blend[b].blend1.alpha_to_one = false; |
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| 223 | } |
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| 224 | } |
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| 225 | |||
| 226 | /* Point the GPU at the new indirect state. */ |
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| 227 | if (brw->gen == 6) { |
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| 228 | BEGIN_BATCH(4); |
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| 229 | OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2)); |
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| 230 | OUT_BATCH(brw->cc.blend_state_offset | 1); |
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| 231 | OUT_BATCH(0); |
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| 232 | OUT_BATCH(0); |
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| 233 | ADVANCE_BATCH(); |
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| 234 | } else { |
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| 235 | BEGIN_BATCH(2); |
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| 236 | OUT_BATCH(_3DSTATE_BLEND_STATE_POINTERS << 16 | (2 - 2)); |
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| 237 | OUT_BATCH(brw->cc.blend_state_offset | 1); |
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| 238 | ADVANCE_BATCH(); |
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| 239 | } |
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| 240 | } |
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| 241 | |||
| 242 | const struct brw_tracked_state gen6_blend_state = { |
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| 243 | .dirty = { |
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| 244 | .mesa = _NEW_BUFFERS | |
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| 245 | _NEW_COLOR | |
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| 246 | _NEW_MULTISAMPLE, |
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| 247 | .brw = BRW_NEW_BATCH | |
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| 248 | BRW_NEW_STATE_BASE_ADDRESS, |
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| 249 | }, |
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| 250 | .emit = gen6_upload_blend_state, |
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| 251 | }; |
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| 252 | |||
| 253 | static void |
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| 254 | gen6_upload_color_calc_state(struct brw_context *brw) |
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| 255 | { |
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| 256 | struct gl_context *ctx = &brw->ctx; |
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| 257 | struct gen6_color_calc_state *cc; |
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| 258 | |||
| 259 | cc = brw_state_batch(brw, AUB_TRACE_CC_STATE, |
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| 260 | sizeof(*cc), 64, &brw->cc.state_offset); |
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| 261 | memset(cc, 0, sizeof(*cc)); |
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| 262 | |||
| 263 | /* _NEW_COLOR */ |
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| 264 | cc->cc0.alpha_test_format = BRW_ALPHATEST_FORMAT_UNORM8; |
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| 265 | UNCLAMPED_FLOAT_TO_UBYTE(cc->cc1.alpha_ref_fi.ui, ctx->Color.AlphaRef); |
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| 266 | |||
| 267 | if (brw->gen < 9) { |
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| 268 | /* _NEW_STENCIL */ |
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| 269 | cc->cc0.stencil_ref = _mesa_get_stencil_ref(ctx, 0); |
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| 270 | cc->cc0.bf_stencil_ref = |
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| 271 | _mesa_get_stencil_ref(ctx, ctx->Stencil._BackFace); |
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| 272 | } |
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| 273 | |||
| 274 | /* _NEW_COLOR */ |
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| 275 | cc->constant_r = ctx->Color.BlendColorUnclamped[0]; |
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| 276 | cc->constant_g = ctx->Color.BlendColorUnclamped[1]; |
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| 277 | cc->constant_b = ctx->Color.BlendColorUnclamped[2]; |
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| 278 | cc->constant_a = ctx->Color.BlendColorUnclamped[3]; |
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| 279 | |||
| 280 | /* Point the GPU at the new indirect state. */ |
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| 281 | if (brw->gen == 6) { |
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| 282 | BEGIN_BATCH(4); |
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| 283 | OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (4 - 2)); |
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| 284 | OUT_BATCH(0); |
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| 285 | OUT_BATCH(0); |
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| 286 | OUT_BATCH(brw->cc.state_offset | 1); |
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| 287 | ADVANCE_BATCH(); |
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| 288 | } else { |
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| 289 | BEGIN_BATCH(2); |
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| 290 | OUT_BATCH(_3DSTATE_CC_STATE_POINTERS << 16 | (2 - 2)); |
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| 291 | OUT_BATCH(brw->cc.state_offset | 1); |
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| 292 | ADVANCE_BATCH(); |
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| 293 | } |
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| 294 | } |
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| 295 | |||
| 296 | const struct brw_tracked_state gen6_color_calc_state = { |
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| 297 | .dirty = { |
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| 298 | .mesa = _NEW_COLOR | |
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| 299 | _NEW_STENCIL, |
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| 300 | .brw = BRW_NEW_BATCH | |
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| 301 | BRW_NEW_STATE_BASE_ADDRESS, |
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| 302 | }, |
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| 303 | .emit = gen6_upload_color_calc_state, |
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| 304 | }; |