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5564 | serge | 1 | #ifndef __NV40_SHADER_H__ |
2 | #define __NV40_SHADER_H__ |
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3 | |||
4 | /* Vertex programs instruction set |
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5 | * |
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6 | * The NV40 instruction set is very similar to NV30. Most fields are in |
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7 | * a slightly different position in the instruction however. |
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8 | * |
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9 | * Merged instructions |
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10 | * In some cases it is possible to put two instructions into one opcode |
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11 | * slot. The rules for when this is OK is not entirely clear to me yet. |
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12 | * |
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13 | * There are separate writemasks and dest temp register fields for each |
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14 | * grouping of instructions. There is however only one field with the |
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15 | * ID of a result register. Writing to temp/result regs is selected by |
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16 | * setting VEC_RESULT/SCA_RESULT. |
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17 | * |
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18 | * Temporary registers |
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19 | * The source/dest temp register fields have been extended by 1 bit, to |
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20 | * give a total of 32 temporary registers. |
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21 | * |
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22 | * Relative Addressing |
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23 | * NV40 can use an address register to index into vertex attribute regs. |
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24 | * This is done by putting the offset value into INPUT_SRC and setting |
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25 | * the INDEX_INPUT flag. |
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26 | * |
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27 | * Conditional execution (see NV_vertex_program{2,3} for details) |
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28 | * There is a second condition code register on NV40, it's use is enabled |
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29 | * by setting the COND_REG_SELECT_1 flag. |
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30 | * |
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31 | * Texture lookup |
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32 | * TODO |
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33 | */ |
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34 | |||
35 | /* ---- OPCODE BITS 127:96 / data DWORD 0 --- */ |
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36 | #define NV40_VP_INST_VEC_RESULT (1 << 30) |
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37 | /* uncertain.. */ |
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38 | #define NV40_VP_INST_COND_UPDATE_ENABLE ((1 << 14)|1<<29) |
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39 | /* use address reg as index into attribs */ |
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40 | #define NV40_VP_INST_INDEX_INPUT (1 << 27) |
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41 | #define NV40_VP_INST_SATURATE (1 << 26) |
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42 | #define NV40_VP_INST_COND_REG_SELECT_1 (1 << 25) |
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43 | #define NV40_VP_INST_ADDR_REG_SELECT_1 (1 << 24) |
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44 | #define NV40_VP_INST_SRC2_ABS (1 << 23) |
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45 | #define NV40_VP_INST_SRC1_ABS (1 << 22) |
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46 | #define NV40_VP_INST_SRC0_ABS (1 << 21) |
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47 | #define NV40_VP_INST_VEC_DEST_TEMP_SHIFT 15 |
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48 | #define NV40_VP_INST_VEC_DEST_TEMP_MASK (0x3F << 15) |
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49 | #define NV40_VP_INST_COND_TEST_ENABLE (1 << 13) |
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50 | #define NV40_VP_INST_COND_SHIFT 10 |
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51 | #define NV40_VP_INST_COND_MASK (0x7 << 10) |
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52 | #define NV40_VP_INST_COND_SWZ_X_SHIFT 8 |
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53 | #define NV40_VP_INST_COND_SWZ_X_MASK (3 << 8) |
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54 | #define NV40_VP_INST_COND_SWZ_Y_SHIFT 6 |
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55 | #define NV40_VP_INST_COND_SWZ_Y_MASK (3 << 6) |
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56 | #define NV40_VP_INST_COND_SWZ_Z_SHIFT 4 |
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57 | #define NV40_VP_INST_COND_SWZ_Z_MASK (3 << 4) |
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58 | #define NV40_VP_INST_COND_SWZ_W_SHIFT 2 |
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59 | #define NV40_VP_INST_COND_SWZ_W_MASK (3 << 2) |
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60 | #define NV40_VP_INST_COND_SWZ_ALL_SHIFT 2 |
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61 | #define NV40_VP_INST_COND_SWZ_ALL_MASK (0xFF << 2) |
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62 | #define NV40_VP_INST_ADDR_SWZ_SHIFT 0 |
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63 | #define NV40_VP_INST_ADDR_SWZ_MASK (0x03 << 0) |
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64 | #define NV40_VP_INST0_KNOWN ( \ |
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65 | NV40_VP_INST_INDEX_INPUT | \ |
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66 | NV40_VP_INST_COND_REG_SELECT_1 | \ |
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67 | NV40_VP_INST_ADDR_REG_SELECT_1 | \ |
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68 | NV40_VP_INST_SRC2_ABS | \ |
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69 | NV40_VP_INST_SRC1_ABS | \ |
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70 | NV40_VP_INST_SRC0_ABS | \ |
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71 | NV40_VP_INST_VEC_DEST_TEMP_MASK | \ |
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72 | NV40_VP_INST_COND_TEST_ENABLE | \ |
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73 | NV40_VP_INST_COND_MASK | \ |
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74 | NV40_VP_INST_COND_SWZ_ALL_MASK | \ |
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75 | NV40_VP_INST_ADDR_SWZ_MASK) |
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76 | |||
77 | /* ---- OPCODE BITS 95:64 / data DWORD 1 --- */ |
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78 | #define NV40_VP_INST_VEC_OPCODE_SHIFT 22 |
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79 | #define NV40_VP_INST_VEC_OPCODE_MASK (0x1F << 22) |
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80 | #define NV40_VP_INST_SCA_OPCODE_SHIFT 27 |
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81 | #define NV40_VP_INST_SCA_OPCODE_MASK (0x1F << 27) |
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82 | #define NV40_VP_INST_CONST_SRC_SHIFT 12 |
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83 | #define NV40_VP_INST_CONST_SRC_MASK (0xFF << 12) |
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84 | #define NV40_VP_INST_INPUT_SRC_SHIFT 8 |
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85 | #define NV40_VP_INST_INPUT_SRC_MASK (0x0F << 8) |
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86 | #define NV40_VP_INST_SRC0H_SHIFT 0 |
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87 | #define NV40_VP_INST_SRC0H_MASK (0xFF << 0) |
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88 | #define NV40_VP_INST1_KNOWN ( \ |
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89 | NV40_VP_INST_VEC_OPCODE_MASK | \ |
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90 | NV40_VP_INST_SCA_OPCODE_MASK | \ |
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91 | NV40_VP_INST_CONST_SRC_MASK | \ |
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92 | NV40_VP_INST_INPUT_SRC_MASK | \ |
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93 | NV40_VP_INST_SRC0H_MASK \ |
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94 | ) |
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95 | |||
96 | /* ---- OPCODE BITS 63:32 / data DWORD 2 --- */ |
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97 | #define NV40_VP_INST_SRC0L_SHIFT 23 |
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98 | #define NV40_VP_INST_SRC0L_MASK (0x1FF << 23) |
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99 | #define NV40_VP_INST_SRC1_SHIFT 6 |
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100 | #define NV40_VP_INST_SRC1_MASK (0x1FFFF << 6) |
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101 | #define NV40_VP_INST_SRC2H_SHIFT 0 |
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102 | #define NV40_VP_INST_SRC2H_MASK (0x3F << 0) |
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103 | #define NV40_VP_INST_IADDRH_SHIFT 0 |
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104 | #define NV40_VP_INST_IADDRH_MASK (0x3F << 0) |
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105 | |||
106 | /* ---- OPCODE BITS 31:0 / data DWORD 3 --- */ |
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107 | #define NV40_VP_INST_IADDRL_SHIFT 29 |
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108 | #define NV40_VP_INST_IADDRL_MASK (7 << 29) |
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109 | #define NV40_VP_INST_SRC2L_SHIFT 21 |
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110 | #define NV40_VP_INST_SRC2L_MASK (0x7FF << 21) |
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111 | #define NV40_VP_INST_SCA_WRITEMASK_SHIFT 17 |
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112 | #define NV40_VP_INST_SCA_WRITEMASK_MASK (0xF << 17) |
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113 | # define NV40_VP_INST_SCA_WRITEMASK_X (1 << 20) |
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114 | # define NV40_VP_INST_SCA_WRITEMASK_Y (1 << 19) |
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115 | # define NV40_VP_INST_SCA_WRITEMASK_Z (1 << 18) |
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116 | # define NV40_VP_INST_SCA_WRITEMASK_W (1 << 17) |
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117 | #define NV40_VP_INST_VEC_WRITEMASK_SHIFT 13 |
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118 | #define NV40_VP_INST_VEC_WRITEMASK_MASK (0xF << 13) |
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119 | # define NV40_VP_INST_VEC_WRITEMASK_X (1 << 16) |
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120 | # define NV40_VP_INST_VEC_WRITEMASK_Y (1 << 15) |
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121 | # define NV40_VP_INST_VEC_WRITEMASK_Z (1 << 14) |
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122 | # define NV40_VP_INST_VEC_WRITEMASK_W (1 << 13) |
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123 | #define NV40_VP_INST_SCA_RESULT (1 << 12) |
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124 | #define NV40_VP_INST_SCA_DEST_TEMP_SHIFT 7 |
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125 | #define NV40_VP_INST_SCA_DEST_TEMP_MASK (0x1F << 7) |
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126 | #define NV40_VP_INST_DEST_SHIFT 2 |
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127 | #define NV40_VP_INST_DEST_MASK (31 << 2) |
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128 | # define NV40_VP_INST_DEST_POS 0 |
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129 | # define NV40_VP_INST_DEST_COL0 1 |
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130 | # define NV40_VP_INST_DEST_COL1 2 |
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131 | # define NV40_VP_INST_DEST_BFC0 3 |
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132 | # define NV40_VP_INST_DEST_BFC1 4 |
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133 | # define NV40_VP_INST_DEST_FOGC 5 |
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134 | # define NV40_VP_INST_DEST_PSZ 6 |
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135 | # define NV40_VP_INST_DEST_TC0 7 |
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136 | # define NV40_VP_INST_DEST_TC(n) (7+n) |
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137 | # define NV40_VP_INST_DEST_TEMP 0x1F |
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138 | #define NV40_VP_INST_INDEX_CONST (1 << 1) |
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139 | #define NV40_VP_INST3_KNOWN ( \ |
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140 | NV40_VP_INST_SRC2L_MASK |\ |
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141 | NV40_VP_INST_SCA_WRITEMASK_MASK |\ |
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142 | NV40_VP_INST_VEC_WRITEMASK_MASK |\ |
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143 | NV40_VP_INST_SCA_DEST_TEMP_MASK |\ |
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144 | NV40_VP_INST_DEST_MASK |\ |
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145 | NV40_VP_INST_INDEX_CONST) |
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146 | |||
147 | /* Useful to split the source selection regs into their pieces */ |
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148 | #define NV40_VP_SRC0_HIGH_SHIFT 9 |
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149 | #define NV40_VP_SRC0_HIGH_MASK 0x0001FE00 |
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150 | #define NV40_VP_SRC0_LOW_MASK 0x000001FF |
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151 | #define NV40_VP_SRC2_HIGH_SHIFT 11 |
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152 | #define NV40_VP_SRC2_HIGH_MASK 0x0001F800 |
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153 | #define NV40_VP_SRC2_LOW_MASK 0x000007FF |
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154 | |||
155 | /* Source selection - these are the bits you fill NV40_VP_INST_SRCn with */ |
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156 | #define NV40_VP_SRC_NEGATE (1 << 16) |
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157 | #define NV40_VP_SRC_SWZ_X_SHIFT 14 |
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158 | #define NV40_VP_SRC_SWZ_X_MASK (3 << 14) |
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159 | #define NV40_VP_SRC_SWZ_Y_SHIFT 12 |
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160 | #define NV40_VP_SRC_SWZ_Y_MASK (3 << 12) |
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161 | #define NV40_VP_SRC_SWZ_Z_SHIFT 10 |
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162 | #define NV40_VP_SRC_SWZ_Z_MASK (3 << 10) |
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163 | #define NV40_VP_SRC_SWZ_W_SHIFT 8 |
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164 | #define NV40_VP_SRC_SWZ_W_MASK (3 << 8) |
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165 | #define NV40_VP_SRC_SWZ_ALL_SHIFT 8 |
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166 | #define NV40_VP_SRC_SWZ_ALL_MASK (0xFF << 8) |
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167 | #define NV40_VP_SRC_TEMP_SRC_SHIFT 2 |
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168 | #define NV40_VP_SRC_TEMP_SRC_MASK (0x1F << 2) |
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169 | #define NV40_VP_SRC_REG_TYPE_SHIFT 0 |
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170 | #define NV40_VP_SRC_REG_TYPE_MASK (3 << 0) |
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171 | # define NV40_VP_SRC_REG_TYPE_UNK0 0 |
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172 | # define NV40_VP_SRC_REG_TYPE_TEMP 1 |
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173 | # define NV40_VP_SRC_REG_TYPE_INPUT 2 |
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174 | # define NV40_VP_SRC_REG_TYPE_CONST 3 |
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175 | |||
176 | #include "nv30/nvfx_shader.h" |
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177 | |||
178 | #endif><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>><>29) |