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Rev | Author | Line No. | Line |
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8327 | maxcodehac | 1 | #ifndef _CPU_H_ |
2 | #define _CPU_H_ |
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3 | |||
4 | |||
5 | //#define ARM_V6 //define to allow v6 instructions |
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6 | //#define THUMB_2 //define to allow Thumb2 |
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7 | |||
8 | #include "types.h" |
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9 | |||
10 | struct ArmCpu; |
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11 | |||
12 | #define ARM_SR_N 0x80000000UL |
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13 | #define ARM_SR_Z 0x40000000UL |
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14 | #define ARM_SR_C 0x20000000UL |
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15 | #define ARM_SR_V 0x10000000UL |
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16 | #define ARM_SR_Q 0x08000000UL |
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17 | #ifdef ARM_V6 //V6KT2, but without T2 to be exact (we implement things like MLS, but not Thumb2 or ThumbEE) |
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18 | #define ARM_SR_J 0x01000000UL |
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19 | #define ARM_SR_E 0x00000200UL |
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20 | #define ARM_SR_A 0x00000100UL |
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21 | #define ARM_SR_GE_0 0x00010000UL |
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22 | #define ARM_SR_GE_1 0x00020000UL |
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23 | #define ARM_SR_GE_2 0x00040000UL |
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24 | #define ARM_SR_GE_3 0x00080000UL |
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25 | #define ARM_SR_GE_MASK 0x000F0000UL |
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26 | #define ARM_SR_GE_SHIFT 16 |
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27 | #endif |
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28 | #define ARM_SR_I 0x00000080UL |
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29 | #define ARM_SR_F 0x00000040UL |
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30 | #define ARM_SR_T 0x00000020UL |
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31 | #define ARM_SR_M 0x0000001FUL |
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32 | |||
33 | #define ARM_SR_MODE_USR 0x00000010UL |
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34 | #define ARM_SR_MODE_FIQ 0x00000011UL |
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35 | #define ARM_SR_MODE_IRQ 0x00000012UL |
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36 | #define ARM_SR_MODE_SVC 0x00000013UL |
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37 | #define ARM_SR_MODE_ABT 0x00000017UL |
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38 | #define ARM_SR_MODE_UND 0x0000001BUL |
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39 | #define ARM_SR_MODE_SYS 0x0000001FUL |
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40 | |||
41 | #define ARV_VECTOR_OFFT_RST 0x00000000UL |
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42 | #define ARM_VECTOR_OFFT_UND 0x00000004UL |
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43 | #define ARM_VECTOR_OFFT_SWI 0x00000008UL |
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44 | #define ARM_VECTOR_OFFT_P_ABT 0x0000000CUL |
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45 | #define ARM_VECTOR_OFFT_D_ABT 0x00000010UL |
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46 | #define ARM_VECTOR_OFFT_UNUSED 0x00000014UL |
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47 | #define ARM_VECTOR_OFFT_IRQ 0x00000018UL |
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48 | #define ARM_VECTOR_OFFT_FIQ 0x0000001CUL |
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49 | |||
50 | #define HYPERCALL_ARM 0xF7BBBBBBUL |
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51 | #define HYPERCALL_THUMB 0xBBBBUL |
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52 | |||
53 | //the following are for cpuGetRegExternal() and are generally used for debugging purposes |
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54 | #define ARM_REG_NUM_CPSR 16 |
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55 | #define ARM_REG_NUM_SPSR 17 |
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56 | |||
57 | struct ArmCpu; |
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58 | |||
59 | typedef Boolean (*ArmCoprocRegXferF) (struct ArmCpu* cpu, void* userData, Boolean two/* MCR2/MRC2 ? */, Boolean MRC, UInt8 op1, UInt8 Rx, UInt8 CRn, UInt8 CRm, UInt8 op2); |
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60 | typedef Boolean (*ArmCoprocDatProcF) (struct ArmCpu* cpu, void* userData, Boolean two/* CDP2 ? */, UInt8 op1, UInt8 CRd, UInt8 CRn, UInt8 CRm, UInt8 op2); |
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61 | typedef Boolean (*ArmCoprocMemAccsF) (struct ArmCpu* cpu, void* userData, Boolean two /* LDC2/STC2 ? */, Boolean N, Boolean store, UInt8 CRd, UInt32 addr, UInt8* option /* NULL if none */); |
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62 | typedef Boolean (*ArmCoprocTwoRegF) (struct ArmCpu* cpu, void* userData, Boolean MRRC, UInt8 op, UInt8 Rd, UInt8 Rn, UInt8 CRm); |
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63 | |||
64 | typedef Boolean (*ArmCpuMemF) (struct ArmCpu* cpu, void* buf, UInt32 vaddr, UInt8 size, Boolean write, Boolean priviledged, UInt8* fsr); //read/write |
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65 | typedef Boolean (*ArmCpuHypercall) (struct ArmCpu* cpu); //return true if handled |
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66 | typedef void (*ArmCpuEmulErr) (struct ArmCpu* cpu, const char* err_str); |
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67 | |||
68 | typedef void (*ArmSetFaultAdrF) (struct ArmCpu* cpu, UInt32 adr, UInt8 faultStatus); |
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69 | |||
70 | #include "icache.h" |
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71 | |||
72 | |||
73 | /* |
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74 | |||
75 | coprocessors: |
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76 | |||
77 | |||
78 | 0, 1 - WMMX (pxa only) |
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79 | 11 - VFP (arm standard) |
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80 | 15 - system control (arm standard) |
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81 | */ |
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82 | |||
83 | |||
84 | typedef struct{ |
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85 | |||
86 | ArmCoprocRegXferF regXfer; |
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87 | ArmCoprocDatProcF dataProcessing; |
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88 | ArmCoprocMemAccsF memAccess; |
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89 | ArmCoprocTwoRegF twoRegF; |
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90 | void* userData; |
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91 | |||
92 | }ArmCoprocessor; |
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93 | |||
94 | typedef struct{ |
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95 | |||
96 | UInt32 R13, R14; |
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97 | UInt32 SPSR; //usr mode doesn't have an SPSR |
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98 | }ArmBankedRegs; |
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99 | |||
100 | |||
101 | |||
102 | |||
103 | |||
104 | |||
105 | |||
106 | |||
107 | typedef struct ArmCpu{ |
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108 | |||
109 | UInt32 regs[16]; //current active regs as per current mode |
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110 | UInt32 CPSR, SPSR; |
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111 | |||
112 | ArmBankedRegs bank_usr; //usr regs when in another mode |
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113 | ArmBankedRegs bank_svc; //svc regs when in another mode |
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114 | ArmBankedRegs bank_abt; //abt regs when in another mode |
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115 | ArmBankedRegs bank_und; //und regs when in another mode |
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116 | ArmBankedRegs bank_irq; //irq regs when in another mode |
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117 | ArmBankedRegs bank_fiq; //fiq regs when in another mode |
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118 | UInt32 extra_regs[5]; //fiq regs when not in fiq mode, usr regs when in fiq mode. R8-12 |
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119 | |||
120 | UInt16 waitingIrqs; |
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121 | UInt16 waitingFiqs; |
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122 | UInt16 CPAR; |
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123 | |||
124 | ArmCoprocessor coproc[16]; //coprocessors |
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125 | |||
126 | // various other cpu config options |
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127 | UInt32 vectorBase; //address of vector base |
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128 | |||
129 | #ifdef ARM_V6 |
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130 | |||
131 | Boolean EEE; //endianness one exception entry |
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132 | Boolean impreciseAbtWaiting; |
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133 | #endif |
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134 | |||
135 | ArmCpuMemF memF; |
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136 | ArmCpuEmulErr emulErrF; |
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137 | ArmCpuHypercall hypercallF; |
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138 | ArmSetFaultAdrF setFaultAdrF; |
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139 | |||
140 | icache ic; |
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141 | |||
142 | void* userData; //shared by all callbacks |
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143 | }ArmCpu; |
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144 | |||
145 | |||
146 | Err cpuInit(ArmCpu* cpu, UInt32 pc, ArmCpuMemF memF, ArmCpuEmulErr emulErrF, ArmCpuHypercall hypercallF, ArmSetFaultAdrF setFaultAdrF); |
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147 | Err cpuDeinit(ArmCpu* cp); |
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148 | void cpuCycle(ArmCpu* cpu); |
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149 | void cpuIrq(ArmCpu* cpu, Boolean fiq, Boolean raise); //unraise when acknowledged |
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150 | |||
151 | #ifdef ARM_V6 |
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152 | |||
153 | void cpuSignalImpreciseAbt(ArmCpu* cpu, Boolean raise); |
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154 | |||
155 | #endif |
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156 | |||
157 | UInt32 cpuGetRegExternal(ArmCpu* cpu, UInt8 reg); |
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158 | void cpuSetReg(ArmCpu* cpu, UInt8 reg, UInt32 val); |
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159 | |||
160 | void cpuCoprocessorRegister(ArmCpu* cpu, UInt8 cpNum, ArmCoprocessor* coproc); |
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161 | void cpuCoprocessorUnregister(ArmCpu* cpu, UInt8 cpNum); |
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162 | |||
163 | void cpuSetVectorAddr(ArmCpu* cpu, UInt32 adr); |
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164 | |||
165 | UInt16 cpuGetCPAR(ArmCpu* cpu); |
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166 | void cpuSetCPAR(ArmCpu* cpu, UInt16 cpar); |
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167 | |||
168 | void cpuIcacheInval(ArmCpu* cpu); |
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169 | void cpuIcacheInvalAddr(ArmCpu* cpu, UInt32 addr); |
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170 | |||
171 | |||
172 | #endif |
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173 |